sync with head yamt-nfs-mp
authoryamt <yamt@NetBSD.org>
Sat, 09 Oct 2010 03:31:35 +0000
branchyamt-nfs-mp
changeset 278948 23584fbbbc9a
parent 278947 490e3e5acefe
child 278949 3222a074add9
sync with head
sys/arch/alpha/alpha/dec_6600.c
sys/arch/alpha/common/sgmap_typedep.c
sys/arch/alpha/include/alpha_cpu.h
sys/arch/alpha/include/elf_machdep.h
sys/arch/alpha/include/logout.h
sys/arch/alpha/pci/tsc.c
sys/arch/alpha/pci/tsp_pci.c
sys/arch/alpha/pci/tsreg.h
sys/arch/alpha/pci/tsvar.h
sys/arch/alpha/stand/common/boot.c
sys/arch/alpha/stand/ustarboot/Makefile
sys/arch/amd64/amd64/machdep.c
sys/arch/amd64/amd64/netbsd32_machdep.c
sys/arch/amd64/conf/GENERIC
sys/arch/amd64/conf/XEN3_DOM0
sys/arch/amd64/conf/XEN3_DOMU
sys/arch/amd64/include/segments.h
sys/arch/amiga/conf/std.amiga
sys/arch/arm/arm/cpufunc.c
sys/arch/arm/arm/cpufunc_asm_sheeva.S
sys/arch/arm/arm32/cpu.c
sys/arch/arm/conf/files.arm
sys/arch/arm/include/armreg.h
sys/arch/arm/include/cpuconf.h
sys/arch/arm/include/cpufunc.h
sys/arch/arm/marvell/files.marvell
sys/arch/arm/marvell/kirkwood.c
sys/arch/arm/marvell/kirkwoodreg.h
sys/arch/arm/marvell/mv78xx0reg.h
sys/arch/arm/marvell/mvsoc.c
sys/arch/arm/marvell/mvsoc_dma.c
sys/arch/arm/marvell/mvsoc_intr.c
sys/arch/arm/marvell/mvsoc_intr.h
sys/arch/arm/marvell/mvsoc_space.c
sys/arch/arm/marvell/mvsocgpp.c
sys/arch/arm/marvell/mvsocgppreg.h
sys/arch/arm/marvell/mvsocgppvar.h
sys/arch/arm/marvell/mvsocreg.h
sys/arch/arm/marvell/mvsoctmr.c
sys/arch/arm/marvell/mvsoctmrreg.h
sys/arch/arm/marvell/mvsocvar.h
sys/arch/arm/marvell/orion.c
sys/arch/arm/marvell/orionreg.h
sys/arch/arm/marvell/pci_machdep.c
sys/arch/arm/omap/files.omap2
sys/arch/arm/omap/omap2_gpmc.c
sys/arch/arm/omap/omap2_gpmcreg.h
sys/arch/arm/omap/omap2_gpmcvar.h
sys/arch/arm/omap/omap2_intr.h
sys/arch/arm/omap/omap2_obio.c
sys/arch/arm/omap/omap2_prcm.c
sys/arch/arm/omap/omap2_prcm.h
sys/arch/arm/omap/omap2_reg.h
sys/arch/arm/omap/omapfb.c
sys/arch/arm/omap/omapfbreg.h
sys/arch/arm/pic/pic.c
sys/arch/arm/sa11x0/sa11x0_com.c
sys/arch/arm/xscale/pxa2x0_mci.c
sys/arch/atari/conf/std.atari
sys/arch/atari/conf/std.hades
sys/arch/atari/conf/std.milan
sys/arch/atari/stand/tostools/libtos/exec_elf.h
sys/arch/cesfic/conf/std.cesfic
sys/arch/dreamcast/conf/GENERIC
sys/arch/dreamcast/conf/Makefile.dreamcast.inc
sys/arch/dreamcast/dev/g2/g2rtc.c
sys/arch/dreamcast/dev/gdrom.c
sys/arch/evbarm/beagle/beagle_machdep.c
sys/arch/evbarm/conf/BEAGLEBOARD
sys/arch/evbarm/conf/DEVKIT8000
sys/arch/evbarm/conf/DNS323
sys/arch/evbarm/conf/GUMSTIX
sys/arch/evbarm/conf/KUROBOX_PRO
sys/arch/evbarm/conf/MARVELL_NAS
sys/arch/evbarm/conf/OVERO
sys/arch/evbarm/conf/SHEEVAPLUG
sys/arch/evbarm/conf/files.devkit8000
sys/arch/evbarm/conf/files.evbarm
sys/arch/evbarm/conf/files.g42xxeb
sys/arch/evbarm/conf/files.gumstix
sys/arch/evbarm/conf/files.marvell
sys/arch/evbarm/conf/files.overo
sys/arch/evbarm/conf/mk.marvell
sys/arch/evbarm/conf/std.marvell
sys/arch/evbarm/devkit8000/if_dme_gpmc.c
sys/arch/evbarm/gumstix/gumstix_machdep.c
sys/arch/evbarm/gumstix/gumstix_start.S
sys/arch/evbarm/gumstix/gumstixreg.h
sys/arch/evbarm/gumstix/gxio.c
sys/arch/evbarm/gumstix/if_sm_gxio.c
sys/arch/evbarm/gumstix/if_smsh_gpmc.c
sys/arch/evbarm/gumstix/if_smsh_gxio.c
sys/arch/evbarm/marvell/marvell_machdep.c
sys/arch/evbarm/marvell/marvell_start.S
sys/arch/evbarm/marvell/marvellreg.h
sys/arch/evbarm/marvell/marvellvar.h
sys/arch/hp300/conf/std.hp300
sys/arch/hp700/conf/GENERIC
sys/arch/hpcarm/conf/INSTALL_JORNADA720
sys/arch/hpcarm/conf/WZERO3
sys/arch/hpcarm/dev/j720pcic.c
sys/arch/hppa/include/ieee.h
sys/arch/i386/conf/ALL
sys/arch/i386/conf/GENERIC
sys/arch/i386/conf/MONOLITHIC
sys/arch/i386/conf/XEN3_DOM0
sys/arch/i386/conf/XEN3_DOMU
sys/arch/i386/i386/dumpsys.c
sys/arch/i386/i386/machdep.c
sys/arch/i386/include/kcore.h
sys/arch/i386/include/pte.h
sys/arch/i386/include/types.h
sys/arch/i386/stand/boot/Makefile.boot
sys/arch/i386/stand/bootxx/Makefile
sys/arch/i386/stand/bootxx/bootxx_ext2fs/Makefile
sys/arch/i386/stand/lib/exec.c
sys/arch/luna68k/conf/std.luna68k
sys/arch/m68k/conf/files.m68k
sys/arch/m68k/conf/std.m68k
sys/arch/m68k/include/ieee.h
sys/arch/m68k/m68k/cpu_in_cksum.c
sys/arch/m68k/m68k/in_cksum.c
sys/arch/mac68k/conf/std.mac68k
sys/arch/macppc/dev/awacs.c
sys/arch/macppc/dev/pmu.c
sys/arch/macppc/dev/smartbat.c
sys/arch/macppc/dev/snapper.c
sys/arch/macppc/macppc/machdep.c
sys/arch/macppc/stand/ofwboot/boot.c
sys/arch/mips/mips/in_cksum.c
sys/arch/mvme68k/conf/std.mvme68k
sys/arch/news68k/conf/std.news68k
sys/arch/news68k/stand/boot/boot.c
sys/arch/newsmips/stand/boot/boot.c
sys/arch/next68k/conf/std.next68k
sys/arch/sparc/conf/files.sparc
sys/arch/sparc/conf/std.sparc
sys/arch/sparc/dev/cgfourteen.c
sys/arch/sparc/dev/cgfourteenvar.h
sys/arch/sparc/include/ieee.h
sys/arch/sparc/sparc/cpu_in_cksum.c
sys/arch/sparc/sparc/in_cksum.c
sys/arch/sparc/stand/Makefile.buildboot
sys/arch/sparc/stand/boot/boot.c
sys/arch/sparc/stand/common/isfloppy.c
sys/arch/sparc/stand/common/isfloppy.h
sys/arch/sparc/stand/common/promdev.c
sys/arch/sparc/stand/ofwboot/Makefile
sys/arch/sparc/stand/ofwboot/boot.c
sys/arch/sparc64/conf/files.sparc64
sys/arch/sparc64/dev/ffb.c
sys/arch/sparc64/dev/ffb_mainbus.c
sys/arch/sparc64/dev/ffbvar.h
sys/arch/sparc64/dev/gfb.c
sys/arch/sparc64/sparc64/autoconf.c
sys/arch/sun2/conf/std.sun2
sys/arch/sun3/conf/std.sun3
sys/arch/sun3/conf/std.sun3x
sys/arch/x68k/conf/std.x68k
sys/arch/x68k/stand/boot/boot.c
sys/arch/x86/acpi/acpi_cpu_md.c
sys/arch/x86/include/cpu.h
sys/arch/x86/include/cpuvar.h
sys/arch/x86/include/ieee.h
sys/arch/x86/include/machdep.h
sys/arch/x86/include/specialreg.h
sys/arch/x86/pci/fwhrng.c
sys/arch/x86/pci/i82802reg.h
sys/arch/x86/pci/ichlpcib.c
sys/arch/x86/x86/bus_dma.c
sys/arch/x86/x86/coretemp.c
sys/arch/x86/x86/cpu.c
sys/arch/x86/x86/est.c
sys/arch/x86/x86/ipmi.c
sys/arch/x86/x86/platform.c
sys/arch/x86/x86/tsc.c
sys/arch/x86/x86/vga_post.c
sys/arch/x86/x86/x86_autoconf.c
sys/arch/x86/x86/x86_machdep.c
sys/arch/xen/include/xen3-public/elfstructs.h
sys/arch/xen/include/xenio.h
sys/arch/xen/include/xenio3.h
sys/arch/xen/x86/cpu.c
sys/arch/xen/xen/balloon.c
sys/compat/linux/arch/alpha/linux_fcntl.h
sys/compat/linux/arch/amd64/linux_fcntl.h
sys/compat/linux/arch/arm/linux_fcntl.h
sys/compat/linux/arch/i386/linux_fcntl.h
sys/compat/linux/arch/mips/linux_fcntl.h
sys/compat/linux/arch/powerpc/linux_fcntl.h
sys/compat/linux/common/linux_dirent.h
sys/compat/linux/common/linux_exec_elf32.c
sys/compat/linux/common/linux_file.c
sys/compat/linux/common/linux_misc.c
sys/compat/linux32/common/linux32_dirent.c
sys/compat/linux32/common/linux32_exec_elf32.c
sys/compat/linux32/common/linux32_types.h
sys/compat/netbsd32/netbsd32_ioctl.c
sys/compat/netbsd32/netbsd32_ioctl.h
sys/conf/files
sys/conf/majors
sys/ddb/db_command.c
sys/ddb/db_input.c
sys/dev/DEVNAMES
sys/dev/acpi/acpi.c
sys/dev/acpi/acpi_acad.c
sys/dev/acpi/acpi_bat.c
sys/dev/acpi/acpi_button.c
sys/dev/acpi/acpi_cpu.c
sys/dev/acpi/acpi_cpu.h
sys/dev/acpi/acpi_cpu_cstate.c
sys/dev/acpi/acpi_cpu_pstate.c
sys/dev/acpi/acpi_cpu_tstate.c
sys/dev/acpi/acpi_lid.c
sys/dev/acpi/acpi_pci.c
sys/dev/acpi/acpi_quirks.c
sys/dev/acpi/acpi_verbose.c
sys/dev/acpi/acpireg.h
sys/dev/acpi/acpivar.h
sys/dev/acpi/files.acpi
sys/dev/acpi/sony_acpi.c
sys/dev/acpi/wb_acpi.c
sys/dev/acpi/wss_acpi.c
sys/dev/acpi/ym_acpi.c
sys/dev/adb/adb_bt.c
sys/dev/adb/adb_ms.c
sys/dev/dm/dm_target.c
sys/dev/filemon/filemon.c
sys/dev/filemon/filemon.h
sys/dev/filemon/filemon_wrapper.c
sys/dev/filemon/mknod-sh
sys/dev/i2c/dbcool.c
sys/dev/i2c/files.i2c
sys/dev/i2c/g760a.c
sys/dev/i2c/g760areg.h
sys/dev/ic/ciss.c
sys/dev/ic/dm9000.c
sys/dev/ic/dm9000reg.h
sys/dev/ic/dm9000var.h
sys/dev/ic/esiop.c
sys/dev/ic/isp_netbsd.c
sys/dev/ic/lan9118reg.h
sys/dev/ic/nslm7x.c
sys/dev/ic/siop.c
sys/dev/ic/w83l518d.c
sys/dev/ic/w83l518d_sdmmc.c
sys/dev/ic/w83l518d_sdmmc.h
sys/dev/ic/w83l518dvar.h
sys/dev/ieee1394/firewire.c
sys/dev/ieee1394/firewirereg.h
sys/dev/ieee1394/fwcrom.c
sys/dev/ieee1394/fwdev.c
sys/dev/ieee1394/fwohci.c
sys/dev/ieee1394/iec13213.h
sys/dev/ieee1394/sbp.c
sys/dev/ieee1394/sbp.h
sys/dev/isa/fd.c
sys/dev/isa/isa.c
sys/dev/isa/itesio_isa.c
sys/dev/isa/itesio_isavar.h
sys/dev/ld.c
sys/dev/ldvar.h
sys/dev/marvell/com_mv.c
sys/dev/marvell/ehci_mv.c
sys/dev/marvell/files.discovery
sys/dev/marvell/gttwsi.c
sys/dev/marvell/if_mvgbe.c
sys/dev/marvell/mvgbereg.h
sys/dev/marvell/mvsdio.c
sys/dev/marvell/mvsdioreg.h
sys/dev/mii/mii_physubr.c
sys/dev/pad/pad.c
sys/dev/pci/genfb_pci.c
sys/dev/pci/hdaudio/files.hdaudio
sys/dev/pci/hdaudio/hdaudio.c
sys/dev/pci/hdaudio/hdaudio_afg.c
sys/dev/pci/hdaudio/hdaudio_ids.c
sys/dev/pci/hdaudio/hdaudio_ids.h
sys/dev/pci/hdaudio/hdaudiovar.h
sys/dev/pci/if_iwn.c
sys/dev/pci/machfb.c
sys/dev/pci/pci_subr.c
sys/dev/pci/pcidevs
sys/dev/pci/pcidevs.h
sys/dev/pci/pcidevs_data.h
sys/dev/pci/r128fb.c
sys/dev/pci/r128fbreg.h
sys/dev/pci/radeonfb.c
sys/dev/pci/radeonfbvar.h
sys/dev/putter/putter.c
sys/dev/raidframe/rf_engine.c
sys/dev/sbus/cgthree_sbus.c
sys/dev/sbus/cgtwelve.c
sys/dev/sbus/files.sbus
sys/dev/sbus/genfb_sbus.c
sys/dev/scsipi/scsipi_base.c
sys/dev/scsipi/scsipiconf.c
sys/dev/sdmmc/ld_sdmmc.c
sys/dev/sdmmc/sdhc.c
sys/dev/sdmmc/sdmmc.c
sys/dev/sdmmc/sdmmc_cis.c
sys/dev/sdmmc/sdmmc_io.c
sys/dev/sdmmc/sdmmc_ioreg.h
sys/dev/sdmmc/sdmmc_mem.c
sys/dev/sdmmc/sdmmcchip.h
sys/dev/sdmmc/sdmmcreg.h
sys/dev/sdmmc/sdmmcvar.h
sys/dev/spi/spi.c
sys/dev/sun/cgsix.c
sys/dev/sun/cgthree.c
sys/dev/sun/sunkbd.c
sys/dev/sysmon/sysmon_envsys_events.c
sys/dev/tprof/tprof.c
sys/dev/usb/if_atu.c
sys/dev/usb/if_aue.c
sys/dev/usb/if_axe.c
sys/dev/usb/if_axereg.h
sys/dev/usb/if_kue.c
sys/dev/usb/if_kuereg.h
sys/dev/usb/if_upgt.c
sys/dev/usb/kue_fw.h
sys/dev/usb/ucom.c
sys/dev/usb/uhub.c
sys/dev/usb/umodem_common.c
sys/dev/usb/usb_quirks.c
sys/dev/usb/usb_quirks.h
sys/dev/usb/usb_subr.c
sys/dev/usb/usbdevs
sys/dev/usb/usbdevs.h
sys/dev/usb/usbdevs_data.h
sys/dev/usb/usbdi_util.c
sys/dev/vnd.c
sys/dev/vndvar.h
sys/dev/wscons/wsconsio.h
sys/dev/wscons/wsdisplay_vcons.c
sys/dev/wscons/wsdisplay_vconsvar.h
sys/dev/wsfb/files.wsfb
sys/dev/wsfb/genfb.c
sys/dev/wsfb/genfbvar.h
sys/dist/ipf/netinet/ip_fil_netbsd.c
sys/external/bsd/drm/dist/shared-core/via_drv.c
sys/external/intel-public/acpica/dist/executer/exconfig.c
sys/fs/nilfs/nilfs_subr.c
sys/fs/nilfs/nilfs_vfsops.c
sys/fs/udf/udf.h
sys/fs/udf/udf_subr.c
sys/kern/exec_elf.c
sys/kern/exec_subr.c
sys/kern/init_main.c
sys/kern/init_sysent.c
sys/kern/kern_cfglock.c
sys/kern/kern_descrip.c
sys/kern/kern_event.c
sys/kern/kern_exec.c
sys/kern/kern_module.c
sys/kern/kern_pax.c
sys/kern/kern_prot.c
sys/kern/kern_syscall.c
sys/kern/makesyscalls.sh
sys/kern/subr_autoconf.c
sys/kern/subr_lockdebug.c
sys/kern/subr_userconf.c
sys/kern/sys_module.c
sys/kern/sys_pipe.c
sys/kern/sys_sig.c
sys/kern/syscalls.c
sys/kern/syscalls.master
sys/kern/tty.c
sys/kern/tty_pty.c
sys/kern/uipc_accf.c
sys/kern/vfs_subr.c
sys/kern/vfs_syscalls.c
sys/kern/vfs_vnops.c
sys/kern/vfs_wapbl.c
sys/lib/libkern/arch/i386/random.S
sys/lib/libsa/loadfile.h
sys/lib/libsa/loadfile_elf32.c
sys/miscfs/genfs/genfs_io.c
sys/miscfs/genfs/genfs_node.h
sys/miscfs/genfs/genfs_vnops.c
sys/miscfs/procfs/procfs_map.c
sys/miscfs/specfs/spec_vnops.c
sys/modules/acpicpu/Makefile
sys/modules/acpiverbose/ACPIVERBOSE.ioconf
sys/modules/acpiverbose/Makefile
sys/modules/filemon/Makefile
sys/modules/npf/Makefile
sys/modules/vnd/Makefile
sys/net/Makefile
sys/net/agr/if_agr.c
sys/net/if.c
sys/net/if_ppp.c
sys/net/if_srt.c
sys/net/npf/Makefile
sys/net/npf/files.npf
sys/net/npf/npf.c
sys/net/npf/npf.h
sys/net/npf/npf_alg.c
sys/net/npf/npf_alg_icmp.c
sys/net/npf/npf_ctl.c
sys/net/npf/npf_handler.c
sys/net/npf/npf_impl.h
sys/net/npf/npf_inet.c
sys/net/npf/npf_instr.c
sys/net/npf/npf_mbuf.c
sys/net/npf/npf_nat.c
sys/net/npf/npf_ncode.h
sys/net/npf/npf_processor.c
sys/net/npf/npf_ruleset.c
sys/net/npf/npf_sendpkt.c
sys/net/npf/npf_session.c
sys/net/npf/npf_tableset.c
sys/net/pfkeyv2.h
sys/netinet/files.ipfilter
sys/netinet/ip_carp.c
sys/netinet/ip_reass.c
sys/netinet/ip_var.h
sys/netinet6/esp_aesctr.c
sys/netinet6/esp_core.c
sys/netinet6/icmp6.c
sys/netinet6/in6_pcb.c
sys/netinet6/in6_proto.c
sys/netinet6/ip6_etherip.c
sys/netinet6/ip6_etherip.h
sys/netipsec/key.c
sys/netipsec/keydb.h
sys/netipsec/xform_ipcomp.c
sys/netkey/key.c
sys/nfs/nfs_boot.c
sys/nfs/nfs_bootdhcp.c
sys/nfs/nfs_node.c
sys/nfs/nfs_vfsops.c
sys/nfs/nfsdiskless.h
sys/nfs/nfsmount.h
sys/nfs/nfsnode.h
sys/opencrypto/crypto.c
sys/rump/dev/Makefile.rumpdev
sys/rump/dev/files.rump
sys/rump/dev/lib/libscsipi/Makefile
sys/rump/dev/lib/libscsipi/SCSIPI.ioconf
sys/rump/dev/lib/libscsipi/component.c
sys/rump/dev/lib/libscsipi/opt/atapibus.h
sys/rump/dev/lib/libscsipi/opt/opt_compat_freebsd.h
sys/rump/dev/lib/libscsipi/opt/opt_scsi.h
sys/rump/dev/lib/libscsipi/opt/scsibus.h
sys/rump/dev/lib/libscsipi/opt/wd.h
sys/rump/dev/lib/libscsipi/shlib_version
sys/rump/dev/lib/libscsitest/Makefile
sys/rump/dev/lib/libscsitest/SCSITEST.ioconf
sys/rump/dev/lib/libscsitest/component.c
sys/rump/dev/lib/libscsitest/scsitest.c
sys/rump/dev/lib/libscsitest/shlib_version
sys/rump/dev/lib/libsysmon/component.c
sys/rump/dev/lib/libucom/UCOM.ioconf
sys/rump/dev/lib/libulpt/ULPT.ioconf
sys/rump/dev/lib/libumass/Makefile
sys/rump/dev/lib/libumass/UMASS.ioconf
sys/rump/dev/lib/libumass/component.c
sys/rump/dev/lib/libumass/opt/atapibus.h
sys/rump/dev/lib/libumass/opt/opt_compat_freebsd.h
sys/rump/dev/lib/libumass/opt/opt_scsi.h
sys/rump/dev/lib/libumass/opt/scsibus.h
sys/rump/dev/lib/libumass/opt/wd.h
sys/rump/dev/lib/libumass/sd_at_scsibus_at_umass.c
sys/rump/include/machine/intr.h
sys/rump/include/rump/Makefile
sys/rump/include/rump/rump.h
sys/rump/include/rump/rump_syscalls.h
sys/rump/include/rump/rump_syscalls_compat.h
sys/rump/include/rump/rumpkern_if_pub.h
sys/rump/include/rump/rumpvfs_if_pub.h
sys/rump/include/rump/scsitest.h
sys/rump/librump/makerumpif.sh
sys/rump/librump/rumpkern/Makefile.rumpkern
sys/rump/librump/rumpkern/emul.c
sys/rump/librump/rumpkern/intr.c
sys/rump/librump/rumpkern/lwproc.c
sys/rump/librump/rumpkern/rump.3
sys/rump/librump/rumpkern/rump.c
sys/rump/librump/rumpkern/rump_private.h
sys/rump/librump/rumpkern/rump_syscalls.c
sys/rump/librump/rumpkern/rumpkern.ifspec
sys/rump/librump/rumpkern/rumpkern_if_priv.h
sys/rump/librump/rumpkern/rumpkern_if_wrappers.c
sys/rump/librump/rumpkern/scheduler.c
sys/rump/librump/rumpkern/sysproxy_socket.c
sys/rump/librump/rumpkern/threads.c
sys/rump/librump/rumpkern/vm.c
sys/rump/librump/rumpvfs/compat.c
sys/rump/librump/rumpvfs/rump_vfs.c
sys/rump/librump/rumpvfs/rump_vfs_private.h
sys/rump/librump/rumpvfs/rumpblk.c
sys/rump/librump/rumpvfs/rumpfs.c
sys/rump/librump/rumpvfs/rumpvfs.ifspec
sys/rump/librump/rumpvfs/rumpvfs_if_priv.h
sys/rump/librump/rumpvfs/rumpvfs_if_wrappers.c
sys/rump/librump/rumpvfs/vm_vfs.c
sys/rump/net/lib/libshmif/Makefile
sys/rump/net/lib/libshmif/dumpbus.c
sys/rump/net/lib/libshmif/if_shmem.c
sys/rump/net/lib/libshmif/shmif_busops.c
sys/rump/net/lib/libshmif/shmifvar.h
sys/sys/Makefile
sys/sys/agpio.h
sys/sys/exec.h
sys/sys/exec_elf.h
sys/sys/fcntl.h
sys/sys/lwp.h
sys/sys/module.h
sys/sys/param.h
sys/sys/rb.h
sys/sys/rbtree.h
sys/sys/syscall.h
sys/sys/syscallargs.h
sys/sys/systm.h
sys/ufs/ffs/ffs_vnops.c
sys/ufs/ufs/ufs_inode.c
sys/uvm/uvm_map.c
sys/uvm/uvm_map.h
sys/uvm/uvm_mremap.c
sys/uvm/uvm_object.h
sys/uvm/uvm_page.c
sys/uvm/uvm_page.h
sys/uvm/uvm_pager.h
sys/uvm/uvm_pdaemon.h
--- a/sys/arch/alpha/alpha/dec_6600.c	Sun Sep 26 03:58:54 2010 +0000
+++ b/sys/arch/alpha/alpha/dec_6600.c	Sat Oct 09 03:31:35 2010 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: dec_6600.c,v 1.26.44.2 2009/09/16 13:37:34 yamt Exp $ */
+/* $NetBSD: dec_6600.c,v 1.26.44.3 2010/10/09 03:31:35 yamt Exp $ */
 
 /*
  * Copyright (c) 1995, 1996, 1997 Carnegie-Mellon University.
@@ -31,7 +31,7 @@
 
 #include <sys/cdefs.h>			/* RCS ID & Copyright macro defns */
 
-__KERNEL_RCSID(0, "$NetBSD: dec_6600.c,v 1.26.44.2 2009/09/16 13:37:34 yamt Exp $");
+__KERNEL_RCSID(0, "$NetBSD: dec_6600.c,v 1.26.44.3 2010/10/09 03:31:35 yamt Exp $");
 
 #include <sys/param.h>
 #include <sys/systm.h>
@@ -44,6 +44,8 @@
 #include <machine/autoconf.h>
 #include <machine/cpuconf.h>
 #include <machine/bus.h>
+#include <machine/alpha.h>
+#include <machine/logout.h>
 
 #include <dev/ic/comreg.h>
 #include <dev/ic/comvar.h>
@@ -83,6 +85,10 @@
 void dec_6600_init(void);
 static void dec_6600_cons_init(void);
 static void dec_6600_device_register(struct device *, void *);
+static void dec_6600_mcheck(unsigned long, struct ev6_logout_area *);
+static void dec_6600_mcheck_sys(unsigned int, struct ev6_logout_area *);
+static void dec_6600_mcheck_handler(unsigned long, struct trapframe *,
+				    unsigned long, unsigned long);
 
 #ifdef KGDB
 #include <machine/db_machdep.h>
@@ -107,8 +113,11 @@
 	platform.iobus = "tsc";
 	platform.cons_init = dec_6600_cons_init;
 	platform.device_register = dec_6600_device_register;
-	STQP(TS_C_DIM0) = 0UL;
-	STQP(TS_C_DIM1) = 0UL;
+	platform.mcheck_handler = dec_6600_mcheck_handler;
+
+	/* enable Cchip and Pchip error interrupts */
+	STQP(TS_C_DIM0) = 0xe000000000000000;
+	STQP(TS_C_DIM1) = 0xe000000000000000;
 }
 
 static void
@@ -362,3 +371,85 @@
 		found = 1;
 	}
 }
+
+
+static void
+dec_6600_mcheck(unsigned long vector, struct ev6_logout_area *la)
+{
+	const char *t = "Unknown", *c = "";
+
+	if (vector == ALPHA_SYS_ERROR || vector == ALPHA_PROC_ERROR)
+		c = " Correctable";
+
+	switch (vector) {
+	case ALPHA_SYS_ERROR:
+	case ALPHA_SYS_MCHECK:
+		t = "System";
+		break;
+
+	case ALPHA_PROC_ERROR:
+	case ALPHA_PROC_MCHECK:
+		t = "Processor";
+		break;
+
+	case ALPHA_ENV_MCHECK:
+		t = "Environmental";
+		break;
+	}
+
+	printf("\n%s%s Machine Check (%lx): "
+	       "Rev 0x%x, Code 0x%x, Flags 0x%x\n\n",
+	       t, c, vector, la->mchk_rev, la->mchk_code, la->la.la_flags);
+}
+
+static void
+dec_6600_mcheck_sys(unsigned int indent, struct ev6_logout_area *la)
+{
+	struct ev6_logout_sys *ls = 
+		(struct ev6_logout_sys *)ALPHA_LOGOUT_SYSTEM_AREA(&la->la);
+
+#define FMT	"%-30s = 0x%016lx\n"
+
+	IPRINTF(indent, FMT, "Software Error Summary Flags", ls->flags);
+
+	IPRINTF(indent, FMT, "CPU Device Interrupt Requests", ls->dir);
+	tsc_print_dir(indent + 1, ls->dir);
+
+	IPRINTF(indent, FMT, "Cchip Miscellaneous Register", ls->misc);
+	tsc_print_misc(indent + 1, ls->misc);
+
+	IPRINTF(indent, FMT, "Pchip 0 Error Register", ls->p0_error);
+	if (ls->flags & 0x5)
+		tsp_print_error(indent + 1, ls->p0_error);
+
+	IPRINTF(indent, FMT, "Pchip 1 Error Register", ls->p1_error);
+	if (ls->flags & 0x6)
+		tsp_print_error(indent + 1, ls->p1_error);
+}
+
+static void
+dec_6600_mcheck_handler(unsigned long mces, struct trapframe *framep,
+			unsigned long vector, unsigned long param)
+{
+	struct mchkinfo *mcp;
+	struct ev6_logout_area *la = (struct ev6_logout_area *)param;
+
+	/*
+	 * If we expected a machine check, just go handle it in common code.
+	 */
+	mcp = &curcpu()->ci_mcinfo;
+	if (mcp->mc_expected) 
+		machine_check(mces, framep, vector, param);
+
+	dec_6600_mcheck(vector, la);
+
+	switch (vector) {
+	case ALPHA_SYS_ERROR:
+	case ALPHA_SYS_MCHECK:
+		dec_6600_mcheck_sys(1, la);
+		break;
+
+	}
+
+	machine_check(mces, framep, vector, param);
+}
--- a/sys/arch/alpha/common/sgmap_typedep.c	Sun Sep 26 03:58:54 2010 +0000
+++ b/sys/arch/alpha/common/sgmap_typedep.c	Sat Oct 09 03:31:35 2010 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: sgmap_typedep.c,v 1.34.44.1 2008/05/16 02:21:44 yamt Exp $ */
+/* $NetBSD: sgmap_typedep.c,v 1.34.44.2 2010/10/09 03:31:36 yamt Exp $ */
 
 /*-
  * Copyright (c) 1997, 1998, 2001 The NetBSD Foundation, Inc.
@@ -31,7 +31,7 @@
  */
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(1, "$NetBSD: sgmap_typedep.c,v 1.34.44.1 2008/05/16 02:21:44 yamt Exp $");
+__KERNEL_RCSID(1, "$NetBSD: sgmap_typedep.c,v 1.34.44.2 2010/10/09 03:31:36 yamt Exp $");
 
 #include "opt_ddb.h"
 
@@ -121,9 +121,12 @@
 		}
 	}
 
-#if 0
-	printf("len 0x%lx -> 0x%lx, boundary 0x%lx -> 0x%lx -> ",
-	    (endva - va), sgvalen, map->_dm_boundary, boundary);
+#ifdef SGMAP_DEBUG
+	if (__C(SGMAP_TYPE,_debug)) {
+		printf("sgmap_load: va:endva = 0x%lx:0x%lx\n", va, endva);
+		printf("sgmap_load: sgvalen = 0x%lx, boundary = 0x%lx\n",
+		       sgvalen, boundary);
+	}
 #endif
 
 	s = splvm();
@@ -133,10 +136,6 @@
 	if (error)
 		return (error);
 
-#if 0
-	printf("error %d sgva 0x%lx\n", error, sgva);
-#endif
-
 	pteidx = sgva >> SGMAP_ADDR_PTEIDX_SHIFT;
 	pte = &page_table[pteidx * SGMAP_PTE_SPACING];
 
@@ -153,8 +152,8 @@
 
 #ifdef SGMAP_DEBUG
 	if (__C(SGMAP_TYPE,_debug))
-		printf("sgmap_load: wbase = 0x%lx, vpage = 0x%x, "
-		    "DMA addr = 0x%lx\n", sgmap->aps_wbase, sgva,
+		printf("sgmap_load: wbase = 0x%lx, vpage = 0x%lx, "
+		    "DMA addr = 0x%lx\n", sgmap->aps_wbase, (uint64_t)sgva,
 		    map->dm_segs[seg].ds_addr);
 #endif
 
@@ -181,9 +180,7 @@
 #ifdef SGMAP_DEBUG
 		if (__C(SGMAP_TYPE,_debug)) {
 			printf("sgmap_load:     spill page, pte = %p, "
-			    "*pte = 0x%lx\n", pte, *pte);
-			printf("sgmap_load:     pte count = %d\n",
-			    map->_dm_ptecnt);
+			    "*pte = 0x%lx\n", pte, (uint64_t)*pte);
 		}
 #endif
 	}
--- a/sys/arch/alpha/include/alpha_cpu.h	Sun Sep 26 03:58:54 2010 +0000
+++ b/sys/arch/alpha/include/alpha_cpu.h	Sat Oct 09 03:31:35 2010 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: alpha_cpu.h,v 1.48 2006/02/16 20:17:13 perry Exp $ */
+/* $NetBSD: alpha_cpu.h,v 1.48.72.1 2010/10/09 03:31:36 yamt Exp $ */
 
 /*
  * Copyright (c) 1996 Carnegie-Mellon University.
@@ -183,6 +183,7 @@
 #define	ALPHA_PROC_ERROR	0x630	/* Processor correctable error	*/
 #define	ALPHA_SYS_MCHECK	0x660	/* System machine check		*/
 #define	ALPHA_PROC_MCHECK	0x670	/* Processor machine check	*/
+#define	ALPHA_ENV_MCHECK	0x680	/* Environmental error		*/
 
 /*
  * Virtual Memory Management definitions [OSF/1 PALcode Specific]
--- a/sys/arch/alpha/include/elf_machdep.h	Sun Sep 26 03:58:54 2010 +0000
+++ b/sys/arch/alpha/include/elf_machdep.h	Sat Oct 09 03:31:35 2010 +0000
@@ -1,16 +1,13 @@
-/* $NetBSD: elf_machdep.h,v 1.10.122.1 2009/06/20 07:19:59 yamt Exp $ */
+/* $NetBSD: elf_machdep.h,v 1.10.122.2 2010/10/09 03:31:36 yamt Exp $ */
 
 #ifndef	_ALPHA_ELF_MACHDEP_H_
 #define	_ALPHA_ELF_MACHDEP_H_
 
 /*
- * Alpha ELF uses different (non-standard) definitions of Elf64_Sword
- * and Elf64_Word.
+ * Alpha ELF uses different (non-standard) definitions for the symbol
+ * hash table section.
  */
-typedef	int64_t		Elf64_Sword;
-#define	ELF64_FSZ_SWORD	8
-typedef	uint64_t	Elf64_Word;
-#define	ELF64_FSZ_WORD	8
+#define	Elf_Symindx	uint64_t
 
 #define	ELF32_MACHDEP_ENDIANNESS	XXX	/* break compilation */
 #define	ELF32_MACHDEP_ID_CASES						\
--- a/sys/arch/alpha/include/logout.h	Sun Sep 26 03:58:54 2010 +0000
+++ b/sys/arch/alpha/include/logout.h	Sat Oct 09 03:31:35 2010 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: logout.h,v 1.6 2005/12/11 12:16:16 christos Exp $ */
+/* $NetBSD: logout.h,v 1.6.78.1 2010/10/09 03:31:36 yamt Exp $ */
 
 /*
  * Copyright (c) 1998 by Matthew Jacob
@@ -262,3 +262,41 @@
 #ifdef	_KERNEL
 extern void ev5_logout_print(mc_hdr_ev5 *, mc_uc_ev5 *);
 #endif
+
+/*
+ * EV6/67 specific Machine Check logout definitions
+ * from DS20E Service Guide, EK-K8F6W-SV. A01
+ */
+
+struct ev6_logout_area {
+	struct alpha_logout_area la;
+	uint32_t mchk_code;
+	uint32_t mchk_rev;
+};
+
+struct ev6_logout_proc {
+	uint64_t i_stat;
+	uint64_t dc_stat;
+	uint64_t c_addr;
+	uint64_t c_syndrome1;
+	uint64_t c_syndrome0;
+	uint64_t c_stat;
+	uint64_t c_sts;
+	uint64_t mm_stat;
+	uint64_t exc_addr;
+	uint64_t ier_cm;
+	uint64_t isum;
+	uint64_t _r;
+	uint64_t pal_base;
+	uint64_t i_ctl;
+	uint64_t pctx;
+};
+
+struct ev6_logout_sys {
+	uint64_t flags;
+	uint64_t dir;
+	uint64_t misc;
+	uint64_t p0_error;
+	uint64_t p1_error;
+};
+
--- a/sys/arch/alpha/pci/tsc.c	Sun Sep 26 03:58:54 2010 +0000
+++ b/sys/arch/alpha/pci/tsc.c	Sat Oct 09 03:31:35 2010 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: tsc.c,v 1.13.78.2 2010/08/11 22:51:32 yamt Exp $ */
+/* $NetBSD: tsc.c,v 1.13.78.3 2010/10/09 03:31:36 yamt Exp $ */
 
 /*-
  * Copyright (c) 1999 by Ross Harvey.  All rights reserved.
@@ -35,7 +35,7 @@
 
 #include <sys/cdefs.h>
 
-__KERNEL_RCSID(0, "$NetBSD: tsc.c,v 1.13.78.2 2010/08/11 22:51:32 yamt Exp $");
+__KERNEL_RCSID(0, "$NetBSD: tsc.c,v 1.13.78.3 2010/10/09 03:31:36 yamt Exp $");
 
 #include <sys/param.h>
 #include <sys/systm.h>
@@ -244,3 +244,32 @@
 
 	return (0);
 }
+
+void
+tsc_print_dir(unsigned int indent, unsigned long dir)
+{
+	char buf[60];
+
+	snprintb(buf, 60,
+		 "\177\20"
+		 "b\77Internal Cchip asynchronous error\0"
+		 "b\76Pchip 0 error\0"
+		 "b\75Pchip 1 error\0"
+		 "b\74Pchip 2 error\0"
+		 "b\73Pchip 3 error\0",
+		 dir);
+	IPRINTF(indent, "DIR = %s\n", buf);
+}
+
+void
+tsc_print_misc(unsigned int indent, unsigned long misc)
+{
+	unsigned long tmp = MISC_NXM_SRC(misc);
+
+	if (!MISC_NXM(misc))
+		return;
+
+	IPRINTF(indent, "NXM address detected\n");
+	IPRINTF(indent, "NXM source         = %s %lu\n",
+		tmp <= 3 ? "CPU" : "Pchip", tmp <= 3 ? tmp : tmp - 4);
+}
--- a/sys/arch/alpha/pci/tsp_pci.c	Sun Sep 26 03:58:54 2010 +0000
+++ b/sys/arch/alpha/pci/tsp_pci.c	Sat Oct 09 03:31:35 2010 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: tsp_pci.c,v 1.3.130.1 2009/05/04 08:10:30 yamt Exp $ */
+/* $NetBSD: tsp_pci.c,v 1.3.130.2 2010/10/09 03:31:36 yamt Exp $ */
 
 /*-
  * Copyright (c) 1999 by Ross Harvey.  All rights reserved.
@@ -33,7 +33,7 @@
 
 #include <sys/cdefs.h>
 
-__KERNEL_RCSID(0, "$NetBSD: tsp_pci.c,v 1.3.130.1 2009/05/04 08:10:30 yamt Exp $");
+__KERNEL_RCSID(0, "$NetBSD: tsp_pci.c,v 1.3.130.2 2010/10/09 03:31:36 yamt Exp $");
 
 #include <sys/param.h>
 #include <sys/systm.h>
@@ -130,3 +130,56 @@
 	*datap = data;
 	alpha_mb();
 }
+
+#define NTH_STR(n, ...) ((const char *[]){ __VA_ARGS__ }[n])
+
+void
+tsp_print_error(unsigned int indent, unsigned long p_error)
+{
+	char buf[40];
+
+	if (PER_INV(p_error)) {
+		IPRINTF(indent, "data invalid\n");
+		return;
+	}
+
+	if (!PER_ERR(p_error))
+		return;
+
+	snprintb(buf, 40,
+		 "\177\20"
+		 "b\0Error lost\0"
+		 "b\1PCI SERR#\0"
+		 "b\2PCI PERR#\0"
+		 "b\3Delayed completion retry timeout\0"
+		 "b\4Invalid S/G page table entry\0"
+		 "b\5Address parity error\0"
+		 "b\6Target abort\0"
+		 "b\7PCI read data parity error\0"
+		 "b\10no PCI DEVSEL#\0"
+		 "b\11unknown\0"
+		 "b\12Uncorrectable ECC\0"
+		 "b\13Correctable ECC\0",
+		 PER_ERR(p_error));
+	IPRINTF(indent, "error    = %s\n", buf);
+	
+	if (PER_ECC(p_error)) {
+		IPRINTF(indent, "address  = 0x%09lx\n", PER_SADR(p_error));
+		IPRINTF(indent, "command  = 0x%lx<%s>\n", PER_CMD(p_error),
+			NTH_STR(PER_CMD(p_error) & 0x3,
+				"DMA read", "DMA RMW", "?", "S/G read"));
+		IPRINTF(indent, "syndrome = 0x%02lx\n", PER_SYN(p_error));
+	} else {
+		IPRINTF(indent, "address  = 0x%08lx, 0x%lx<%s>\n",
+			PER_PADR(p_error), PER_TRNS(p_error),
+			NTH_STR(PER_TRNS(p_error), "No DAC", "DAC SG Win3",
+				"Monster Window", "Monster Window"));
+		IPRINTF(indent, "command  = 0x%lx<%s>\n", PER_CMD(p_error),
+			NTH_STR(PER_CMD(p_error),
+				"PCI IACK", "PCI special cycle",
+				"PCI I/O read", "PCI I/O write", "?",
+				"PCI PTP write", "PCI memory read",
+				"PCI memory write", "PCI CSR write",
+				"?", "?", "?", "?", "?", "?", "?"));
+	}
+}
--- a/sys/arch/alpha/pci/tsreg.h	Sun Sep 26 03:58:54 2010 +0000
+++ b/sys/arch/alpha/pci/tsreg.h	Sat Oct 09 03:31:35 2010 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: tsreg.h,v 1.3 2001/07/05 08:38:24 toshii Exp $ */
+/* $NetBSD: tsreg.h,v 1.3.130.1 2010/10/09 03:31:36 yamt Exp $ */
 
 /*-
  * Copyright (c) 1999 by Ross Harvey.  All rights reserved.
@@ -89,6 +89,8 @@
 
 #define TS_C_MISC	0x101##a000##0080UL	/* Miscellaneous Register */
 
+#	define	MISC_NXM(r)	TSFIELD((r), 28, 1)
+#	define	MISC_NXM_SRC(r)	TSFIELD((r), 29, 3)
 #	define	MISC_REV(r)	TSFIELD((r), 39, 8)
 
 #define TS_C_MPD	0x101##a000##00c0UL
@@ -158,6 +160,15 @@
 	/* reserved	0x0380 */
 #define P_PERROR	0x03c0
 
+#	define	PER_ERR(r)	TSFIELD((r),  0, 12)
+#	define	PER_ECC(r)	TSFIELD((r), 10, 2)
+#	define	PER_SADR(r)	TSFIELD((r), 16, 34)
+#	define	PER_PADR(r)	(TSFIELD((r), 18, 32) << 2)
+#	define	PER_TRNS(r)	TSFIELD((r), 16, 2)
+#	define	PER_INV(r)	TSFIELD((r), 51, 1)
+#	define	PER_CMD(r)	TSFIELD((r), 52, 4)
+#	define	PER_SYN(r)	TSFIELD((r), 56, 8)
+
 #define P_PERRMASK	0x0400
 #define P_PERRSET	0x0440
 #define P_TLBIV		0x0480
--- a/sys/arch/alpha/pci/tsvar.h	Sun Sep 26 03:58:54 2010 +0000
+++ b/sys/arch/alpha/pci/tsvar.h	Sat Oct 09 03:31:35 2010 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: tsvar.h,v 1.5.78.3 2010/08/11 22:51:32 yamt Exp $ */
+/* $NetBSD: tsvar.h,v 1.5.78.4 2010/10/09 03:31:36 yamt Exp $ */
 
 /*-
  * Copyright (c) 1999 by Ross Harvey.  All rights reserved.
@@ -77,3 +77,9 @@
 void	tsp_bus_mem_init(bus_space_tag_t, void *);
 
 void	tsp_bus_mem_init2(bus_space_tag_t, void *);
+
+void	tsp_print_error(unsigned int, unsigned long);
+void	tsc_print_misc(unsigned int, unsigned long);
+void	tsc_print_dir(unsigned int, unsigned long);
+
+#define IPRINTF(i, f, ...)	printf("%*s" f, i * 4, "", ##__VA_ARGS__)
--- a/sys/arch/alpha/stand/common/boot.c	Sun Sep 26 03:58:54 2010 +0000
+++ b/sys/arch/alpha/stand/common/boot.c	Sat Oct 09 03:31:35 2010 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: boot.c,v 1.28.78.1 2009/05/04 08:10:30 yamt Exp $ */
+/* $NetBSD: boot.c,v 1.28.78.2 2010/10/09 03:31:37 yamt Exp $ */
 
 /*
  * Copyright (c) 1992, 1993
@@ -122,8 +122,8 @@
 		gets(boot_file);
 	}
 
-#ifdef NO_LOAD_NOTE
-	loadflag = LOAD_KERNEL & ~LOAD_NOTE;
+#ifdef NO_LOAD_BACKWARDS
+	loadflag = LOAD_KERNEL & ~LOAD_BACKWARDS;
 #else
 	loadflag = LOAD_KERNEL;
 #endif
--- a/sys/arch/alpha/stand/ustarboot/Makefile	Sun Sep 26 03:58:54 2010 +0000
+++ b/sys/arch/alpha/stand/ustarboot/Makefile	Sat Oct 09 03:31:35 2010 +0000
@@ -1,4 +1,4 @@
-# $NetBSD: Makefile,v 1.6.124.1 2009/05/04 08:10:31 yamt Exp $
+# $NetBSD: Makefile,v 1.6.124.2 2010/10/09 03:31:37 yamt Exp $
 
 PROG = ustarboot
 
@@ -12,7 +12,7 @@
 		-DLIBSA_SINGLE_DEVICE=blkdev \
 		  -D"blkdevioctl(x,y,z)=EINVAL" \
 		-DLIBSA_SINGLE_FILESYSTEM=ustarfs \
-		-DNO_LOAD_NOTE
+		-DNO_LOAD_BACKWARDS
 
 CLEANFILES+= ${PROG}.sym
 
--- a/sys/arch/amd64/amd64/machdep.c	Sun Sep 26 03:58:54 2010 +0000
+++ b/sys/arch/amd64/amd64/machdep.c	Sat Oct 09 03:31:35 2010 +0000
@@ -1,4 +1,4 @@
-/*	$NetBSD: machdep.c,v 1.89.2.5 2010/08/11 22:51:33 yamt Exp $	*/
+/*	$NetBSD: machdep.c,v 1.89.2.6 2010/10/09 03:31:37 yamt Exp $	*/
 
 /*-
  * Copyright (c) 1996, 1997, 1998, 2000, 2006, 2007, 2008
@@ -107,7 +107,7 @@
  */
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: machdep.c,v 1.89.2.5 2010/08/11 22:51:33 yamt Exp $");
+__KERNEL_RCSID(0, "$NetBSD: machdep.c,v 1.89.2.6 2010/10/09 03:31:37 yamt Exp $");
 
 /* #define XENDEBUG_LOW  */
 
@@ -697,8 +697,10 @@
         if ((howto & RB_POWERDOWN) == RB_POWERDOWN) {
 #ifndef XEN
 #if NACPICA > 0
-		acpi_enter_sleep_state(acpi_softc, ACPI_STATE_S5);
-		printf("WARNING: powerdown failed!\n");
+		if (acpi_softc != NULL) {
+			acpi_enter_sleep_state(acpi_softc, ACPI_STATE_S5);
+			printf("WARNING: ACPI powerdown failed!\n");
+		}
 #endif
 #else /* XEN */
 		HYPERVISOR_shutdown();
--- a/sys/arch/amd64/amd64/netbsd32_machdep.c	Sun Sep 26 03:58:54 2010 +0000
+++ b/sys/arch/amd64/amd64/netbsd32_machdep.c	Sat Oct 09 03:31:35 2010 +0000
@@ -1,4 +1,4 @@
-/*	$NetBSD: netbsd32_machdep.c,v 1.50.2.4 2010/08/11 22:51:33 yamt Exp $	*/
+/*	$NetBSD: netbsd32_machdep.c,v 1.50.2.5 2010/10/09 03:31:37 yamt Exp $	*/
 
 /*
  * Copyright (c) 2001 Wasabi Systems, Inc.
@@ -36,7 +36,7 @@
  */
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: netbsd32_machdep.c,v 1.50.2.4 2010/08/11 22:51:33 yamt Exp $");
+__KERNEL_RCSID(0, "$NetBSD: netbsd32_machdep.c,v 1.50.2.5 2010/10/09 03:31:37 yamt Exp $");
 
 #ifdef _KERNEL_OPT
 #include "opt_compat_netbsd.h"
@@ -962,7 +962,7 @@
 	pcb = lwp_getpcb(curlwp);
 
 	if (((scp->sc_eflags ^ tf->tf_rflags) & PSL_USERSTATIC) != 0 ||
-	    scp->sc_cs != GSEL(GUCODE32_SEL, SEL_UPL))
+	    !VALID_USER_CSEL32(scp->sc_cs))
 		return EINVAL;
 	if (scp->sc_fs != 0 && !VALID_USER_DSEL32(scp->sc_fs) &&
 	    !(scp->sc_fs == GSEL(GUFS_SEL, SEL_UPL) && pcb->pcb_fs != 0))
@@ -991,7 +991,7 @@
 	pcb = lwp_getpcb(l);
 
 	if (((gr[_REG32_EFL] ^ tf->tf_rflags) & PSL_USERSTATIC) != 0 ||
-	    gr[_REG32_CS] != GSEL(GUCODE32_SEL, SEL_UPL))
+	    !VALID_USER_CSEL32(gr[_REG32_CS]))
 		return EINVAL;
 	if (gr[_REG32_FS] != 0 && !VALID_USER_DSEL32(gr[_REG32_FS]) &&
 	    !(gr[_REG32_FS] == GSEL(GUFS_SEL, SEL_UPL) && pcb->pcb_fs != 0))
--- a/sys/arch/amd64/conf/GENERIC	Sun Sep 26 03:58:54 2010 +0000
+++ b/sys/arch/amd64/conf/GENERIC	Sat Oct 09 03:31:35 2010 +0000
@@ -1,4 +1,4 @@
-# $NetBSD: GENERIC,v 1.205.2.7 2010/08/11 22:51:33 yamt Exp $
+# $NetBSD: GENERIC,v 1.205.2.8 2010/10/09 03:31:37 yamt Exp $
 #
 # GENERIC machine description file
 #
@@ -22,7 +22,7 @@
 
 options 	INCLUDE_CONFIG_FILE	# embed config file in kernel binary
 
-#ident 		"GENERIC-$Revision: 1.205.2.7 $"
+#ident 		"GENERIC-$Revision: 1.205.2.8 $"
 
 maxusers	64		# estimated number of users
 
@@ -1108,6 +1108,9 @@
 pseudo-device	vnd			# disk-like interface to files
 #options 	VND_COMPRESSION		# compressed vnd(4)
 
+# NPF
+#pseudo-device	npf
+
 # network pseudo-devices
 pseudo-device	bpfilter		# Berkeley packet filter
 #pseudo-device	carp			# Common Address Redundancy Protocol
--- a/sys/arch/amd64/conf/XEN3_DOM0	Sun Sep 26 03:58:54 2010 +0000
+++ b/sys/arch/amd64/conf/XEN3_DOM0	Sat Oct 09 03:31:35 2010 +0000
@@ -1,4 +1,4 @@
-# $NetBSD: XEN3_DOM0,v 1.15.2.6 2010/08/11 22:51:33 yamt Exp $
+# $NetBSD: XEN3_DOM0,v 1.15.2.7 2010/10/09 03:31:37 yamt Exp $
 
 include 	"arch/amd64/conf/std.xen"
 
@@ -786,6 +786,7 @@
 pseudo-device	md		1	# memory disk device (ramdisk)
 pseudo-device	vnd			# disk-like interface to files
 pseudo-device	putter			# for puffs and pud
+pseudo-device	dm			# device-mapper driver for LVM
 
 # network pseudo-devices
 pseudo-device	bpfilter		# Berkeley packet filter
--- a/sys/arch/amd64/conf/XEN3_DOMU	Sun Sep 26 03:58:54 2010 +0000
+++ b/sys/arch/amd64/conf/XEN3_DOMU	Sat Oct 09 03:31:35 2010 +0000
@@ -1,4 +1,4 @@
-# $NetBSD: XEN3_DOMU,v 1.8.4.3 2010/08/11 22:51:33 yamt Exp $
+# $NetBSD: XEN3_DOMU,v 1.8.4.4 2010/10/09 03:31:38 yamt Exp $
 
 include 	"arch/amd64/conf/std.xen"
 
@@ -195,6 +195,7 @@
 
 pseudo-device	md		1	# memory disk device (ramdisk)
 pseudo-device	vnd			# disk-like interface to files
+pseudo-device	dm			# device-mapper driver for LVM
 
 # network pseudo-devices
 pseudo-device	bpfilter		# Berkeley packet filter
--- a/sys/arch/amd64/include/segments.h	Sun Sep 26 03:58:54 2010 +0000
+++ b/sys/arch/amd64/include/segments.h	Sat Oct 09 03:31:35 2010 +0000
@@ -1,4 +1,4 @@
-/*	$NetBSD: segments.h,v 1.18.2.2 2010/08/11 22:51:34 yamt Exp $	*/
+/*	$NetBSD: segments.h,v 1.18.2.3 2010/10/09 03:31:38 yamt Exp $	*/
 
 /*-
  * Copyright (c) 1990 The Regents of the University of California.
@@ -395,10 +395,8 @@
 #define VALID_USER_DSEL32(s) \
     (((s) & 0xffff) == GSEL(GUDATA32_SEL, SEL_UPL) || \
      ((s) & 0xffff) == LSEL(LUDATA32_SEL, SEL_UPL))
-#if 0 /* not used */
 #define VALID_USER_CSEL32(s) \
     ((s) == GSEL(GUCODE32_SEL, SEL_UPL) || (s) == LSEL(LUCODE32_SEL, SEL_UPL))
-#endif
 
 #define VALID_USER_CSEL(s) \
     ((s) == GSEL(GUCODE_SEL, SEL_UPL) || (s) == LSEL(LUCODE_SEL, SEL_UPL))
--- a/sys/arch/amiga/conf/std.amiga	Sun Sep 26 03:58:54 2010 +0000
+++ b/sys/arch/amiga/conf/std.amiga	Sat Oct 09 03:31:35 2010 +0000
@@ -1,15 +1,13 @@
-#	$NetBSD: std.amiga,v 1.21 2005/12/11 12:16:27 christos Exp $
+#	$NetBSD: std.amiga,v 1.21.78.1 2010/10/09 03:31:38 yamt Exp $
 
 # standard amiga information
 
 machine amiga m68k
-include		"conf/std"	# MI standard options
+include		"conf/std"			# MI standard options
+include		"arch/m68k/conf/std.m68k"	# m68k standard options
 
 mainbus0	at root
 
 clock0	at mainbus0
 kbd0	at mainbus0
 zbus0	at mainbus0
-
-options 	EXEC_ELF32
-options 	EXEC_SCRIPT
--- a/sys/arch/arm/arm/cpufunc.c	Sun Sep 26 03:58:54 2010 +0000
+++ b/sys/arch/arm/arm/cpufunc.c	Sat Oct 09 03:31:35 2010 +0000
@@ -1,4 +1,4 @@
-/*	$NetBSD: cpufunc.c,v 1.83.4.4 2010/08/11 22:51:38 yamt Exp $	*/
+/*	$NetBSD: cpufunc.c,v 1.83.4.5 2010/10/09 03:31:38 yamt Exp $	*/
 
 /*
  * arm7tdmi support code Copyright (c) 2001 John Fremlin
@@ -45,11 +45,11 @@
  *
  * C functions for supporting CPU / MMU / TLB specific operations.
  *
- * Created      : 30/01/97
+ * Created	: 30/01/97
  */
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: cpufunc.c,v 1.83.4.4 2010/08/11 22:51:38 yamt Exp $");
+__KERNEL_RCSID(0, "$NetBSD: cpufunc.c,v 1.83.4.5 2010/10/09 03:31:38 yamt Exp $");
 
 #include "opt_compat_netbsd.h"
 #include "opt_cpuoptions.h"
@@ -1141,6 +1141,63 @@
 };
 #endif /* CPU_CORTEX */
 
+#ifdef CPU_SHEEVA
+struct cpu_functions sheeva_cpufuncs = {
+	/* CPU functions */
+
+	.cf_id			= cpufunc_id,
+	.cf_cpwait		= cpufunc_nullop,
+
+	/* MMU functions */
+
+	.cf_control		= cpufunc_control,
+	.cf_domains		= cpufunc_domains,
+	.cf_setttb		= armv5_ec_setttb,
+	.cf_faultstatus		= cpufunc_faultstatus,
+	.cf_faultaddress	= cpufunc_faultaddress,
+
+	/* TLB functions */
+
+	.cf_tlb_flushID		= armv4_tlb_flushID,
+	.cf_tlb_flushID_SE	= arm10_tlb_flushID_SE,
+	.cf_tlb_flushI		= armv4_tlb_flushI,
+	.cf_tlb_flushI_SE	= arm10_tlb_flushI_SE,
+	.cf_tlb_flushD		= armv4_tlb_flushD,
+	.cf_tlb_flushD_SE	= armv4_tlb_flushD_SE,
+
+	/* Cache operations */
+
+	.cf_icache_sync_all	= armv5_ec_icache_sync_all,
+	.cf_icache_sync_range	= armv5_ec_icache_sync_range,
+
+	.cf_dcache_wbinv_all	= armv5_ec_dcache_wbinv_all,
+	.cf_dcache_wbinv_range	= sheeva_dcache_wbinv_range,
+	.cf_dcache_inv_range	= sheeva_dcache_inv_range,
+	.cf_dcache_wb_range	= sheeva_dcache_wb_range,
+
+	.cf_idcache_wbinv_all	= armv5_ec_idcache_wbinv_all,
+	.cf_idcache_wbinv_range = sheeva_idcache_wbinv_range,
+
+	/* Other functions */
+
+	.cf_flush_prefetchbuf	= cpufunc_nullop,
+	.cf_drain_writebuf	= armv4_drain_writebuf,
+	.cf_flush_brnchtgt_C	= cpufunc_nullop,
+	.cf_flush_brnchtgt_E	= (void *)cpufunc_nullop,
+
+	.cf_sleep		= (void *)cpufunc_nullop,
+
+	/* Soft functions */
+
+	.cf_dataabt_fixup	= cpufunc_null_fixup,
+	.cf_prefetchabt_fixup	= cpufunc_null_fixup,
+
+	.cf_context_switch	= arm10_context_switch,
+
+	.cf_setup		= sheeva_setup
+};
+#endif /* CPU_SHEEVA */
+
 
 /*
  * Global constants also used by locore.s
@@ -1155,7 +1212,7 @@
     defined(CPU_FA526) || \
     defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \
     defined(__CPU_XSCALE_PXA2XX) || defined(CPU_XSCALE_IXP425) || \
-    defined(CPU_CORTEX)
+    defined(CPU_CORTEX) || defined(CPU_SHEEVA)
 static void get_cachetype_cp15(void);
 
 /* Additional cache information local to this file.  Log2 of some of the
@@ -1168,17 +1225,17 @@
 static inline u_int
 get_cachesize_cp15(int cssr)
 {
-    u_int csid;
+	u_int csid;
 
 #if (CPU_CORTEX) > 0
-    __asm volatile(".arch\tarmv7a");
-    __asm volatile("mcr p15, 2, %0, c0, c0, 0" :: "r" (cssr));
-    __asm volatile("isb");	/* sync to the new cssr */
+	__asm volatile(".arch\tarmv7a");
+	__asm volatile("mcr p15, 2, %0, c0, c0, 0" :: "r" (cssr));
+	__asm volatile("isb");	/* sync to the new cssr */
 #else
-    __asm volatile("mcr p15, 1, %0, c0, c0, 2" :: "r" (cssr));
+	__asm volatile("mcr p15, 1, %0, c0, c0, 2" :: "r" (cssr));
 #endif
-    __asm volatile("mrc p15, 1, %0, c0, c0, 0" : "=r" (csid));
-    return csid;
+	__asm volatile("mrc p15, 1, %0, c0, c0, 0" : "=r" (csid));
+	return csid;
 }
 #endif
 
@@ -1476,6 +1533,16 @@
 		return 0;
 	}
 #endif /* CPU_ARM9E || CPU_ARM10 */
+#if defined(CPU_SHEEVA)
+	if (cputype == CPU_ID_MV88SV131 ||
+	    cputype == CPU_ID_MV88FR571_VD) {
+		cpufuncs = sheeva_cpufuncs;
+		cpu_reset_needs_v4_MMU_disable = 1;	/* V4 or higher */
+		get_cachetype_cp15();
+		pmap_pte_init_generic();
+		return 0;
+	}
+#endif /* CPU_SHEEVA */
 #ifdef CPU_ARM10
 	if (/* cputype == CPU_ID_ARM1020T || */
 	    cputype == CPU_ID_ARM1020E) {
@@ -1571,13 +1638,13 @@
 	}
 #endif	/* CPU_FA526 */
 #ifdef CPU_IXP12X0
-        if (cputype == CPU_ID_IXP1200) {
-                cpufuncs = ixp12x0_cpufuncs;
-                cpu_reset_needs_v4_MMU_disable = 1;
-                get_cachetype_table();
-                pmap_pte_init_sa1();
-                return 0;
-        }
+	if (cputype == CPU_ID_IXP1200) {
+		cpufuncs = ixp12x0_cpufuncs;
+		cpu_reset_needs_v4_MMU_disable = 1;
+		get_cachetype_table();
+		pmap_pte_init_sa1();
+		return 0;
+	}
 #endif  /* CPU_IXP12X0 */
 #ifdef CPU_XSCALE_80200
 	if (cputype == CPU_ID_80200) {
@@ -1688,7 +1755,7 @@
 #endif /* __CPU_XSCALE_PXA2XX */
 #ifdef CPU_XSCALE_IXP425
 	if (cputype == CPU_ID_IXP425_533 || cputype == CPU_ID_IXP425_400 ||
-            cputype == CPU_ID_IXP425_266) {
+	    cputype == CPU_ID_IXP425_266) {
 		ixp425_icu_init();
 
 		cpufuncs = xscale_cpufuncs;
@@ -2105,7 +2172,7 @@
 	defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \
 	defined(__CPU_XSCALE_PXA2XX) || defined(CPU_XSCALE_IXP425) || \
 	defined(CPU_ARM10) || defined(CPU_ARM11) || defined(CPU_ARM1136) || \
-	defined(CPU_FA526) || defined(CPU_CORTEX)
+	defined(CPU_FA526) || defined(CPU_CORTEX) || defined(CPU_SHEEVA)
 
 #define IGN	0
 #define OR	1
@@ -2511,10 +2578,10 @@
 
 #if defined(PROCESS_ID_IS_CURCPU)
 	/* set curcpu() */
-        __asm("mcr\tp15, 0, %0, c13, c0, 4" : : "r"(&cpu_info_store));
+	__asm("mcr\tp15, 0, %0, c13, c0, 4" : : "r"(&cpu_info_store));
 #elif defined(PROCESS_ID_IS_CURLWP)
 	/* set curlwp() */
-        __asm("mcr\tp15, 0, %0, c13, c0, 4" : : "r"(&lwp0));
+	__asm("mcr\tp15, 0, %0, c13, c0, 4" : : "r"(&lwp0));
 #endif
 
 	cpuctrl = CPU_CONTROL_MMU_ENABLE | CPU_CONTROL_SYST_ENABLE
@@ -2575,10 +2642,10 @@
 
 #if defined(PROCESS_ID_IS_CURCPU)
 	/* set curcpu() */
-        __asm("mcr\tp15, 0, %0, c13, c0, 4" : : "r"(&cpu_info_store));
+	__asm("mcr\tp15, 0, %0, c13, c0, 4" : : "r"(&cpu_info_store));
 #elif defined(PROCESS_ID_IS_CURLWP)
 	/* set curlwp() */
-        __asm("mcr\tp15, 0, %0, c13, c0, 4" : : "r"(&lwp0));
+	__asm("mcr\tp15, 0, %0, c13, c0, 4" : : "r"(&lwp0));
 #endif
 
 	cpuctrl = CPU_CONTROL_MMU_ENABLE | CPU_CONTROL_IC_ENABLE
@@ -2672,10 +2739,10 @@
 
 #if defined(PROCESS_ID_IS_CURCPU)
 	/* set curcpu() */
-        __asm("mcr\tp15, 0, %0, c13, c0, 4" : : "r"(&cpu_info_store));
+	__asm("mcr\tp15, 0, %0, c13, c0, 4" : : "r"(&cpu_info_store));
 #elif defined(PROCESS_ID_IS_CURLWP)
 	/* set curlwp() */
-        __asm("mcr\tp15, 0, %0, c13, c0, 4" : : "r"(&lwp0));
+	__asm("mcr\tp15, 0, %0, c13, c0, 4" : : "r"(&lwp0));
 #endif
 
 	cpuid = cpu_id();
@@ -3059,3 +3126,63 @@
 }
 #endif	/* CPU_XSCALE_80200 || CPU_XSCALE_80321 || __CPU_XSCALE_PXA2XX || CPU_XSCALE_IXP425 */
 
+#if defined(CPU_SHEEVA)
+struct cpu_option sheeva_options[] = {
+	{ "cpu.cache",		BIC, OR,  (CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE) },
+	{ "cpu.nocache",	OR,  BIC, (CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE) },
+	{ "sheeva.cache",	BIC, OR,  (CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE) },
+	{ "sheeva.icache",	BIC, OR,  CPU_CONTROL_IC_ENABLE },
+	{ "sheeva.dcache",	BIC, OR,  CPU_CONTROL_DC_ENABLE },
+	{ "cpu.writebuf",	BIC, OR,  CPU_CONTROL_WBUF_ENABLE },
+	{ "cpu.nowritebuf",	OR,  BIC, CPU_CONTROL_WBUF_ENABLE },
+	{ "sheeva.writebuf",	BIC, OR,  CPU_CONTROL_WBUF_ENABLE },
+	{ NULL,			IGN, IGN, 0 }
+};
+
+void
+sheeva_setup(char *args)
+{
+	int cpuctrl, cpuctrlmask;
+
+	cpuctrl = CPU_CONTROL_MMU_ENABLE | CPU_CONTROL_SYST_ENABLE
+	    | CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE
+	    | CPU_CONTROL_WBUF_ENABLE | CPU_CONTROL_BPRD_ENABLE;
+	cpuctrlmask = CPU_CONTROL_MMU_ENABLE | CPU_CONTROL_SYST_ENABLE
+	    | CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE
+	    | CPU_CONTROL_WBUF_ENABLE | CPU_CONTROL_ROM_ENABLE
+	    | CPU_CONTROL_BEND_ENABLE | CPU_CONTROL_AFLT_ENABLE
+	    | CPU_CONTROL_BPRD_ENABLE
+	    | CPU_CONTROL_ROUNDROBIN | CPU_CONTROL_CPCLK;
+
+#ifndef ARM32_DISABLE_ALIGNMENT_FAULTS
+	cpuctrl |= CPU_CONTROL_AFLT_ENABLE;
+#endif
+
+	cpuctrl = parse_cpu_options(args, sheeva_options, cpuctrl);
+
+	/*
+	 * Sheeva has L2 Cache.  Enable/Disable it here.
+	 * Really not support yet...
+	 */
+
+#ifdef __ARMEB__
+	cpuctrl |= CPU_CONTROL_BEND_ENABLE;
+#endif
+
+	if (vector_page == ARM_VECTORS_HIGH)
+		cpuctrl |= CPU_CONTROL_VECRELOC;
+
+	/* Clear out the cache */
+	cpu_idcache_wbinv_all();
+
+	/* Now really make sure they are clean.  */
+	__asm volatile ("mcr\tp15, 0, r0, c7, c7, 0" : : );
+
+	/* Set the control register */
+	curcpu()->ci_ctrl = cpuctrl;
+	cpu_control(0xffffffff, cpuctrl);
+
+	/* And again. */
+	cpu_idcache_wbinv_all();
+}
+#endif	/* CPU_SHEEVA */
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/sys/arch/arm/arm/cpufunc_asm_sheeva.S	Sat Oct 09 03:31:35 2010 +0000
@@ -0,0 +1,216 @@
+/*-
+ * Copyright (C) 2008 MARVELL INTERNATIONAL LTD.
+ * All rights reserved.
+ *
+ * Developed by Semihalf.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of MARVELL nor the names of contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include <machine/cpu.h>
+#include <machine/asm.h>
+#include <arm/arm32/vmparam.h>
+
+.Lsheeva_cache_line_size:
+	.word	_C_LABEL(arm_pdcache_line_size)
+.Lsheeva_asm_page_mask:
+	.word	_C_LABEL(PAGE_MASK)
+
+ENTRY(sheeva_dcache_wbinv_range)
+	str	lr, [sp, #-4]!
+	mrs	lr, cpsr
+	/* Start with cache line aligned address */
+	ldr	ip, .Lsheeva_cache_line_size
+	ldr	ip, [ip]
+	sub	ip, ip, #1
+	and	r2, r0, ip
+	add	r1, r1, r2
+	add	r1, r1, ip
+	bics	r1, r1, ip
+	bics	r0, r0, ip
+
+	ldr	ip, .Lsheeva_asm_page_mask
+	and	r2, r0, ip
+	rsb	r2, r2, #PAGE_SIZE
+	cmp	r1, r2
+	movcc	ip, r1
+	movcs	ip, r2
+1:
+	add	r3, r0, ip
+	sub	r2, r3, #1
+	/* Disable irqs */
+	orr	r3, lr, #I32_bit | F32_bit
+	msr	cpsr_c, r3
+	mcr	p15, 5, r0, c15, c15, 0	/* Clean and inv zone start address */
+	mcr	p15, 5, r2, c15, c15, 1	/* Clean and inv zone end address */
+	/* Enable irqs */
+	msr	cpsr_c, lr
+
+	add	r0, r0, ip
+	sub	r1, r1, ip
+	cmp	r1, #PAGE_SIZE
+	movcc	ip, r1
+	movcs	ip, #PAGE_SIZE
+	cmp	r1, #0
+	bne	1b
+	mov	r0, #0
+	mcr	p15, 0, r0, c7, c10, 4	/* drain the write buffer */
+	ldr	lr, [sp], #4
+	RET
+
+ENTRY(sheeva_dcache_inv_range)
+	str	lr, [sp, #-4]!
+	mrs	lr, cpsr
+	/* Start with cache line aligned address */
+	ldr	ip, .Lsheeva_cache_line_size
+	ldr	ip, [ip]
+	sub	ip, ip, #1
+	and	r2, r0, ip
+	add	r1, r1, r2
+	add	r1, r1, ip
+	bics	r1, r1, ip
+	bics	r0, r0, ip
+
+	ldr	ip, .Lsheeva_asm_page_mask
+	and	r2, r0, ip
+	rsb	r2, r2, #PAGE_SIZE
+	cmp	r1, r2
+	movcc	ip, r1
+	movcs	ip, r2
+1:
+	add	r3, r0, ip
+	sub	r2, r3, #1
+	/* Disable irqs */
+	orr	r3, lr, #I32_bit | F32_bit
+	msr	cpsr_c, r3
+	mcr	p15, 5, r0, c15, c14, 0	/* Inv zone start address */
+	mcr	p15, 5, r2, c15, c14, 1	/* Inv zone end address */
+	/* Enable irqs */
+	msr	cpsr_c, lr
+
+	add	r0, r0, ip
+	sub	r1, r1, ip
+	cmp	r1, #PAGE_SIZE
+	movcc	ip, r1
+	movcs	ip, #PAGE_SIZE
+	cmp	r1, #0
+	bne	1b
+	mov	r0, #0
+	mcr	p15, 0, r0, c7, c10, 4	/* drain the write buffer */
+	ldr	lr, [sp], #4
+	RET
+
+ENTRY(sheeva_dcache_wb_range)
+	str	lr, [sp, #-4]!
+	mrs	lr, cpsr
+	/* Start with cache line aligned address */
+	ldr	ip, .Lsheeva_cache_line_size
+	ldr	ip, [ip]
+	sub	ip, ip, #1
+	and	r2, r0, ip
+	add	r1, r1, r2
+	add	r1, r1, ip
+	bics	r1, r1, ip
+	bics	r0, r0, ip
+
+	ldr	ip, .Lsheeva_asm_page_mask
+	and	r2, r0, ip
+	rsb	r2, r2, #PAGE_SIZE
+	cmp	r1, r2
+	movcc	ip, r1
+	movcs	ip, r2
+1:
+	add	r3, r0, ip
+	sub	r2, r3, #1
+	/* Disable irqs */
+	orr	r3, lr, #I32_bit | F32_bit
+	msr	cpsr_c, r3
+	mcr	p15, 5, r0, c15, c13, 0	/* Clean zone start address */
+	mcr	p15, 5, r2, c15, c13, 1	/* Clean zone end address */
+	/* Enable irqs */
+	msr	cpsr_c, lr
+
+	add	r0, r0, ip
+	sub	r1, r1, ip
+	cmp	r1, #PAGE_SIZE
+	movcc	ip, r1
+	movcs	ip, #PAGE_SIZE
+	cmp	r1, #0
+	bne	1b
+	mov	r0, #0
+	mcr	p15, 0, r0, c7, c10, 4	/* drain the write buffer */
+	ldr	lr, [sp], #4
+	RET
+
+ENTRY(sheeva_idcache_wbinv_range)
+	str	lr, [sp, #-4]!
+	mrs	lr, cpsr
+	/* Start with cache line aligned address */
+	ldr	ip, .Lsheeva_cache_line_size
+	ldr	ip, [ip]
+	sub	ip, ip, #1
+	and	r2, r0, ip
+	add	r1, r1, r2
+	add	r1, r1, ip
+	bics	r1, r1, ip
+	bics	r0, r0, ip
+
+	ldr	ip, .Lsheeva_asm_page_mask
+	and	r2, r0, ip
+	rsb	r2, r2, #PAGE_SIZE
+	cmp	r1, r2
+	movcc	ip, r1
+	movcs	ip, r2
+1:
+	add	r3, r0, ip
+	sub	r2, r3, #1
+	/* Disable irqs */
+	orr	r3, lr, #I32_bit | F32_bit
+	msr	cpsr_c, r3
+	mcr	p15, 5, r0, c15, c15, 0	/* Clean and inv zone start address */
+	mcr	p15, 5, r2, c15, c15, 1	/* Clean and inv zone end address */
+	/* Enable irqs */
+	msr	cpsr_c, lr
+
+	/* Invalidate and clean icache line by line */
+	ldr	r3, .Lsheeva_cache_line_size
+	ldr	r3, [r3]
+2:
+	mcr	p15, 0, r0, c7, c5, 1
+	add	r0, r0, r3
+	cmp	r2, r0
+	bhi	2b
+
+	add	r0, r2, #1
+	sub	r1, r1, ip
+	cmp	r1, #PAGE_SIZE
+	movcc	ip, r1
+	movcs	ip, #PAGE_SIZE
+	cmp	r1, #0
+	bne	1b
+	mov	r0, #0
+	mcr	p15, 0, r0, c7, c10, 4	/* drain the write buffer */
+	ldr	lr, [sp], #4
+	RET
--- a/sys/arch/arm/arm32/cpu.c	Sun Sep 26 03:58:54 2010 +0000
+++ b/sys/arch/arm/arm32/cpu.c	Sat Oct 09 03:31:35 2010 +0000
@@ -1,4 +1,4 @@
-/*	$NetBSD: cpu.c,v 1.67.4.4 2010/08/11 22:51:39 yamt Exp $	*/
+/*	$NetBSD: cpu.c,v 1.67.4.5 2010/10/09 03:31:39 yamt Exp $	*/
 
 /*
  * Copyright (c) 1995 Mark Brinicombe.
@@ -46,7 +46,7 @@
 
 #include <sys/param.h>
 
-__KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.67.4.4 2010/08/11 22:51:39 yamt Exp $");
+__KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.67.4.5 2010/10/09 03:31:39 yamt Exp $");
 
 #include <sys/systm.h>
 #include <sys/malloc.h>
@@ -344,6 +344,10 @@
 	  generic_steppings },
 	{ CPU_ID_TI925T,	CPU_CLASS_ARM9TDMI,	"TI ARM925T",
 	  generic_steppings },
+	{ CPU_ID_MV88SV131,	CPU_CLASS_ARM9ES,	"Sheeva 88SV131",
+	  generic_steppings },
+	{ CPU_ID_MV88FR571_VD,	CPU_CLASS_ARM9ES,	"Sheeva 88FR571-vd",
+	  generic_steppings },
 
 	{ CPU_ID_ARM1020E,	CPU_CLASS_ARM10E,	"ARM1020E",
 	  generic_steppings },
@@ -605,7 +609,7 @@
 #ifdef CPU_ARM9
 	case CPU_CLASS_ARM9TDMI:
 #endif
-#ifdef CPU_ARM9E
+#if defined(CPU_ARM9E) || defined(CPU_SHEEVA)
 	case CPU_CLASS_ARM9ES:
 	case CPU_CLASS_ARM9EJS:
 #endif
--- a/sys/arch/arm/conf/files.arm	Sun Sep 26 03:58:54 2010 +0000
+++ b/sys/arch/arm/conf/files.arm	Sat Oct 09 03:31:35 2010 +0000
@@ -1,4 +1,4 @@
-#	$NetBSD: files.arm,v 1.90.4.4 2010/08/11 22:51:40 yamt Exp $
+#	$NetBSD: files.arm,v 1.90.4.5 2010/10/09 03:31:39 yamt Exp $
 
 # temporary define to allow easy moving to ../arch/arm/arm32
 defflag				ARM32
@@ -12,6 +12,7 @@
 				CPU_XSCALE_80200 CPU_XSCALE_80321
 				CPU_XSCALE_PXA250 CPU_XSCALE_PXA270
 				CPU_XSCALE_IXP425 
+				CPU_SHEEVA
 defflag	opt_cputypes.h		CPU_ARM1136: CPU_ARM11
 defflag	opt_cputypes.h		CPU_ARM1176: CPU_ARM11
 defflag	opt_cputypes.h		CPU_CORTEXA8: CPU_CORTEX
@@ -105,7 +106,8 @@
 file	arch/arm/arm/cpufunc_asm_arm7tdmi.S	cpu_arm7tdmi
 file	arch/arm/arm/cpufunc_asm_arm8.S		cpu_arm8
 file	arch/arm/arm/cpufunc_asm_arm9.S		cpu_arm9
-file	arch/arm/arm/cpufunc_asm_arm10.S	cpu_arm9e | cpu_arm10
+file	arch/arm/arm/cpufunc_asm_arm10.S	cpu_arm9e | cpu_arm10 |
+							cpu_sheeva
 file	arch/arm/arm/cpufunc_asm_arm11.S	cpu_arm11 | cpu_cortex
 file	arch/arm/arm/cpufunc_asm_arm1136.S	cpu_arm1136
 file	arch/arm/arm/cpufunc_asm_armv4.S	cpu_arm9 | cpu_arm9e |
@@ -120,9 +122,11 @@
 							cpu_xscale_ixp425 |
 							cpu_xscale_pxa250 |
 							cpu_xscale_pxa270 |
-							cpu_cortex
+							cpu_cortex |
+							cpu_sheeva
 file	arch/arm/arm/cpufunc_asm_armv5.S	cpu_arm10
-file	arch/arm/arm/cpufunc_asm_armv5_ec.S	cpu_arm9e | cpu_arm10
+file	arch/arm/arm/cpufunc_asm_armv5_ec.S	cpu_arm9e | cpu_arm10 |
+							cpu_sheeva
 file	arch/arm/arm/cpufunc_asm_armv6.S	cpu_arm11 | cpu_cortex
 file	arch/arm/arm/cpufunc_asm_armv7.S	cpu_cortex
 file	arch/arm/arm/cpufunc_asm_sa1.S		cpu_sa110 | cpu_sa1100 |
@@ -137,6 +141,7 @@
 						    cpu_xscale_pxa270 |
 						    cpu_cortex
 file	arch/arm/arm/cpufunc_asm_ixp12x0.S	cpu_ixp12x0
+file	arch/arm/arm/cpufunc_asm_sheeva.S	cpu_sheeva
 file	arch/arm/arm/fusu.S
 file	arch/arm/arm/idle_machdep.c
 file	arch/arm/arm/lock_cas.S
--- a/sys/arch/arm/include/armreg.h	Sun Sep 26 03:58:54 2010 +0000
+++ b/sys/arch/arm/include/armreg.h	Sat Oct 09 03:31:35 2010 +0000
@@ -1,4 +1,4 @@
-/*	$NetBSD: armreg.h,v 1.37.50.3 2010/08/11 22:51:41 yamt Exp $	*/
+/*	$NetBSD: armreg.h,v 1.37.50.4 2010/10/09 03:31:39 yamt Exp $	*/
 
 /*
  * Copyright (c) 1998, 2001 Ben Harris
@@ -119,6 +119,7 @@
 #define CPU_ID_DEC		0x44000000 /* 'D' */
 #define CPU_ID_INTEL		0x69000000 /* 'i' */
 #define	CPU_ID_TI		0x54000000 /* 'T' */
+#define CPU_ID_MARVELL		0x56000000 /* 'V' */
 #define	CPU_ID_FARADAY		0x66000000 /* 'f' */
 
 /* How to decide what format the CPUID is in. */
@@ -205,6 +206,8 @@
 #define CPU_ID_SA110		0x4401a100
 #define CPU_ID_SA1100		0x4401a110
 #define	CPU_ID_TI925T		0x54029250
+#define CPU_ID_MV88FR571_VD	0x56155710
+#define CPU_ID_MV88SV131	0x56251310
 #define	CPU_ID_FA526		0x66015260
 #define CPU_ID_SA1110		0x6901b110
 #define CPU_ID_IXP1200		0x6901c120
@@ -315,6 +318,18 @@
 #define	XSCALE_AUXCTL_MD_WT	0x00000020 /* mini-D$ wt, read-allocate */
 #define	XSCALE_AUXCTL_MD_MASK	0x00000030
 
+/* Marvell Feroceon Extra Features Register (CP15 register 1, opcode2 0) */
+#define FC_DCACHE_REPL_LOCK	0x80000000 /* Replace DCache Lock */
+#define FC_DCACHE_STREAM_EN	0x20000000 /* DCache Streaming Switch */
+#define FC_WR_ALLOC_EN		0x10000000 /* Enable Write Allocate */
+#define FC_L2_PREF_DIS		0x01000000 /* L2 Cache Prefetch Disable */
+#define FC_L2_INV_EVICT_LINE	0x00800000 /* L2 Invalidates Uncorrectable Error Line Eviction */
+#define FC_L2CACHE_EN		0x00400000 /* L2 enable */
+#define FC_ICACHE_REPL_LOCK	0x00080000 /* Replace ICache Lock */
+#define FC_GLOB_HIST_REG_EN	0x00040000 /* Branch Global History Register Enable */
+#define FC_BRANCH_TARG_BUF_DIS	0x00020000 /* Branch Target Buffer Disable */
+#define FC_L1_PAR_ERR_EN	0x00010000 /* L1 Parity Error Enable */
+
 /* Cache type register definitions 0 */
 #define	CPU_CT_FORMAT(x)	(((x) >> 29) & 0x7)	/* reg format */
 #define	CPU_CT_ISIZE(x)		((x) & 0xfff)		/* I$ info */
--- a/sys/arch/arm/include/cpuconf.h	Sun Sep 26 03:58:54 2010 +0000
+++ b/sys/arch/arm/include/cpuconf.h	Sat Oct 09 03:31:35 2010 +0000
@@ -1,4 +1,4 @@
-/*	$NetBSD: cpuconf.h,v 1.13.50.3 2010/08/11 22:51:41 yamt Exp $	*/
+/*	$NetBSD: cpuconf.h,v 1.13.50.4 2010/10/09 03:31:39 yamt Exp $	*/
 
 /*
  * Copyright (c) 2002 Wasabi Systems, Inc.
@@ -81,7 +81,8 @@
 			 defined(CPU_XSCALE_80200) +			\
 			 defined(CPU_XSCALE_80321) +			\
 			 defined(__CPU_XSCALE_PXA2XX) +			\
-			 defined(CPU_XSCALE_IXP425))
+			 defined(CPU_XSCALE_IXP425)) +			\
+			 defined(CPU_SHEEVA))
 #else
 #define	CPU_NTYPES	2
 #endif /* _KERNEL_OPT */
@@ -116,7 +117,8 @@
 #if !defined(_KERNEL_OPT) ||						\
     (defined(CPU_ARM9E) || defined(CPU_ARM10) ||			\
      defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) ||		\
-     defined(__CPU_XSCALE_PXA2XX) || defined(CPU_XSCALE_IXP425))
+     defined(__CPU_XSCALE_PXA2XX) || defined(CPU_XSCALE_IXP425)) ||	\
+     defined(CPU_SHEEVA)
 #define	ARM_ARCH_5	1
 #else
 #define	ARM_ARCH_5	0
@@ -177,7 +179,7 @@
 #if !defined(_KERNEL_OPT) ||						\
     (defined(CPU_ARM6) || defined(CPU_ARM7) || defined(CPU_ARM7TDMI) ||	\
      defined(CPU_ARM8) || defined(CPU_ARM9) || defined(CPU_ARM9E) ||	\
-     defined(CPU_ARM10) || defined(CPU_FA526))
+     defined(CPU_ARM10) || defined(CPU_FA526)) || defined(CPU_SHEEVA)
 #define	ARM_MMU_GENERIC		1
 #else
 #define	ARM_MMU_GENERIC		0
--- a/sys/arch/arm/include/cpufunc.h	Sun Sep 26 03:58:54 2010 +0000
+++ b/sys/arch/arm/include/cpufunc.h	Sat Oct 09 03:31:35 2010 +0000
@@ -365,7 +365,7 @@
 extern unsigned arm9_dcache_index_inc;
 #endif
 
-#if defined(CPU_ARM9E) || defined(CPU_ARM10)
+#if defined(CPU_ARM9E) || defined(CPU_ARM10) || defined(CPU_SHEEVA)
 void	arm10_tlb_flushID_SE	(u_int);
 void	arm10_tlb_flushI_SE	(u_int);
 
@@ -374,7 +374,7 @@
 void	arm10_setup		(char *);
 #endif
 
-#if defined(CPU_ARM9E) || defined (CPU_ARM10)
+#if defined(CPU_ARM9E) || defined (CPU_ARM10) || defined(CPU_SHEEVA)
 void	armv5_ec_setttb			(u_int);
 
 void	armv5_ec_icache_sync_all	(void);
@@ -481,7 +481,7 @@
     defined(CPU_FA526) || \
     defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \
     defined(__CPU_XSCALE_PXA2XX) || defined(CPU_XSCALE_IXP425) || \
-    defined(CPU_CORTEX)
+    defined(CPU_CORTEX) || defined(CPU_SHEEVA)
 
 void	armv4_tlb_flushID	(void);
 void	armv4_tlb_flushI	(void);
@@ -541,6 +541,14 @@
 void	xscale_setup		(char *);
 #endif	/* CPU_XSCALE_80200 || CPU_XSCALE_80321 || __CPU_XSCALE_PXA2XX || CPU_XSCALE_IXP425 || CPU_CORTEX */
 
+#if defined(CPU_SHEEVA)
+void	sheeva_dcache_wbinv_range (vaddr_t, vsize_t);
+void	sheeva_dcache_inv_range	(vaddr_t, vsize_t);
+void	sheeva_dcache_wb_range	(vaddr_t, vsize_t);
+void	sheeva_idcache_wbinv_range (vaddr_t, vsize_t);
+void	sheeva_setup(char *);
+#endif
+
 #define tlb_flush	cpu_tlb_flushID
 #define setttb		cpu_setttb
 #define drain_writebuf	cpu_drain_writebuf
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/sys/arch/arm/marvell/files.marvell	Sat Oct 09 03:31:35 2010 +0000
@@ -0,0 +1,71 @@
+#       $NetBSD: files.marvell,v 1.2.2.2 2010/10/09 03:31:40 yamt Exp $
+#
+# Configuration info for Marvell System on Chip support
+#
+
+include "arch/arm/pic/files.pic"
+
+device	mvsoc { [unit = -1], [offset = -1], [irq = -1] } : bus_space_generic, pic
+attach	mvsoc at mainbus
+file	arch/arm/marvell/mvsoc.c		mvsoc
+file	arch/arm/marvell/mvsoc_space.c
+file	arch/arm/marvell/mvsoc_dma.c
+
+file	arch/arm/arm32/irq_dispatch.S
+
+defflag opt_mvsoc.h				ORION KIRKWOOD MV78XX0
+file	arch/arm/marvell/mvsoc_intr.c
+file	arch/arm/marvell/orion.c		orion
+file	arch/arm/marvell/kirkwood.c		kirkwood
+#file	arch/arm/marvell/mv78xx0.c		mv78xx0
+
+
+# Integrated peripherals
+include "dev/marvell/files.discovery"
+
+# Timers
+device	mvsoctmr
+attach	mvsoctmr at mvsoc
+file	arch/arm/marvell/mvsoctmr.c		mvsoctmr
+
+
+# PCI Express Interface
+attach	mvpex at mvsoc with mvpex_mbus
+
+# PCI Interface
+attach	gtpci at mvsoc with gtpci_mbus
+
+file	arch/arm/marvell/pci_machdep.c		mvpex | gtpci
+
+device	pchb
+attach	pchb at pci
+file	dev/marvell/pchb.c			pchb
+
+# Serial-ATA II Host Controller (SATAHC)
+attach	mvsata at mvsoc with mvsata_mbus
+
+# Gigabit Ethernet Controller Interface
+attach	mvgbec at mvsoc with mvgbec_mbus
+
+# USB 2.0 Interface
+attach	ehci at mvsoc with mvusb_mbus
+
+# Cryptographic Engines and Security Accelerator
+#attach	mvcesa at mvsoc with mvcesa_mbus
+
+# TWSI Two-Wire Serial Interface
+attach	gttwsi at mvsoc with gttwsi_mbus
+
+# UART Interface
+attach	com at mvsoc with mvuart_mbus
+
+# IDMA Controller and XOR Engine
+attach	gtidmac at mvsoc with gtidmac_mbus
+
+# General Purpose I/O Port Interface
+device	mvsocgpp: gpiobus, pic
+attach	mvsocgpp at mvsoc
+file	arch/arm/marvell/mvsocgpp.c		mvsocgpp	needs-flag
+
+# Secure Digital Input/Output (SDIO) Interface
+attach	mvsdio at mvsoc with mvsdio_mbus
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/sys/arch/arm/marvell/kirkwood.c	Sat Oct 09 03:31:35 2010 +0000
@@ -0,0 +1,292 @@
+/*	$NetBSD: kirkwood.c,v 1.1.2.2 2010/10/09 03:31:40 yamt Exp $	*/
+/*
+ * Copyright (c) 2010 KIYOHARA Takashi
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>
+__KERNEL_RCSID(0, "$NetBSD: kirkwood.c,v 1.1.2.2 2010/10/09 03:31:40 yamt Exp $");
+
+#define _INTR_PRIVATE
+
+#include "mvsocgpp.h"
+
+#include <sys/param.h>
+#include <sys/bus.h>
+
+#include <machine/intr.h>
+
+#include <arm/pic/picvar.h>
+#include <arm/pic/picvar.h>
+
+#include <arm/marvell/mvsocreg.h>
+#include <arm/marvell/mvsocvar.h>
+#include <arm/marvell/kirkwoodreg.h>
+
+#include <dev/marvell/marvellreg.h>
+
+
+static void kirkwood_intr_init(void);
+
+static void kirkwood_pic_unblock_low_irqs(struct pic_softc *, size_t, uint32_t);
+static void kirkwood_pic_unblock_high_irqs(struct pic_softc *, size_t,
+					   uint32_t);
+static void kirkwood_pic_block_low_irqs(struct pic_softc *, size_t, uint32_t);
+static void kirkwood_pic_block_high_irqs(struct pic_softc *, size_t, uint32_t);
+static int kirkwood_pic_find_pending_high_irqs(struct pic_softc *);
+static void kirkwood_pic_establish_irq(struct pic_softc *, struct intrsource *);
+static void kirkwood_pic_source_name(struct pic_softc *, int, char *, size_t);
+
+static int kirkwood_find_pending_irqs(void);
+
+static const char * const sources[64] = {
+    "MainHighSum(0)",  "Bridge(1)",       "Host2CPU DB(2)",  "CPU2Host DB(3)",
+    "Reserved_4(4)",   "Xor0Chan0(5)",    "Xor0Chan1(6)",    "Xor1Chan0(7)",
+    "Xor1Chan1(8)",    "PEX0INT(9)",      "Reserved(10)",    "GbE0Sum(11)",
+    "GbE0Rx(12)",      "GbE0Tx(13)",      "GbE0Misc(14)",    "GbE1Sum(15)",
+    "GbE1Rx(16)",      "GbE1Tx(17)",      "GbE1Misc(18)",    "USB0Cnt(19)",
+    "Reserved(20)",    "Sata(21)",        "SecurityInt(22)", "SPIInt(23)",
+    "AudioINT(24)",    "Reserved(25)",    "TS0Int(26)",      "Reserved(27)",
+    "SDIOInt(28)",     "TWSI(29)",        "AVBInt(30)",      "TDMInt(31)"
+
+    "Reserved(32)",    "Uart0Int(33)",    "Uart1Int(34)",    "GPIOLo7_0(35)"
+    "GPIOLo8_15(36)",  "GPIOLo16_23(37)", "GPIOLo24_31(38)", "GPIOHi7_0(39)"
+    "GPIOHi8_15(40)",  "GPIOHi16_23(41)", "XOR0Err(42)",     "XOR1Err(43)"
+    "PEX0Err(44)",     "Reserved(45)",    "GbE0Err(46)",     "GbE1Err(47)"
+    "USBErr(48)",      "SecurityErr(49)", "AudioErr(50)",    "Reserved(51)"
+    "Reserved(52)",    "RTCInt(53)",      "Reserved(54)",    "Reserved(55)"
+    "Reserved(56)",    "Reserved(57)",    "Reserved(58)",    "Reserved(59)"
+    "Reserved(60)",    "Reserved(61)",    "Reserved(62)",    "Reserved(63)"
+};
+
+static struct pic_ops kirkwood_picops_low = {
+	.pic_unblock_irqs = kirkwood_pic_unblock_low_irqs,
+	.pic_block_irqs = kirkwood_pic_block_low_irqs,
+	.pic_establish_irq = kirkwood_pic_establish_irq,
+	.pic_source_name = kirkwood_pic_source_name,
+};
+static struct pic_ops kirkwood_picops_high = {
+	.pic_unblock_irqs = kirkwood_pic_unblock_high_irqs,
+	.pic_block_irqs = kirkwood_pic_block_high_irqs,
+	.pic_find_pending_irqs = kirkwood_pic_find_pending_high_irqs,
+	.pic_establish_irq = kirkwood_pic_establish_irq,
+	.pic_source_name = kirkwood_pic_source_name,
+};
+static struct pic_softc kirkwood_pic_low = {
+	.pic_ops = &kirkwood_picops_low,
+	.pic_maxsources = 32,
+	.pic_name = "kirkwood_low",
+};
+static struct pic_softc kirkwood_pic_high = {
+	.pic_ops = &kirkwood_picops_high,
+	.pic_maxsources = 32,
+	.pic_name = "kirkwood_high",
+};
+
+
+/*
+ * kirkwood_intr_bootstrap:
+ *
+ *	Initialize the rest of the interrupt subsystem, making it
+ *	ready to handle interrupts from devices.
+ */
+void
+kirkwood_intr_bootstrap(void)
+{
+	extern void (*mvsoc_intr_init)(void);
+
+	/* disable all interrupts */
+	write_mlmbreg(KIRKWOOD_MLMB_MIRQIMLR, 0);
+	write_mlmbreg(KIRKWOOD_MLMB_MIRQIMHR, 0);
+
+	/* disable all bridge interrupts */
+	write_mlmbreg(MVSOC_MLMB_MLMBIMR, 0);
+
+	mvsoc_intr_init = kirkwood_intr_init;
+
+#if NMVSOCGPP > 0
+	switch (mvsoc_model()) {
+	case MARVELL_KIRKWOOD_88F6180: gpp_npins = 30; break;
+	case MARVELL_KIRKWOOD_88F6192: gpp_npins = 36; break;
+	case MARVELL_KIRKWOOD_88F6281: gpp_npins = 50; break;
+	}
+	gpp_irqbase = 96;	/* Main Low(32) + High(32) + Bridge(32) */
+#endif
+}
+
+static void
+kirkwood_intr_init(void)
+{
+	extern struct pic_softc mvsoc_bridge_pic;
+	void *ih;
+
+	pic_add(&kirkwood_pic_low, 0);
+
+	pic_add(&kirkwood_pic_high, 32);
+	ih = intr_establish(KIRKWOOD_IRQ_HIGH, IPL_HIGH, IST_LEVEL_HIGH,
+	    pic_handle_intr, &kirkwood_pic_high);
+	KASSERT(ih != NULL);
+
+	pic_add(&mvsoc_bridge_pic, 64);
+	ih = intr_establish(KIRKWOOD_IRQ_BRIDGE, IPL_HIGH, IST_LEVEL_HIGH,
+	    pic_handle_intr, &mvsoc_bridge_pic);
+	KASSERT(ih != NULL);
+
+	find_pending_irqs = kirkwood_find_pending_irqs;
+}
+
+/* ARGSUSED */
+static void
+kirkwood_pic_unblock_low_irqs(struct pic_softc *pic, size_t irqbase,
+			      uint32_t irq_mask)
+{
+
+	write_mlmbreg(KIRKWOOD_MLMB_MIRQIMLR,
+	    read_mlmbreg(KIRKWOOD_MLMB_MIRQIMLR) | irq_mask);
+}
+
+/* ARGSUSED */
+static void
+kirkwood_pic_unblock_high_irqs(struct pic_softc *pic, size_t irqbase,
+			       uint32_t irq_mask)
+{
+
+	write_mlmbreg(KIRKWOOD_MLMB_MIRQIMHR,
+	    read_mlmbreg(KIRKWOOD_MLMB_MIRQIMHR) | irq_mask);
+}
+
+/* ARGSUSED */
+static void
+kirkwood_pic_block_low_irqs(struct pic_softc *pic, size_t irqbase,
+			    uint32_t irq_mask)
+{
+
+	write_mlmbreg(KIRKWOOD_MLMB_MIRQIMLR,
+	    read_mlmbreg(KIRKWOOD_MLMB_MIRQIMLR) & ~irq_mask);
+}
+
+/* ARGSUSED */
+static void
+kirkwood_pic_block_high_irqs(struct pic_softc *pic, size_t irqbase,
+			     uint32_t irq_mask)
+{
+
+	write_mlmbreg(KIRKWOOD_MLMB_MIRQIMHR,
+	    read_mlmbreg(KIRKWOOD_MLMB_MIRQIMHR) & ~irq_mask);
+}
+
+static int
+kirkwood_pic_find_pending_high_irqs(struct pic_softc *pic)
+{
+	uint32_t pending;
+
+	pending = read_mlmbreg(KIRKWOOD_MLMB_MICHR) &
+	    read_mlmbreg(KIRKWOOD_MLMB_MIRQIMHR);
+	if (pending == 0)
+		return 0;
+	pic_mark_pending_sources(pic, 0, pending);
+	return 1;
+}
+
+/* ARGSUSED */
+static void
+kirkwood_pic_establish_irq(struct pic_softc *pic, struct intrsource *is)
+{
+	/* Nothing */
+}
+
+static void
+kirkwood_pic_source_name(struct pic_softc *pic, int irq, char *buf, size_t len)
+{
+
+	strlcpy(buf, sources[pic->pic_irqbase + irq], len);
+}
+
+/*
+ * Called with interrupts disabled
+ */
+static int
+kirkwood_find_pending_irqs(void)
+{
+	uint32_t pending;
+
+	pending = read_mlmbreg(KIRKWOOD_MLMB_MICLR) &
+	    read_mlmbreg(KIRKWOOD_MLMB_MIRQIMLR);
+	if (pending == 0)
+		return 0;
+
+	return pic_mark_pending_sources(&kirkwood_pic_low, 0, pending);
+}
+
+/*
+ * Clock functions
+ */
+
+void
+kirkwood_getclks(bus_addr_t iobase)
+{
+	uint32_t reg;
+	uint16_t model;
+
+#define MHz	* 1000 * 1000
+
+	model = mvsoc_model();
+	if (model == MARVELL_KIRKWOOD_88F6281)
+		mvTclk = 200 MHz;
+	else		/* 166MHz */
+		mvTclk = 166666667;
+
+	reg = *(volatile uint32_t *)(iobase + KIRKWOOD_MPP_BASE +
+	    KIRKWOOD_MPP_SAMPLE_AT_RESET);
+	if (model == MARVELL_KIRKWOOD_88F6180) {
+		switch (reg & 0x0000001c) {
+		case 0x00000014: mvPclk =  600 MHz;
+		case 0x00000018: mvPclk =  800 MHz;
+		default:
+			panic("unknown mvPclk\n");
+		}
+		mvSysclk = 200 MHz;
+	} else {
+		switch (reg & 0x0040001a) {
+		case 0x00000008: mvPclk =  600 MHz; break;
+		case 0x00400008: mvPclk =  800 MHz; break;
+		case 0x0040000a: mvPclk = 1000 MHz; break;
+		case 0x00000012: mvPclk = 1200 MHz; break;
+		case 0x00000018: mvPclk = 1200 MHz; break;
+		default:
+			panic("unknown mvPclk\n");
+		}
+
+		switch (reg & 0x000001e0) {
+		case 0x00000060: mvSysclk = mvPclk * 2 / 5; break;
+		case 0x00000080: mvSysclk = mvPclk * 1 / 3; break;
+		case 0x000000c0: mvSysclk = mvPclk * 1 / 4; break;
+		default:
+			panic("unknown mvSysclk\n");
+		}
+	}
+
+#undef MHz
+
+}
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/sys/arch/arm/marvell/kirkwoodreg.h	Sat Oct 09 03:31:35 2010 +0000
@@ -0,0 +1,206 @@
+/*	$NetBSD: kirkwoodreg.h,v 1.1.2.2 2010/10/09 03:31:40 yamt Exp $	*/
+/*
+ * Copyright (c) 2007, 2008 KIYOHARA Takashi
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _KIRKWOODREG_H_
+#define _KIRKWOODREG_H_
+
+#include <arm/marvell/mvsocreg.h>
+#include <dev/marvell/mvgbereg.h>
+
+/*
+ *                MHz TCLK  GbE SATA  TDMI Audio MTS GPIO
+ * 6180:     600/800, 166,  x1,   -,    -,   o,   -,  30
+ * 6190:         600, 166, *x2,  x1,    -,   -,   -,  36	* GbEx1+100BTx1
+ * 6192:         800, 166,  x2,  x2,    o,   o,   o,  36
+ * 6281: 1.0/1.2/1.5, 200,  x2,  x2,    o,   o,   o,  50
+ */
+
+#define KIRKWOOD_UNITID_DDR		MVSOC_UNITID_DDR
+#define KIRKWOOD_UNITID_DEVBUS		MVSOC_UNITID_DEVBUS
+#define KIRKWOOD_UNITID_MLMB		MVSOC_UNITID_MLMB
+#define KIRKWOOD_UNITID_CRYPT		0x3	/* Cryptographic Engine reg */
+#define KIRKWOOD_UNITID_SA		0x3	/* Security Accelelerator reg */
+#define KIRKWOOD_UNITID_PEX		MVSOC_UNITID_PEX
+#define KIRKWOOD_UNITID_USB		0x5	/* USB registers */
+#define KIRKWOOD_UNITID_IDMA		0x6	/* IDMA registers */
+#define KIRKWOOD_UNITID_XOR		0x6	/* XOR registers */
+#define KIRKWOOD_UNITID_GBE		0x7	/* Gigabit Ethernet registers */
+#define KIRKWOOD_UNITID_SATA		0x8	/* SATA registers */
+#define KIRKWOOD_UNITID_SDIO		0x9	/* SDIO registers */
+#define KIRKWOOD_UNITID_AUDIO		0xa	/* Audio registers */
+#define KIRKWOOD_UNITID_MTS		0xb	/* MPEG Transport Stream reg */
+#define KIRKWOOD_UNITID_TDM		0xd	/* TDM registers */
+
+#define KIRKWOOD_ATTR_NAND		0x2f
+#define KIRKWOOD_ATTR_SPI		0x1e
+#define KIRKWOOD_ATTR_BOOTROM		0x1d
+#define KIRKWOOD_ATTR_PEX_MEM		0xe8
+#define KIRKWOOD_ATTR_PEX_IO		0xe0
+#define KIRKWOOD_ATTR_CRYPT		0x00
+
+#define KIRKWOOD_IRQ_HIGH		0	/* High interrupt */
+#define KIRKWOOD_IRQ_BRIDGE		1	/* Mbus-L to Mbus Bridge */
+#define KIRKWOOD_IRQ_H2CPUDB		2	/* Doorbell interrupt */
+#define KIRKWOOD_IRQ_CPU2HDB		3	/* Doorbell interrupt */
+#define KIRKWOOD_IRQ_XOR0CHAN0		5	/* Xor 0 Channel0 */
+#define KIRKWOOD_IRQ_XOR0CHAN1		6	/* Xor 0 Channel1 */
+#define KIRKWOOD_IRQ_XOR1CHAN0		7	/* Xor 1 Channel0 */
+#define KIRKWOOD_IRQ_XOR1CHAN1		8	/* Xor 1 Channel1 */
+#define KIRKWOOD_IRQ_PEX0INT		9	/* PCI Express port0 INT A-D */
+#define KIRKWOOD_IRQ_GBE0SUM		11	/* GbE0 summary */
+#define KIRKWOOD_IRQ_GBE0RX		12	/* GbE0 receive interrupt */
+#define KIRKWOOD_IRQ_GBE0TX		13	/* GbE0 transmit interrupt */
+#define KIRKWOOD_IRQ_GBE0MISC		14	/* GbE0 miscellaneous intr */
+#define KIRKWOOD_IRQ_GBE1SUM		15	/* GbE1 summary */
+#define KIRKWOOD_IRQ_GBE1RX		16	/* GbE1 receive interrupt */
+#define KIRKWOOD_IRQ_GBE1TX		17	/* GbE1 transmit interrupt */
+#define KIRKWOOD_IRQ_GBE1MISC		18	/* GbE1 miscellaneous intr */
+#define KIRKWOOD_IRQ_USB0CNT		19	/* USB0 controller interrupt */
+#define KIRKWOOD_IRQ_SATA		21	/*Sata ports interrupt summary*/
+#define KIRKWOOD_IRQ_SECURITYINT	22	/* Security engine completion */
+#define KIRKWOOD_IRQ_SPIINT		23	/* SPI Interrupt */
+#define KIRKWOOD_IRQ_AUDIOINT		24	/* Audio interrupt */
+#define KIRKWOOD_IRQ_TS0INT		26	/* TS0 Interrupt */
+#define KIRKWOOD_IRQ_SDIOINT		28	/* SDIO Interrupt */
+#define KIRKWOOD_IRQ_TWSI		29	/* TWSI interrupt */
+#define KIRKWOOD_IRQ_AVBINT		30	/* AVB Interrupt */
+#define KIRKWOOD_IRQ_TDMINT		31	/* TDM Interrupt */
+#define KIRKWOOD_IRQ_UART0INT		33	/* UART0 */
+#define KIRKWOOD_IRQ_UART1INT		34	/* UART1 */
+#define KIRKWOOD_IRQ_GPIOLO7_0		35	/* GPIO Low[7:0] */
+#define KIRKWOOD_IRQ_GPIOLO8_15		36	/* GPIO Low[15:8] */
+#define KIRKWOOD_IRQ_GPIOLO16_23	37	/* GPIO Low[23:16] */
+#define KIRKWOOD_IRQ_GPIOLO24_31	38	/* GPIO Low[31:24] */
+#define KIRKWOOD_IRQ_GPIOHI7_0		39	/* GPIO High[7:0] */
+#define KIRKWOOD_IRQ_GPIOHI8_15		40	/* GPIO High[15:8] */
+#define KIRKWOOD_IRQ_GPIOHI16_23	41	/* GPIO High[23:16] */
+#define KIRKWOOD_IRQ_XOR0ERR		42	/* XOR0 error */
+#define KIRKWOOD_IRQ_XOR1ERR		43	/* XOR1 error */
+#define KIRKWOOD_IRQ_PEX0ERR		44	/* PCI Express0 error */
+#define KIRKWOOD_IRQ_GBE0ERR		46	/* GbE port0 error */
+#define KIRKWOOD_IRQ_GBE1ERR		47	/* GbE port1 error */
+#define KIRKWOOD_IRQ_USBERR		48	/* USB error */
+#define KIRKWOOD_IRQ_SECURITYERR	49	/* Cryptographic engine error */
+#define KIRKWOOD_IRQ_AUDIOERR		50	/* Audio error */
+#define KIRKWOOD_IRQ_RTCINT		53	/* Real time clock interrupt */
+
+
+/*
+ * Physical address of integrated peripherals
+ */
+
+#define KIRKWOOD_UNITID2PHYS(uid)	((KIRKWOOD_UNITID_ ## uid) << 16)
+
+/*
+ * Pin Multiplexing Interface Registers
+ */
+#define KIRKWOOD_MPP_BASE		(MVSOC_DEVBUS_BASE + 0x0000)
+#define KIRKWOOD_MPP_SIZE		   0x40		/* XXXX */
+#define KIRKWOOD_MPP_MPPC0R		   0x00
+#define KIRKWOOD_MPP_MPPC1R		   0x04
+#define KIRKWOOD_MPP_MPPC2R		   0x08
+#define KIRKWOOD_MPP_MPPC3R		   0x0c
+#define KIRKWOOD_MPP_MPPC4R		   0x10
+#define KIRKWOOD_MPP_MPPC5R		   0x14
+#define KIRKWOOD_MPP_MPPC6R		   0x18
+#define KIRKWOOD_MPP_SAMPLE_AT_RESET	   0x30
+
+/*
+ * Real-Time Clock Unit Registers
+ */
+#define KIRKWOOD_RTC_BASE		(MVSOC_DEVBUS_BASE + 0x0300)
+
+/*
+ * Serial Peripheral Interface Registers
+ */
+#define KIRKWOOD_SPI_BASE		(MVSOC_DEVBUS_BASE + 0x0600)
+
+/*
+ * Mbus-L to Mbus Bridge Registers
+ */
+/* CPU Address Map Registers */
+#define KIRKWOOD_MLMB_NWINDOW		8
+#define KIRKWOOD_MLMB_NREMAP		4
+
+/* Main Interrupt Controller Registers */
+#define KIRKWOOD_MLMB_MICLR		  0x200	/*Main Interrupt Cause Low reg*/
+#define KIRKWOOD_MLMB_MIRQIMLR		  0x204	/*Main IRQ Interrupt Low Mask*/
+#define KIRKWOOD_MLMB_MFIQIMLR		  0x208	/*Main FIQ Interrupt Low Mask*/
+#define KIRKWOOD_MLMB_EIMLR		  0x20c	/*Endpoint Interrupt Low Mask*/
+#define KIRKWOOD_MLMB_MICHR		  0x210	/*Main Intr Cause High reg*/
+#define KIRKWOOD_MLMB_MIRQIMHR		  0x214	/*Main IRQ Interrupt High Mask*/
+#define KIRKWOOD_MLMB_MFIQIMHR		  0x218	/*Main FIQ Interrupt High Mask*/
+#define KIRKWOOD_MLMB_EIMHR		  0x21c	/*Endpoint Interrupt High Mask*/
+
+
+/*
+ * Cryptographic Engine and Security Accelerator Registers
+ */
+#define KIRKWOOD_CESA_BASE	(KIRKWOOD_UNITID2PHYS(CRYPT))	/* 0x30000 */
+
+/*
+ * USB 2.0 Interface Registers
+ */
+#define KIRKWOOD_USB_BASE	(KIRKWOOD_UNITID2PHYS(USB))	/* 0x50000 */
+
+/*
+ * IDMA Controller and XOR Engine Registers
+ */
+#define KIRKWOOD_IDMAC_BASE	(KIRKWOOD_UNITID2PHYS(IDMA))	/* 0x60000 */
+
+/*
+ * Gigabit Ethernet Registers
+ */
+#define KIRKWOOD_GBE0_BASE	(KIRKWOOD_UNITID2PHYS(GBE))	/* 0x70000 */
+#define KIRKWOOD_GBE1_BASE	(KIRKWOOD_GBE0_BASE + MVGBE_SIZE)
+
+/*
+ * Serial-ATA Host Controller (SATAHC) Registers
+ */
+#define KIRKWOOD_SATAHC_BASE	(KIRKWOOD_UNITID2PHYS(SATA))	/* 0x80000 */
+
+/*
+ * Secure Digital Input/Output (SDIO) Interface Registers
+ */
+#define KIRKWOOD_SDIO_BASE	(KIRKWOOD_UNITID2PHYS(SDIO))	/* 0x90000 */
+
+/*
+ * Audio (I2S/S/PDIF) Interface Registers
+ */
+#define KIRKWOOD_AUDIO_BASE	(KIRKWOOD_UNITID2PHYS(AUDIOSDIO))/* 0xa0000 */
+
+/*
+ * MPEG-2 Transport Stream (TS) Interface Registers
+ */
+#define KIRKWOOD_MTS_BASE	(KIRKWOOD_UNITID2PHYS(MTS))	/* 0xb0000 */
+
+/*
+ * Time Division Multiplexing (TDM) Unit Registers
+ */
+#define KIRKWOOD_TDM_BASE	(KIRKWOOD_UNITID2PHYS(TDM))	/* 0xd0000 */
+
+#endif	/* _KIRKWOODREG_H_ */
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/sys/arch/arm/marvell/mv78xx0reg.h	Sat Oct 09 03:31:35 2010 +0000
@@ -0,0 +1,206 @@
+/*	$NetBSD: mv78xx0reg.h,v 1.1.2.2 2010/10/09 03:31:40 yamt Exp $	*/
+/*
+ * Copyright (c) 2010 KIYOHARA Takashi
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _MV78XX0REG_H_
+#define _MV78XX0REG_H_
+
+#include <arm/marvell/mvsocreg.h>
+
+/*
+ *              MHz  PCIe  GbE  SATA TDMI  COM
+ * MV76100:    800, 2      x2,   x1,   -,  x3
+ * MV78100:    1.2, 2 x4,  x2,   x2,  x2,  x4
+ * MV78200: 1.0 x2, 2 x4,  x4,   x2,  x2,  x4
+ */
+
+#define MV78XX0_UNITID_DDR		MVSOC_UNITID_DDR
+#define MV78XX0_UNITID_DEVBUS		MVSOC_UNITID_DEVBUS
+#define MV78XX0_UNITID_LMB		MVSOC_UNITID_LMB
+#define MV78XX0_UNITID_GBE23		0x3	/* Gigabit Ethernet registers */
+#define MV78XX0_UNITID_PEX		MVSOC_UNITID_PEX
+#define MV78XX0_UNITID_USB		0x5	/* USB registers */
+#define MV78XX0_UNITID_IDMA		0x6	/* IDMA registers */
+#define MV78XX0_UNITID_XOR		0x6	/* XOR registers */
+#define MV78XX0_UNITID_GBE01		0x7	/* Gigabit Ethernet registers */
+#define MV78XX0_UNITID_CRYPT		0x9	/* Cryptographic Engine reg */
+#define MV78XX0_UNITID_SA		0x9	/* Security Accelelerator reg */
+#define MV78XX0_UNITID_SATA		0xa	/* SATA registers */
+#define MV78XX0_UNITID_TDM		0xb	/* TDM registers */
+
+#define MV78XX0_ATTR_DEVICE_CS0		0x3e
+#define MV78XX0_ATTR_DEVICE_CS1		0x3d
+#define MV78XX0_ATTR_DEVICE_CS2		0x3b
+#define MV78XX0_ATTR_DEVICE_CS2		0x37
+#define MV78XX0_ATTR_BOOT_CS		0x2f
+#define MV78XX0_ATTR_SPI		0x1f
+#define MV78XX0_ATTR_PEX_IO		0xe0	/* PCIe x4 Port 0.0 */
+#define MV78XX0_ATTR_PEX_MEM		0xe8
+#define MV78XX0_ATTR_PEX1_IO		0xe0	/* PCIe x1 Port 1 */
+#define MV78XX0_ATTR_PEX1_MEM		0xe8
+#define MV78XX0_ATTR_PEX_0_IO		0xe0	/* PCIe x1 Port 0.0 */
+#define MV78XX0_ATTR_PEX_0_MEM		0xe8
+#define MV78XX0_ATTR_PEX_1_IO		0xd0	/* PCIe x1 Port 0.1 */
+#define MV78XX0_ATTR_PEX_1_MEM		0xd8
+#define MV78XX0_ATTR_PEX_2_IO		0xb0	/* PCIe x1 Port 0.2 */
+#define MV78XX0_ATTR_PEX_2_MEM		0xb8
+#define MV78XX0_ATTR_PEX_3_IO		0x70	/* PCIe x1 Port 0.3 */
+#define MV78XX0_ATTR_PEX_3_MEM		0x78
+
+#define MV78XX0_IRQ_ERRSUM		0	/* Sum of Main Intr Err Cause */
+#define MV78XX0_IRQ_SPI			1	/* SPI */
+#define MV78XX0_IRQ_TWSI0		2	/* TWSI0 */
+#define MV78XX0_IRQ_TWSI1		3	/* TWSI1 */
+#define MV78XX0_IRQ_IDMA0		4	/* IDMA Channel0 completion */
+#define MV78XX0_IRQ_IDMA1		5	/* IDMA Channel1 completion */
+#define MV78XX0_IRQ_IDMA2		6	/* IDMA Channel2 completion */
+#define MV78XX0_IRQ_IDMA3		7	/* IDMA Channel3 completion */
+#define MV78XX0_IRQ_TIMER0		8	/* Timer0 */
+#define MV78XX0_IRQ_TIMER1		9	/* Timer1 */
+#define MV78XX0_IRQ_TIMER2		10	/* Timer2 */
+#define MV78XX0_IRQ_TIMER3		11	/* Timer3 */
+#define MV78XX0_IRQ_UART0		12	/* UART0 */
+#define MV78XX0_IRQ_UART1		13	/* UART1 */
+#define MV78XX0_IRQ_UART2		14	/* UART2 */
+#define MV78XX0_IRQ_UART3		15	/* UART3 */
+#define MV78XX0_IRQ_USB0		16	/* USB0 */
+#define MV78XX0_IRQ_USB1		17	/* USB1 */
+#define MV78XX0_IRQ_USB2		18	/* USB2 */
+#define MV78XX0_IRQ_CRYPTO		19	/* Crypto engine completion */
+#define MV78XX0_IRQ_XOR0		22	/* XOR engine 0 completion */
+#define MV78XX0_IRQ_XOR1		23	/* XOR engine 1 completion */
+#define MV78XX0_IRQ_SATA		26	/* SATA ports */
+#define MV78XX0_IRQ_TDMI_INT		27	/* TDM */
+#define MV78XX0_IRQ_PEX00INTA		32	/* PCIe Port0.0 INTA/B/C/D */
+#define MV78XX0_IRQ_PEX01INTA		33	/* PCIe Port0.1 INTA/B/C/D */
+#define MV78XX0_IRQ_PEX02INTA		34	/* PCIe Port0.2 INTA/B/C/D */
+#define MV78XX0_IRQ_PEX03INTA		35	/* PCIe Port0.3 INTA/B/C/D */
+#define MV78XX0_IRQ_PEX10INTA		36	/* PCIe Port1.0 INTA/B/C/D */
+#define MV78XX0_IRQ_PEX11INTA		37	/* PCIe Port1.1 INTA/B/C/D */
+#define MV78XX0_IRQ_PEX12INTA		38	/* PCIe Port1.2 INTA/B/C/D */
+#define MV78XX0_IRQ_PEX13INTA		39	/* PCIe Port1.3 INTA/B/C/D */
+#define MV78XX0_IRQ_GE00SUM		40	/* Gigabit Ethernet Port0 sum */
+#define MV78XX0_IRQ_GE00RX		41	/* Gigabit Ethernet Port0 Rx */
+#define MV78XX0_IRQ_GE00TX		42	/* Gigabit Ethernet Port0 Tx */
+#define MV78XX0_IRQ_GE00MISC		43	/* Gigabit Ethernet Port0 misc*/
+#define MV78XX0_IRQ_GE01SUM		44	/* Gigabit Ethernet Port1 sum */
+#define MV78XX0_IRQ_GE01RX		45	/* Gigabit Ethernet Port1 Rx */
+#define MV78XX0_IRQ_GE01TX		46	/* Gigabit Ethernet Port1 Tx */
+#define MV78XX0_IRQ_GE01MISC		47	/* Gigabit Ethernet Port1 misc*/
+#define MV78XX0_IRQ_GE10SUM		48	/* Gigabit Ethernet Port2 sum */
+#define MV78XX0_IRQ_GE10RX		49	/* Gigabit Ethernet Port2 Rx */
+#define MV78XX0_IRQ_GE10TX		50	/* Gigabit Ethernet Port2 Tx */
+#define MV78XX0_IRQ_GE10MISC		51	/* Gigabit Ethernet Port2 misc*/
+#define MV78XX0_IRQ_GE11SUM		52	/* Gigabit Ethernet Port3 sum */
+#define MV78XX0_IRQ_GE11RX		53	/* Gigabit Ethernet Port3 Rx */
+#define MV78XX0_IRQ_GE11TX		54	/* Gigabit Ethernet Port3 Tx */
+#define MV78XX0_IRQ_GE11MISC		55	/* Gigabit Ethernet Port3 misc*/
+#define MV78XX0_IRQ_GPIO0_7		56	/* GPIO[7:0] */
+#define MV78XX0_IRQ_GPIO8_15		57	/* GPIO[15:8] */
+#define MV78XX0_IRQ_GPIO16_23		58	/* GPIO[23:16] */
+#define MV78XX0_IRQ_GPIO24_31		59	/* GPIO[31:24] */
+#define MV78XX0_IRQ_DB_IN		60 /*Summary of Inbound Doorbell Cause*/
+#define MV78XX0_IRQ_DB_OUT		61/*Summary of Outbound Doorbell Cause*/
+
+
+/*
+ * Physical address of integrated peripherals
+ */
+
+#undef UNITID2PHYS
+#define UNITID2PHYS(uid)	((MV78XX0_UNITID_ ## uid) << 16)
+
+/*
+ * General Purpose Port Registers
+ */
+#define MV78XX0_GPP_BASE		(MVSOC_DEVBUS_BASE + 0x0100)
+#define MV78XX0_GPP_SIZE		  0x100
+
+/*
+ * UART Interface Registers
+ */
+					/* NS16550 compatible */
+#define MV78XX0_COM2_BASE		(MVSOC_DEVBUS_BASE + 0x2200)
+#define MV78XX0_COM3_BASE		(MVSOC_DEVBUS_BASE + 0x2300)
+
+/*
+ * Mbus-L to Mbus Bridge Registers
+ */
+/* CPU Address Map Registers */
+#define MV78XX0_MLMB_NWINDOW		14
+#define MV78XX0_MLMB_NREMAP		8
+
+/* Main Interrupt Controller Registers */
+#define MV78XX0_MLMB_MICLR		  0x200	/*Main Interrupt Cause Low reg*/
+#define MV78XX0_MLMB_MIRQIMLR		  0x204	/* Main IRQ Interrupt Mask */
+#define MV78XX0_MLMB_MFIQIMLR		  0x208	/* Main FIQ Interrupt Mask */
+#define MV78XX0_MLMB_EIMLR		  0x20c	/* Endpoint Interrupt Mask */
+#define MV78XX0_MLMB_MICHR		  0x210	/* Main Intr Cause High reg */
+#define MV78XX0_MLMB_MIRQIMHR		  0x214 /*Main IRQ Interrupt High Mask*/
+#define MV78XX0_MLMB_MFIQIMHR		  0x218 /*Main FIQ Interrupt High Mask*/
+#define MV78XX0_MLMB_EIMHR		  0x21c	/*Endpoint Interrupt High Mask*/
+
+/* CPU Timers Registers */
+/*   see oriontmrreg.h */
+
+
+/*
+ * PCI Express Interface Registers
+ */
+#define MV78XX0_PEX_BASE	(UNITID2PHYS(PEX))	/* 0x40000 */
+
+/*
+ * USB 2.0 Interface Registers
+ */
+#define MV78XX0_USB_BASE	(UNITID2PHYS(USB))	/* 0x50000 */
+
+/*
+ * IDMA Controller and XOR Engine Registers
+ */
+#define MV78XX0_IDMAC_BASE	(UNITID2PHYS(IDMA))	/* 0x60000 */
+
+/*
+ * Gigabit Ethernet Registers
+ */
+#define MV78XX0_GBE01_BASE	(UNITID2PHYS(GBE01))	/* 0x70000 */
+#define MV78XX0_GBE23_BASE	(UNITID2PHYS(GBE23))	/* 0x30000 */
+
+/*
+ * Cryptographic Engine and Security Accelerator Registers
+ */
+#define MV78XX0_CESA_BASE	(UNITID2PHYS(CRYPT))	/* 0x90000 */
+
+/*
+ * Serial-ATA Host Controller (SATAHC) Registers
+ */
+#define MV78XX0_SATAHC_BASE	(UNITID2PHYS(SATA))	/* 0xa0000 */
+
+/*
+ * Time Division Multiplexing (TDM) Unit Registers
+ */
+#define MV78XX0_TDM_BASE	(UNITID2PHYS(TDM))	/* 0xb0000 */
+
+#endif	/* _MV78XX0REG_H_ */
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/sys/arch/arm/marvell/mvsoc.c	Sat Oct 09 03:31:35 2010 +0000
@@ -0,0 +1,649 @@
+/*	$NetBSD: mvsoc.c,v 1.1.2.2 2010/10/09 03:31:40 yamt Exp $	*/
+/*
+ * Copyright (c) 2007, 2008 KIYOHARA Takashi
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>
+__KERNEL_RCSID(0, "$NetBSD: mvsoc.c,v 1.1.2.2 2010/10/09 03:31:40 yamt Exp $");
+
+#include "opt_cputypes.h"
+#include "opt_mvsoc.h"
+
+#include <sys/param.h>
+#include <sys/bus.h>
+#include <sys/device.h>
+#include <sys/errno.h>
+
+#include <dev/pci/pcidevs.h>
+#include <dev/pci/pcireg.h>
+#include <dev/marvell/marvellreg.h>
+#include <dev/marvell/marvellvar.h>
+
+#include <arm/marvell/mvsocreg.h>
+#include <arm/marvell/mvsocvar.h>
+#include <arm/marvell/orionreg.h>
+#include <arm/marvell/kirkwoodreg.h>
+
+#include "locators.h"
+
+
+static int mvsoc_match(device_t, struct cfdata *, void *);
+static void mvsoc_attach(device_t, device_t, void *);
+
+static int mvsoc_print(void *, const char *);
+static int mvsoc_search(device_t, cfdata_t, const int *, void *);
+
+uint32_t mvPclk, mvSysclk, mvTclk = 0;
+int nwindow = 0, nremap = 0;
+static vaddr_t regbase = 0xffffffff, dsc_base, pex_base;
+vaddr_t mlmb_base;
+
+void (*mvsoc_intr_init)(void);
+
+
+/* attributes */
+static struct {
+	int tag;
+	uint32_t attr;
+	uint32_t target;
+} mvsoc_tags[] = {
+	{ MARVELL_TAG_SDRAM_CS0,
+	  MARVELL_ATTR_SDRAM_CS0,	MVSOC_UNITID_DDR },
+	{ MARVELL_TAG_SDRAM_CS1,
+	  MARVELL_ATTR_SDRAM_CS1,	MVSOC_UNITID_DDR },
+	{ MARVELL_TAG_SDRAM_CS2,
+	  MARVELL_ATTR_SDRAM_CS2,	MVSOC_UNITID_DDR },
+	{ MARVELL_TAG_SDRAM_CS3,
+	  MARVELL_ATTR_SDRAM_CS3,	MVSOC_UNITID_DDR },
+
+#if defined(ORION)
+	{ ORION_TAG_DEVICE_CS0,
+	  ORION_ATTR_DEVICE_CS0,	MVSOC_UNITID_DEVBUS },
+	{ ORION_TAG_DEVICE_CS1,
+	  ORION_ATTR_DEVICE_CS1,	MVSOC_UNITID_DEVBUS },
+	{ ORION_TAG_DEVICE_CS2,
+	  ORION_ATTR_DEVICE_CS2,	MVSOC_UNITID_DEVBUS },
+	{ ORION_TAG_DEVICE_BOOTCS,
+	  ORION_ATTR_BOOT_CS,		MVSOC_UNITID_DEVBUS },
+	{ ORION_TAG_FLASH_CS,
+	  ORION_ATTR_FLASH_CS,		MVSOC_UNITID_DEVBUS },
+	{ ORION_TAG_PEX0_MEM,
+	  ORION_ATTR_PEX_MEM,		ORION_UNITID_PEX },
+	{ ORION_TAG_PEX0_IO,
+	  ORION_ATTR_PEX_IO,		ORION_UNITID_PEX },
+	{ ORION_TAG_PEX1_MEM,
+	  ORION_ATTR_PEX_MEM,		ORION_UNITID_PEX1 },
+	{ ORION_TAG_PEX1_IO,
+	  ORION_ATTR_PEX_IO,		ORION_UNITID_PEX1 },
+	{ ORION_TAG_PCI_MEM,
+	  ORION_ATTR_PCI_MEM,		ORION_UNITID_PCI },
+	{ ORION_TAG_PCI_IO,
+	  ORION_ATTR_PCI_IO,		ORION_UNITID_PCI },
+	{ ORION_TAG_CRYPT,
+	  ORION_ATTR_CRYPT,		ORION_UNITID_CRYPT },
+#endif
+
+#if defined(KIRKWOOD)
+	{ KIRKWOOD_TAG_NAND,
+	  KIRKWOOD_ATTR_NAND,		MVSOC_UNITID_DEVBUS },
+	{ KIRKWOOD_TAG_SPI,
+	  KIRKWOOD_ATTR_SPI,		MVSOC_UNITID_DEVBUS },
+	{ KIRKWOOD_TAG_BOOTROM,
+	  KIRKWOOD_ATTR_BOOTROM,	MVSOC_UNITID_DEVBUS },
+	{ KIRKWOOD_TAG_PEX_MEM,
+	  KIRKWOOD_ATTR_PEX_MEM,	KIRKWOOD_UNITID_PEX },
+	{ KIRKWOOD_TAG_PEX_IO,
+	  KIRKWOOD_ATTR_PEX_IO,		KIRKWOOD_UNITID_PEX },
+	{ KIRKWOOD_TAG_CRYPT,
+	  KIRKWOOD_ATTR_CRYPT,		KIRKWOOD_UNITID_CRYPT },
+#endif
+};
+
+#if defined(ORION)
+#define ORION_1(m)	MARVELL_ORION_1_ ## m
+#define ORION_2(m)	MARVELL_ORION_2_ ## m
+#endif
+#if defined(KIRKWOOD)
+#undef KIRKWOOD
+#define KIRKWOOD(m)	MARVELL_KIRKWOOD_ ## m
+#endif
+#if defined(MV78XX0)
+#undef MV78XX0
+#define MV78XX0(m)	MARVELL_MV78XX0_ ## m
+#endif
+static struct {
+	uint16_t model;
+	uint8_t rev;
+	const char *modelstr;
+	const char *revstr;
+	const char *typestr;
+} nametbl[] = {
+#if defined(ORION)
+	{ ORION_1(88F1181),	0, "MV88F1181", NULL,	"Orion1" },
+	{ ORION_1(88F5082),	2, "MV88F5082", "A2",	"Orion1" },
+	{ ORION_1(88F5180N),	3, "MV88F5180N","B1",	"Orion1" },
+	{ ORION_1(88F5181),	0, "MV88F5181",	"A0",	"Orion1" },
+	{ ORION_1(88F5181),	1, "MV88F5181",	"A1",	"Orion1" },
+	{ ORION_1(88F5181),	2, "MV88F5181",	"B0",	"Orion1" },
+	{ ORION_1(88F5181),	3, "MV88F5181",	"B1",	"Orion1" },
+	{ ORION_1(88F5181),	8, "MV88F5181L","A0",	"Orion1" },
+	{ ORION_1(88F5181),	9, "MV88F5181L","A1",	"Orion1" },
+	{ ORION_1(88F5182),	0, "MV88F5182",	"A0",	"Orion1" },
+	{ ORION_1(88F5182),	1, "MV88F5182",	"A1",	"Orion1" },
+	{ ORION_1(88F5182),	2, "MV88F5182",	"A2",	"Orion1" },
+	{ ORION_1(88F6082),	0, "MV88F6082",	"A0",	"Orion1" },
+	{ ORION_1(88F6082),	1, "MV88F6082",	"A1",	"Orion1" },
+	{ ORION_1(88F6183),	0, "MV88F6183",	"A0",	"Orion1" },
+	{ ORION_1(88F6183),	1, "MV88F6183",	"Z0",	"Orion1" },
+	{ ORION_1(88W8660),	0, "MV88W8660",	"A0",	"Orion1" },
+	{ ORION_1(88W8660),	1, "MV88W8660",	"A1",	"Orion1" },
+
+	{ ORION_2(88F1281),	0, "MV88F1281",	"A0",	"Orion2" },
+	{ ORION_2(88F5281),	0, "MV88F5281",	"A0",	"Orion2" },
+	{ ORION_2(88F5281),	1, "MV88F5281",	"B0",	"Orion2" },
+	{ ORION_2(88F5281),	2, "MV88F5281",	"C0",	"Orion2" },
+	{ ORION_2(88F5281),	3, "MV88F5281",	"C1",	"Orion2" },
+	{ ORION_2(88F5281),	4, "MV88F5281",	"D0",	"Orion2" },
+#endif
+
+#if defined(KIRKWOOD)
+	{ KIRKWOOD(88F6180),	2, "88F6180",	"A0",	"Kirkwood" },
+	{ KIRKWOOD(88F6192),	0, "88F619x",	"Z0",	"Kirkwood" },
+	{ KIRKWOOD(88F6192),	2, "88F619x",	"A0",	"Kirkwood" },
+	{ KIRKWOOD(88F6281),	0, "88F6281",	"Z0",	"Kirkwood" },
+	{ KIRKWOOD(88F6281),	2, "88F6281",	"A0",	"Kirkwood" },
+	{ KIRKWOOD(88F6281),	3, "88F6281",	"A1",	"Kirkwood" },
+#endif
+
+#if defined(MV78XX0)
+	{ MV78XX0(MV78100),	1, "MV78100",	"A0",  "Discovery Innovation" },
+	{ MV78XX0(MV78100),	2, "MV78100",	"A1",  "Discovery Innovation" },
+	{ MV78XX0(MV78200),	1, "MV78200",	"A0",  "Discovery Innovation" },
+#endif
+};
+
+#define OFFSET_DEFAULT	MVA_OFFSET_DEFAULT
+#define IRQ_DEFAULT	MVA_IRQ_DEFAULT
+static const struct mvsoc_periph {
+	int model;
+	const char *name;
+	int unit;
+	bus_size_t offset;
+	int irq;
+} mvsoc_periphs[] = {
+#if defined(ORION)
+    { ORION_1(88F1181),	"mvsoctmr",0, MVSOC_TMR_BASE,	IRQ_DEFAULT },
+    { ORION_1(88F1181),	"mvsocgpp",0, MVSOC_GPP_BASE,	ORION_IRQ_GPIO7_0 },
+    { ORION_1(88F1181),	"com",     0, MVSOC_COM0_BASE,	ORION_IRQ_UART0 },
+    { ORION_1(88F1181),	"com",     1, MVSOC_COM1_BASE,	ORION_IRQ_UART1 },
+    { ORION_1(88F1181),	"gttwsi",  0, MVSOC_TWSI_BASE,	ORION_IRQ_TWSI },
+    { ORION_1(88F1181),	"mvpex",   0, MVSOC_PEX_BASE,	ORION_IRQ_PEX0INT },
+    { ORION_1(88F1181),	"mvpex",   1, ORION_PEX1_BASE,	ORION_IRQ_PEX1INT },
+
+    { ORION_1(88F5082),	"mvsoctmr",0, MVSOC_TMR_BASE,	IRQ_DEFAULT },
+    { ORION_1(88F5082),	"mvsocgpp",0, MVSOC_GPP_BASE,	ORION_IRQ_GPIO7_0 },
+    { ORION_1(88F5082),	"com",     0, MVSOC_COM0_BASE,	ORION_IRQ_UART0 },
+    { ORION_1(88F5082),	"com",     1, MVSOC_COM1_BASE,	ORION_IRQ_UART1 },
+    { ORION_1(88F5082),	"ehci",    0, ORION_USB0_BASE,	ORION_IRQ_USBCNT0 },
+    { ORION_1(88F5082),	"ehci",    1, ORION_USB1_BASE,	ORION_IRQ_USBCNT1 },
+//  { ORION_1(88F5082),	"gtidmac", 0, ORION_IDMAC_BASE,	0 },
+    { ORION_1(88F5082),	"gttwsi",  0, MVSOC_TWSI_BASE,	ORION_IRQ_TWSI },
+    { ORION_1(88F5082),	"mvcesa",  0, ORION_CESA_BASE,	ORION_IRQ_SECURITYINTR},
+    { ORION_1(88F5082),	"mvgbec",  0, ORION_GBE_BASE,	IRQ_DEFAULT },
+    { ORION_1(88F5082),	"mvpex",   0, MVSOC_PEX_BASE,	ORION_IRQ_PEX0INT },
+    { ORION_1(88F5082),	"mvsata",  0, ORION_SATAHC_BASE,ORION_IRQ_SATAINTR },
+
+    { ORION_1(88F5180N),"mvsoctmr",0, MVSOC_TMR_BASE,	IRQ_DEFAULT },
+    { ORION_1(88F5180N),"mvsocgpp",0, MVSOC_GPP_BASE,	ORION_IRQ_GPIO7_0 },
+    { ORION_1(88F5180N),"com",     0, MVSOC_COM0_BASE,	ORION_IRQ_UART0 },
+    { ORION_1(88F5180N),"com",     1, MVSOC_COM1_BASE,	ORION_IRQ_UART1 },
+    { ORION_1(88F5180N),"ehci",    0, ORION_USB0_BASE,	ORION_IRQ_USBCNT0 },
+//  { ORION_1(88F5180N),"gtidmac", 0, ORION_IDMAC_BASE,	0 },
+    { ORION_1(88F5180N),"gtpci",   0, ORION_PCI_BASE,	ORION_IRQ_PEX0INT },
+    { ORION_1(88F5180N),"gttwsi",  0, MVSOC_TWSI_BASE,	ORION_IRQ_TWSI },
+    { ORION_1(88F5180N),"mvgbec",  0, ORION_GBE_BASE,	IRQ_DEFAULT },
+    { ORION_1(88F5180N),"mvpex",   0, MVSOC_PEX_BASE,	ORION_IRQ_PEX0INT },
+
+    { ORION_1(88F5181),	"mvsoctmr",0, MVSOC_TMR_BASE,	IRQ_DEFAULT },
+    { ORION_1(88F5181),	"mvsocgpp",0, MVSOC_GPP_BASE,	ORION_IRQ_GPIO7_0 },
+    { ORION_1(88F5181),	"com",     0, MVSOC_COM0_BASE,	ORION_IRQ_UART0 },
+    { ORION_1(88F5181),	"com",     1, MVSOC_COM1_BASE,	ORION_IRQ_UART1 },
+    { ORION_1(88F5181),	"ehci",    0, ORION_USB0_BASE,	ORION_IRQ_USBCNT0 },
+//  { ORION_1(88F5181),	"gtidmac", 0, ORION_IDMAC_BASE,	0 },
+    { ORION_1(88F5181),	"gtpci",   0, ORION_PCI_BASE,	ORION_IRQ_PEX0INT },
+    { ORION_1(88F5181),	"gttwsi",  0, MVSOC_TWSI_BASE,	ORION_IRQ_TWSI },
+    { ORION_1(88F5181),	"mvcesa",  0, ORION_CESA_BASE,	ORION_IRQ_SECURITYINTR},
+    { ORION_1(88F5181),	"mvgbec",  0, ORION_GBE_BASE,	IRQ_DEFAULT },
+    { ORION_1(88F5181),	"mvpex",   0, MVSOC_PEX_BASE,	ORION_IRQ_PEX0INT },
+
+    { ORION_1(88F5182),	"mvsoctmr",0, MVSOC_TMR_BASE,	IRQ_DEFAULT },
+    { ORION_1(88F5182),	"mvsocgpp",0, MVSOC_GPP_BASE,	ORION_IRQ_GPIO7_0 },
+    { ORION_1(88F5182),	"com",     0, MVSOC_COM0_BASE,	ORION_IRQ_UART0 },
+    { ORION_1(88F5182),	"com",     1, MVSOC_COM1_BASE,	ORION_IRQ_UART1 },
+    { ORION_1(88F5182),	"ehci",    0, ORION_USB0_BASE,	ORION_IRQ_USBCNT0 },
+    { ORION_1(88F5182),	"ehci",    1, ORION_USB1_BASE,	ORION_IRQ_USBCNT1 },
+//  { ORION_1(88F5182),	"gtidmac", 0, ORION_IDMAC_BASE,	0 },
+    { ORION_1(88F5182),	"gtpci",   0, ORION_PCI_BASE,	ORION_IRQ_PEX0INT },
+    { ORION_1(88F5182),	"gttwsi",  0, MVSOC_TWSI_BASE,	ORION_IRQ_TWSI },
+    { ORION_1(88F5182),	"mvgbec",  0, ORION_GBE_BASE,	IRQ_DEFAULT },
+    { ORION_1(88F5182),	"mvsata",  0, ORION_SATAHC_BASE,ORION_IRQ_SATAINTR },
+    { ORION_1(88F5182),	"mvpex",   0, MVSOC_PEX_BASE,	ORION_IRQ_PEX0INT },
+
+    { ORION_1(88F6082),	"mvsoctmr",0, MVSOC_TMR_BASE,	IRQ_DEFAULT },
+    { ORION_1(88F6082),	"mvsocgpp",0, MVSOC_GPP_BASE,	ORION_IRQ_GPIO7_0 },
+    { ORION_1(88F6082),	"com",     0, MVSOC_COM0_BASE,	ORION_IRQ_UART0 },
+    { ORION_1(88F6082),	"com",     1, MVSOC_COM1_BASE,	ORION_IRQ_UART1 },
+    { ORION_1(88F6082),	"ehci",    0, ORION_USB0_BASE,	ORION_IRQ_USBCNT0 },
+    { ORION_1(88F6082),	"gttwsi",  0, MVSOC_TWSI_BASE,	ORION_IRQ_TWSI },
+    { ORION_1(88F6082),	"mvcesa",  0, ORION_CESA_BASE,	ORION_IRQ_SECURITYINTR},
+    { ORION_1(88F6082),	"mvgbec",  0, ORION_GBE_BASE,	IRQ_DEFAULT },
+    { ORION_1(88F6082),	"mvsata",  0, ORION_SATAHC_BASE,ORION_IRQ_SATAINTR },
+    { ORION_1(88F6082),	"mvpex",   0, MVSOC_PEX_BASE,	ORION_IRQ_PEX0INT },
+
+    { ORION_1(88F6183),	"mvsoctmr",0, MVSOC_TMR_BASE,	IRQ_DEFAULT },
+    { ORION_1(88F6183),	"mvsocgpp",0, MVSOC_GPP_BASE,	ORION_IRQ_GPIO7_0 },
+    { ORION_1(88F6183),	"gttwsi",  0, MVSOC_TWSI_BASE,	ORION_IRQ_TWSI },
+    { ORION_1(88F6183),	"mvpex",   0, MVSOC_PEX_BASE,	ORION_IRQ_PEX0INT },
+
+    { ORION_1(88W8660),	"mvsoctmr",0, MVSOC_TMR_BASE,	IRQ_DEFAULT },
+    { ORION_1(88W8660),	"mvsocgpp",0, MVSOC_GPP_BASE,	ORION_IRQ_GPIO7_0 },
+    { ORION_1(88W8660),	"com",     0, MVSOC_COM0_BASE,	ORION_IRQ_UART0 },
+    { ORION_1(88W8660),	"com",     1, MVSOC_COM1_BASE,	ORION_IRQ_UART1 },
+    { ORION_1(88W8660),	"ehci",    0, ORION_USB0_BASE,	ORION_IRQ_USBCNT0 },
+//  { ORION_1(88W8660),	"gtidmac", 0, ORION_IDMAC_BASE,	0 },
+    { ORION_1(88W8660),	"gtpci",   0, ORION_PCI_BASE,	ORION_IRQ_PEX0INT },
+    { ORION_1(88W8660),	"gttwsi",  0, MVSOC_TWSI_BASE,	ORION_IRQ_TWSI },
+    { ORION_1(88W8660),	"mvgbec",  0, ORION_GBE_BASE,	IRQ_DEFAULT },
+    { ORION_1(88W8660),	"mvpex",   0, MVSOC_PEX_BASE,	ORION_IRQ_PEX0INT },
+
+    { ORION_2(88F1281),	"mvsoctmr",0, MVSOC_TMR_BASE,	IRQ_DEFAULT },
+    { ORION_2(88F1281),	"mvsocgpp",0, MVSOC_GPP_BASE,	ORION_IRQ_GPIO7_0 },
+    { ORION_2(88F1281),	"com",     0, MVSOC_COM0_BASE,	ORION_IRQ_UART0 },
+    { ORION_2(88F1281),	"com",     1, MVSOC_COM1_BASE,	ORION_IRQ_UART1 },
+    { ORION_2(88F1281),	"gttwsi",  0, MVSOC_TWSI_BASE,	ORION_IRQ_TWSI },
+    { ORION_2(88F1281),	"mvpex",   0, MVSOC_PEX_BASE,	ORION_IRQ_PEX0INT },
+    { ORION_2(88F1281),	"mvpex",   1, ORION_PEX1_BASE,	ORION_IRQ_PEX1INT },
+
+    { ORION_2(88F5281),	"mvsoctmr",0, MVSOC_TMR_BASE,	IRQ_DEFAULT },
+    { ORION_2(88F5281),	"mvsocgpp",0, MVSOC_GPP_BASE,	ORION_IRQ_GPIO7_0 },
+    { ORION_2(88F5281),	"com",     0, MVSOC_COM0_BASE,	ORION_IRQ_UART0 },
+    { ORION_2(88F5281),	"com",     1, MVSOC_COM1_BASE,	ORION_IRQ_UART1 },
+    { ORION_2(88F5281),	"ehci",    0, ORION_USB0_BASE,	ORION_IRQ_USBCNT0 },
+//  { ORION_2(88F5281),	"gtidmac", 0, ORION_IDMAC_BASE,	0 },
+    { ORION_2(88F5281),	"gtpci",   0, ORION_PCI_BASE,	ORION_IRQ_PEX0INT },
+    { ORION_2(88F5281),	"gttwsi",  0, MVSOC_TWSI_BASE,	ORION_IRQ_TWSI },
+    { ORION_2(88F5281),	"mvgbec",  0, ORION_GBE_BASE,	IRQ_DEFAULT },
+    { ORION_2(88F5281),	"mvpex",   0, MVSOC_PEX_BASE,	ORION_IRQ_PEX0INT },
+#endif
+
+#if defined(KIRKWOOD)
+    { KIRKWOOD(88F6180),"mvsoctmr",0, MVSOC_TMR_BASE,	IRQ_DEFAULT },
+    { KIRKWOOD(88F6180),"mvsocgpp",0, MVSOC_GPP_BASE,	KIRKWOOD_IRQ_GPIOLO7_0},
+    { KIRKWOOD(88F6180),"com",     0, MVSOC_COM0_BASE,	KIRKWOOD_IRQ_UART0INT },
+    { KIRKWOOD(88F6180),"com",     1, MVSOC_COM1_BASE,	KIRKWOOD_IRQ_UART1INT },
+    { KIRKWOOD(88F6180),"ehci",    0, KIRKWOOD_USB_BASE,KIRKWOOD_IRQ_USB0CNT },
+//  { KIRKWOOD(88F6180),"gtidmac", 0, KIRKWOOD_IDMAC_BASE,? },
+    { KIRKWOOD(88F6180),"gttwsi",  0, MVSOC_TWSI_BASE,	KIRKWOOD_IRQ_TWSI },
+    { KIRKWOOD(88F6180),"mvcesa",  0, KIRKWOOD_CESA_BASE,KIRKWOOD_IRQ_SECURITYINT},
+    { KIRKWOOD(88F6180),"mvgbec",  0, KIRKWOOD_GBE0_BASE,IRQ_DEFAULT },
+    { KIRKWOOD(88F6180),"mvpex",   0, MVSOC_PEX_BASE,	KIRKWOOD_IRQ_PEX0INT },
+    { KIRKWOOD(88F6180),"mvsdio",  0, KIRKWOOD_SDIO_BASE,KIRKWOOD_IRQ_SDIOINT },
+
+    { KIRKWOOD(88F6192),"mvsoctmr",0, MVSOC_TMR_BASE,	IRQ_DEFAULT },
+    { KIRKWOOD(88F6192),"mvsocgpp",0, MVSOC_GPP_BASE,	KIRKWOOD_IRQ_GPIOLO7_0},
+    { KIRKWOOD(88F6192),"com",     0, MVSOC_COM0_BASE,	KIRKWOOD_IRQ_UART0INT },
+    { KIRKWOOD(88F6192),"com",     1, MVSOC_COM1_BASE,	KIRKWOOD_IRQ_UART1INT },
+    { KIRKWOOD(88F6192),"ehci",    0, KIRKWOOD_USB_BASE,KIRKWOOD_IRQ_USB0CNT },
+//  { KIRKWOOD(88F6192),"gtidmac", 0, KIRKWOOD_IDMAC_BASE,? },
+    { KIRKWOOD(88F6192),"gttwsi",  0, MVSOC_TWSI_BASE,	KIRKWOOD_IRQ_TWSI },
+    { KIRKWOOD(88F6192),"mvcesa",  0, KIRKWOOD_CESA_BASE,KIRKWOOD_IRQ_SECURITYINT},
+    { KIRKWOOD(88F6192),"mvgbec",  0, KIRKWOOD_GBE0_BASE,IRQ_DEFAULT },
+    { KIRKWOOD(88F6192),"mvgbec",  1, KIRKWOOD_GBE1_BASE,IRQ_DEFAULT },
+    { KIRKWOOD(88F6192),"mvpex",   0, MVSOC_PEX_BASE,	KIRKWOOD_IRQ_PEX0INT },
+    { KIRKWOOD(88F6192),"mvsata",  0, KIRKWOOD_SATAHC_BASE,KIRKWOOD_IRQ_SATA },
+    { KIRKWOOD(88F6192),"mvsdio",  0, KIRKWOOD_SDIO_BASE,KIRKWOOD_IRQ_SDIOINT },
+
+    { KIRKWOOD(88F6281),"mvsoctmr",0, MVSOC_TMR_BASE,	IRQ_DEFAULT },
+    { KIRKWOOD(88F6281),"mvsocgpp",0, MVSOC_GPP_BASE,	KIRKWOOD_IRQ_GPIOLO7_0},
+    { KIRKWOOD(88F6281),"com",     0, MVSOC_COM0_BASE,	KIRKWOOD_IRQ_UART0INT },
+    { KIRKWOOD(88F6281),"com",     1, MVSOC_COM1_BASE,	KIRKWOOD_IRQ_UART1INT },
+    { KIRKWOOD(88F6281),"ehci",    0, KIRKWOOD_USB_BASE,KIRKWOOD_IRQ_USB0CNT },
+//  { KIRKWOOD(88F6281),"gtidmac", 0, KIRKWOOD_IDMAC_BASE,? },
+    { KIRKWOOD(88F6281),"gttwsi",  0, MVSOC_TWSI_BASE,	KIRKWOOD_IRQ_TWSI },
+    { KIRKWOOD(88F6281),"mvcesa",  0, KIRKWOOD_CESA_BASE,KIRKWOOD_IRQ_SECURITYINT},
+    { KIRKWOOD(88F6281),"mvgbec",  0, KIRKWOOD_GBE0_BASE,IRQ_DEFAULT },
+    { KIRKWOOD(88F6281),"mvgbec",  1, KIRKWOOD_GBE1_BASE,IRQ_DEFAULT },
+    { KIRKWOOD(88F6281),"mvpex",   0, MVSOC_PEX_BASE,	KIRKWOOD_IRQ_PEX0INT },
+    { KIRKWOOD(88F6281),"mvsata",  0, KIRKWOOD_SATAHC_BASE,KIRKWOOD_IRQ_SATA },
+    { KIRKWOOD(88F6281),"mvsdio",  0, KIRKWOOD_SDIO_BASE,KIRKWOOD_IRQ_SDIOINT },
+#endif
+
+#if defined(MV78XX0)
+    { MV78XX0(MV78100),	"mvsoctmr",0,MVSOC_TMR_BASE,	IRQ_DEFAULT },
+    { MV78XX0(MV78100),	"mvsocgpp",0,MVSOC_GPP_BASE,	MV78XX0_IRQ_GPIOLO7_0 },
+    { MV78XX0(MV78100),	"com",	0, MVSOC_COM0_BASE,	MV78XX0_IRQ_UART0INT },
+    { MV78XX0(MV78100),	"com",	1, MVSOC_COM1_BASE,	MV78XX0_IRQ_UART1INT },
+    { MV78XX0(MV78100),	"gttwsi",0,MVSOC_TWSI_BASE,	MV78XX0_IRQ_TWSI },
+      :
+
+    { MV78XX0(MV78200),	"mvsoctmr",0,MVSOC_TMR_BASE,	IRQ_DEFAULT },
+    { MV78XX0(MV78200),	"mvsocgpp",0,MVSOC_GPP_BASE,	MV78XX0_IRQ_GPIOLO7_0 },
+    { MV78XX0(MV78200),	"com",	0, MVSOC_COM0_BASE,	MV78XX0_IRQ_UART0INT },
+    { MV78XX0(MV78200),	"com",	1, MVSOC_COM1_BASE,	MV78XX0_IRQ_UART1INT },
+    { MV78XX0(MV78200),	"gttwsi",0,MVSOC_TWSI_BASE,	MV78XX0_IRQ_TWSI },
+      :
+#endif
+};
+
+
+CFATTACH_DECL_NEW(mvsoc, sizeof(struct mvsoc_softc),
+    mvsoc_match, mvsoc_attach, NULL, NULL);
+
+/* ARGSUSED */
+static int
+mvsoc_match(device_t parent, struct cfdata *match, void *aux)
+{
+
+	return 1;
+}
+
+/* ARGSUSED */
+static void
+mvsoc_attach(device_t parent, device_t self, void *aux)
+{
+	struct mvsoc_softc *sc = device_private(self);
+	struct marvell_attach_args mva;
+	uint16_t model;
+	uint8_t rev;
+	int i;
+
+	sc->sc_dev = self;
+	sc->sc_iot = &mvsoc_bs_tag;
+	sc->sc_addr = regbase;
+	sc->sc_dmat = &mvsoc_bus_dma_tag;
+	if (bus_space_map(sc->sc_iot, sc->sc_addr, 0x100000, 0, &sc->sc_ioh) !=
+	    0) {
+		aprint_error_dev(self, "can't map registers\n");
+		return;
+	}
+
+	model = mvsoc_model();
+	rev = mvsoc_rev();
+	for (i = 0; i < __arraycount(nametbl); i++)
+		if (nametbl[i].model == model && nametbl[i].rev == rev)
+			break;
+	if (i >= __arraycount(nametbl))
+		panic("unknown SoC: model 0x%04x, rev 0x%02x", model, rev);
+
+	aprint_normal(": Marvell %s %s%s  %s\n",
+	    nametbl[i].modelstr,
+	    nametbl[i].revstr != NULL ? "Rev. " : "",
+	    nametbl[i].revstr != NULL ? nametbl[i].revstr : "",
+	    nametbl[i].typestr);
+        aprint_normal("%s: CPU Clock %d.%03d MHz"
+	    "  SysClock %d.%03d MHz  TClock %d.%03d MHz\n",
+	    device_xname(self),
+	    mvPclk / 1000000, (mvPclk / 1000) % 1000,
+	    mvSysclk / 1000000, (mvSysclk / 1000) % 1000,
+	    mvTclk / 1000000, (mvTclk / 1000) % 1000);
+	aprint_naive("\n");
+
+	mvsoc_intr_init();
+
+	for (i = 0; i < __arraycount(mvsoc_periphs); i++) {
+		if (mvsoc_periphs[i].model != model)
+			continue;
+
+		mva.mva_name = mvsoc_periphs[i].name;
+		mva.mva_model = model;
+		mva.mva_revision = rev;
+		mva.mva_iot = sc->sc_iot;
+		mva.mva_ioh = sc->sc_ioh;
+		mva.mva_unit = mvsoc_periphs[i].unit;
+		mva.mva_addr = sc->sc_addr;
+		mva.mva_offset = mvsoc_periphs[i].offset;
+		mva.mva_size = 0;
+		mva.mva_dmat = sc->sc_dmat;
+		mva.mva_irq = mvsoc_periphs[i].irq;
+
+		config_found_sm_loc(sc->sc_dev, "mvsoc", NULL, &mva,
+		    mvsoc_print, mvsoc_search);
+	}
+}
+
+static int
+mvsoc_print(void *aux, const char *pnp)
+{
+	struct marvell_attach_args *mva = aux;
+
+	if (pnp)
+		aprint_normal("%s at %s unit %d",
+		    mva->mva_name, pnp, mva->mva_unit);
+	else {
+		if (mva->mva_unit != MVA_UNIT_DEFAULT)
+			aprint_normal(" unit %d", mva->mva_unit);
+		if (mva->mva_offset != MVA_OFFSET_DEFAULT) {
+			aprint_normal(" offset 0x%04lx", mva->mva_offset);
+			if (mva->mva_size > 0)
+				aprint_normal("-0x%04lx",
+				    mva->mva_offset + mva->mva_size - 1);
+		}
+		if (mva->mva_irq != MVA_IRQ_DEFAULT)
+			aprint_normal(" irq %d", mva->mva_irq);
+	}
+
+	return UNCONF;
+}
+
+/* ARGSUSED */
+static int
+mvsoc_search(device_t parent, cfdata_t cf, const int *ldesc, void *aux)
+{
+
+	return config_match(parent, cf, aux);
+}
+
+/* ARGSUSED */
+int
+marvell_winparams_by_tag(device_t dev, int tag, int *target, int *attribute,
+			 uint64_t *base, uint32_t *size)
+{
+	uint32_t base32;
+	int rv;
+
+	rv = mvsoc_target(tag, target, attribute, &base32, size);
+	*base = base32;
+	if (rv == -1)
+		return -1;
+	return 0;
+}
+
+
+/*
+ * These functions is called before bus_space is initialized.
+ */
+
+void
+mvsoc_bootstrap(bus_addr_t iobase)
+{
+
+	regbase = iobase;
+	dsc_base = iobase + MVSOC_DSC_BASE;
+	mlmb_base = iobase + MVSOC_MLMB_BASE;
+	pex_base = iobase + MVSOC_PEX_BASE;
+}
+
+/*
+ * We can read register of PCI configurations from (MVSOC_PEX_BASE + 0).
+ */
+uint16_t
+mvsoc_model()
+{
+	/*
+	 * We read product-id from vendor/device register of PCI-Express.
+	 */
+	uint32_t reg;
+	uint16_t model;
+
+	KASSERT(regbase != 0xffffffff);
+
+	reg = *(volatile uint32_t *)(pex_base + PCI_ID_REG);
+	model = PCI_PRODUCT(reg);
+
+#if defined(ORION)
+	if (model == PCI_PRODUCT_MARVELL_88F5182) {
+		reg = *(volatile uint32_t *)(regbase + ORION_PMI_BASE +
+		    ORION_PMI_SAMPLE_AT_RESET);
+		if ((reg & ORION_PMISMPL_TCLK_MASK) == 0)
+			model = PCI_PRODUCT_MARVELL_88F5082;
+	}
+#endif
+
+	return model;
+}
+
+uint8_t
+mvsoc_rev()
+{
+	uint32_t reg;
+	uint8_t rev;
+
+	KASSERT(regbase != 0xffffffff);
+
+	reg = *(volatile uint32_t *)(pex_base + PCI_CLASS_REG);
+	rev = PCI_REVISION(reg);
+
+	return rev;
+}
+
+
+int
+mvsoc_target(int tag, uint32_t *target, uint32_t *attr, uint32_t *base,
+	     uint32_t *size)
+{
+	int i;
+
+	KASSERT(regbase != 0xffffffff);
+
+	if (tag == MVSOC_TAG_INTERNALREG) {
+		if (target != NULL)
+			*target = 0;
+		if (attr != NULL)
+			*attr = 0;
+		if (base != NULL)
+			*base = read_mlmbreg(MVSOC_MLMB_IRBAR) &
+			    MVSOC_MLMB_IRBAR_BASE_MASK;
+		if (size != NULL)
+			*size = 0;
+
+		return 0;
+	}
+
+	/* sanity check */
+	for (i = 0; i < __arraycount(mvsoc_tags); i++)
+		if (mvsoc_tags[i].tag == tag)
+			break;
+	if (i >= __arraycount(mvsoc_tags))
+		return -1;
+
+	if (target != NULL)
+		*target = mvsoc_tags[i].target;
+	if (attr != NULL)
+		*attr = mvsoc_tags[i].attr;
+
+	if (mvsoc_tags[i].target == MVSOC_UNITID_DDR) {
+		/*
+		 * Read DDR SDRAM Controller Address Decode Registers
+		 */
+		uint32_t baseaddrreg, sizereg;
+		int cs = 0;
+
+		switch (mvsoc_tags[i].attr) {
+		case MARVELL_ATTR_SDRAM_CS0:
+			cs = 0;
+			break;
+		case MARVELL_ATTR_SDRAM_CS1:
+			cs = 1;
+			break;
+		case MARVELL_ATTR_SDRAM_CS2:
+			cs = 2;
+			break;
+		case MARVELL_ATTR_SDRAM_CS3:
+			cs = 3;
+			break;
+		}
+		sizereg = *(volatile uint32_t *)(dsc_base + MVSOC_DSC_CSSR(cs));
+		if (sizereg & MVSOC_DSC_CSSR_WINEN) {
+			baseaddrreg = *(volatile uint32_t *)(dsc_base +
+			    MVSOC_DSC_CSBAR(cs));
+
+			if (base != NULL)
+				*base = baseaddrreg & MVSOC_DSC_CSBAR_BASE_MASK;
+			if (size != NULL)
+				*size = (sizereg & MVSOC_DSC_CSSR_SIZE_MASK) +
+				    (~MVSOC_DSC_CSSR_SIZE_MASK + 1);
+		} else {
+			if (base != NULL)
+				*base = 0;
+			if (size != NULL)
+				*size = 0;
+		}
+		return 0;
+	} else {
+		/*
+		 * Read CPU Address Map Registers
+		 */
+		uint32_t basereg, ctrlreg, ta, tamask;
+
+		ta = MVSOC_MLMB_WCR_TARGET(mvsoc_tags[i].target) |
+		    MVSOC_MLMB_WCR_ATTR(mvsoc_tags[i].attr);
+		tamask = MVSOC_MLMB_WCR_TARGET(MVSOC_UNITID_MASK) |
+		    MVSOC_MLMB_WCR_ATTR(MARVELL_ATTR_MASK);
+
+		if (base != NULL)
+			*base = 0;
+		if (size != NULL)
+			*size = 0;
+
+		for (i = 0; i < nwindow; i++) {
+			ctrlreg = read_mlmbreg(MVSOC_MLMB_WCR(i));
+			if ((ctrlreg & tamask) != ta)
+				continue;
+			if (ctrlreg & MVSOC_MLMB_WCR_WINEN) {
+				basereg = read_mlmbreg(MVSOC_MLMB_WBR(i));
+
+				if (base != NULL)
+					*base =
+					    basereg & MVSOC_MLMB_WBR_BASE_MASK;
+				if (size != NULL)
+					*size = (ctrlreg &
+					    MVSOC_MLMB_WCR_SIZE_MASK) +
+					    (~MVSOC_MLMB_WCR_SIZE_MASK + 1);
+			}
+			break;
+		}
+		return i;
+	}
+}
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/sys/arch/arm/marvell/mvsoc_dma.c	Sat Oct 09 03:31:35 2010 +0000
@@ -0,0 +1,74 @@
+/*	$NetBSD: mvsoc_dma.c,v 1.1.2.2 2010/10/09 03:31:40 yamt Exp $ */
+
+/*
+ * Copyright (c) 2004 Jesse Off
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of The Fujitsu Component Limited nor the name of
+ *    Genetec corporation may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY FUJITSU COMPONENT LIMITED AND GENETEC
+ * CORPORATION ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES,
+ * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED.  IN NO EVENT SHALL FUJITSU COMPONENT LIMITED OR GENETEC
+ * CORPORATION BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
+ * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+/*
+ * bus_dma tag for MV88Fxx81 Orion
+ */
+
+#include <sys/cdefs.h>
+__KERNEL_RCSID(0, "$NetBSD: mvsoc_dma.c,v 1.1.2.2 2010/10/09 03:31:40 yamt Exp $");
+
+#define _ARM32_BUS_DMA_PRIVATE
+
+#include <sys/param.h>
+#include <sys/types.h>
+#include <sys/device.h>
+#include <sys/systm.h>
+#include <sys/extent.h>
+
+#include <machine/bus.h>
+
+#include <arm/marvell/mvsocvar.h>
+
+struct arm32_bus_dma_tag mvsoc_bus_dma_tag = {
+	NULL,			/* _ranges: set by platform specific routine */
+	0,			/* _nranges */
+
+	NULL,			/* _cookie */
+
+	_bus_dmamap_create,
+	_bus_dmamap_destroy,
+	_bus_dmamap_load,
+	_bus_dmamap_load_mbuf,
+	_bus_dmamap_load_uio,
+	_bus_dmamap_load_raw,
+	_bus_dmamap_unload,
+	_bus_dmamap_sync,
+	NULL,			/* sync_post */
+
+	_bus_dmamem_alloc,
+	_bus_dmamem_free,
+	_bus_dmamem_map,
+	_bus_dmamem_unmap,
+	_bus_dmamem_mmap,
+};
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/sys/arch/arm/marvell/mvsoc_intr.c	Sat Oct 09 03:31:35 2010 +0000
@@ -0,0 +1,153 @@
+/*	$NetBSD: mvsoc_intr.c,v 1.1.2.2 2010/10/09 03:31:40 yamt Exp $	*/
+/*
+ * Copyright (c) 2010 KIYOHARA Takashi
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>
+__KERNEL_RCSID(0, "$NetBSD: mvsoc_intr.c,v 1.1.2.2 2010/10/09 03:31:40 yamt Exp $");
+
+#define _INTR_PRIVATE
+
+#include <sys/param.h>
+#include <sys/proc.h>
+
+#include <uvm/uvm_extern.h>
+
+#include <machine/intr.h>
+
+#include <arm/cpu.h>
+#include <arm/pic/picvar.h>
+#include <arm/marvell/mvsocreg.h>
+#include <arm/marvell/mvsocvar.h>
+
+
+static void mvsoc_bridge_pic_unblock_irqs(struct pic_softc *, size_t, uint32_t);
+static void mvsoc_bridge_pic_block_irqs(struct pic_softc *, size_t, uint32_t);
+static int mvsoc_bridge_pic_find_pending_irqs(struct pic_softc *);
+static void mvsoc_bridge_pic_establish_irq(struct pic_softc *,
+					   struct intrsource *);
+static void mvsoc_bridge_pic_source_name(struct pic_softc *, int, char *,
+					 size_t);
+
+static const char * const sources[] = {
+    "CPUSelfInt",      "CPUTimer0IntReq", "CPUTimer1IntReq", "CPUWDTimerIntReq",
+    "AccessErr",       "Bit64Err",
+};
+
+static struct pic_ops mvsoc_bridge_picops = {
+	.pic_unblock_irqs = mvsoc_bridge_pic_unblock_irqs,
+	.pic_block_irqs = mvsoc_bridge_pic_block_irqs,
+	.pic_find_pending_irqs = mvsoc_bridge_pic_find_pending_irqs,
+	.pic_establish_irq = mvsoc_bridge_pic_establish_irq,
+	.pic_source_name = mvsoc_bridge_pic_source_name,
+};
+
+struct pic_softc mvsoc_bridge_pic = {
+	.pic_ops = &mvsoc_bridge_picops,
+	.pic_maxsources = MVSOC_MLMB_MLMBI_NIRQ,
+	.pic_name = "mvsoc_bridge",
+};
+
+
+void
+mvsoc_irq_handler(void *frame)
+{
+	struct cpu_info * const ci = curcpu();
+	const int oldipl = ci->ci_cpl;
+	const uint32_t oldipl_mask = __BIT(oldipl);
+	int ipl_mask = 0;
+
+	uvmexp.intrs++;
+
+	ipl_mask = find_pending_irqs();
+
+	/*
+	 * Record the pending_ipls and deliver them if we can.
+	 */
+	if ((ipl_mask & ~oldipl_mask) > oldipl_mask)
+		pic_do_pending_ints(I32_bit, oldipl, frame);
+}
+
+/*
+ * Mbus-L to Mbus bridge
+ */
+
+void *
+mvsoc_bridge_intr_establish(int ih, int ipl, int (*ih_func)(void *), void *arg)
+{
+
+	return intr_establish(mvsoc_bridge_pic.pic_irqbase + ih, ipl, 0,
+	    ih_func, arg);
+}
+
+/* ARGSUSED */
+static void
+mvsoc_bridge_pic_unblock_irqs(struct pic_softc *pic, size_t irqbase,
+			      uint32_t irq_mask)
+{
+
+	write_mlmbreg(MVSOC_MLMB_MLMBICR,
+	    read_mlmbreg(MVSOC_MLMB_MLMBICR) & ~irq_mask);
+	write_mlmbreg(MVSOC_MLMB_MLMBIMR,
+	    read_mlmbreg(MVSOC_MLMB_MLMBIMR) | irq_mask);
+}
+
+/* ARGSUSED */
+static void
+mvsoc_bridge_pic_block_irqs(struct pic_softc *pic, size_t irqbase,
+			    uint32_t irq_mask)
+{
+
+	write_mlmbreg(MVSOC_MLMB_MLMBIMR,
+	    read_mlmbreg(MVSOC_MLMB_MLMBIMR) & ~irq_mask);
+}
+
+static int
+mvsoc_bridge_pic_find_pending_irqs(struct pic_softc *pic)
+{
+	uint32_t pending;
+
+	pending =
+	    read_mlmbreg(MVSOC_MLMB_MLMBICR) & read_mlmbreg(MVSOC_MLMB_MLMBIMR);
+	if (pending == 0)
+		return 0;
+	pic_mark_pending_sources(pic, 0, pending);
+	return 1;
+}
+
+/* ARGSUSED */
+static void
+mvsoc_bridge_pic_establish_irq(struct pic_softc *pic, struct intrsource *is)
+{
+	/* Nothing */
+}
+
+static void
+mvsoc_bridge_pic_source_name(struct pic_softc *pic, int irq, char *buf,
+			     size_t len)
+{
+
+	strlcpy(buf, sources[irq], len);
+}
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/sys/arch/arm/marvell/mvsoc_intr.h	Sat Oct 09 03:31:35 2010 +0000
@@ -0,0 +1,49 @@
+/*	$NetBSD: mvsoc_intr.h,v 1.1.2.2 2010/10/09 03:31:40 yamt Exp $	*/
+/*
+ * Copyright (c) 2010 KIYOHARA Takashi
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _MVSOC_INTR_H_
+#define _MVSOC_INTR_H_
+
+#define ARM_IRQ_HANDLER	_C_LABEL(mvsoc_irq_handler)
+
+#ifndef _LOCORE
+int (*find_pending_irqs)(void);
+
+void mvsoc_irq_handler(void *);
+
+#include <arm/pic/picvar.h>
+
+static __inline void *
+marvell_intr_establish(int irq, int ipl, int (*func)(void *), void *arg)
+{
+
+	return intr_establish(irq, ipl, IST_LEVEL_HIGH, func, arg);
+}
+
+#endif	/* _LOCORE */
+
+#endif	/* _MVSOC_INTR_H_ */
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/sys/arch/arm/marvell/mvsoc_space.c	Sat Oct 09 03:31:35 2010 +0000
@@ -0,0 +1,320 @@
+/*	$NetBSD: mvsoc_space.c,v 1.1.2.2 2010/10/09 03:31:40 yamt Exp $	*/
+/*
+ * Copyright (c) 2007 KIYOHARA Takashi
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>
+__KERNEL_RCSID(0, "$NetBSD: mvsoc_space.c,v 1.1.2.2 2010/10/09 03:31:40 yamt Exp $");
+
+#include "opt_mvsoc.h"
+#include "mvpex.h"
+#include "gtpci.h"
+
+#include <sys/param.h>
+#include <sys/systm.h>
+
+#include <uvm/uvm_extern.h>
+
+#include <machine/bus.h>
+
+#include <arm/marvell/mvsocreg.h>
+#include <arm/marvell/mvsocvar.h>
+
+
+/* Proto types for all the bus_space structure functions */
+bs_protos(mvsoc);
+bs_protos(generic);
+bs_protos(generic_armv4);
+bs_protos(bs_notimpl);
+
+#define MVSOC_BUS_SPACE_DEFAULT_FUNCS		\
+	/* mapping/unmapping */			\
+	mvsoc_bs_map,				\
+	mvsoc_bs_unmap,				\
+	mvsoc_bs_subregion,			\
+						\
+	/* allocation/deallocation */		\
+	mvsoc_bs_alloc,				\
+	mvsoc_bs_free,				\
+						\
+	/* get kernel virtual address */	\
+	mvsoc_bs_vaddr,				\
+						\
+	/* mmap bus space for userland */	\
+	bs_notimpl_bs_mmap,			\
+						\
+	/* barrier */				\
+	mvsoc_bs_barrier,			\
+						\
+	/* read (single) */			\
+	generic_bs_r_1,				\
+	generic_armv4_bs_r_2,			\
+	generic_bs_r_4,				\
+	bs_notimpl_bs_r_8,			\
+						\
+	/* read multiple */			\
+	generic_bs_rm_1,			\
+	generic_armv4_bs_rm_2,			\
+	generic_bs_rm_4,			\
+	bs_notimpl_bs_rm_8,			\
+						\
+	/* read region */			\
+	generic_bs_rr_1,			\
+	generic_armv4_bs_rr_2,			\
+	generic_bs_rr_4,			\
+	bs_notimpl_bs_rr_8,			\
+						\
+	/* write (single) */			\
+	generic_bs_w_1,				\
+	generic_armv4_bs_w_2,			\
+	generic_bs_w_4,				\
+	bs_notimpl_bs_w_8,			\
+						\
+	/* write multiple */			\
+	generic_bs_wm_1,			\
+	generic_armv4_bs_wm_2,			\
+	generic_bs_wm_4,			\
+	bs_notimpl_bs_wm_8,			\
+						\
+	/* write region */			\
+	generic_bs_wr_1,			\
+	generic_armv4_bs_wr_2,			\
+	generic_bs_wr_4,			\
+	bs_notimpl_bs_wr_8,			\
+						\
+	/* set multiple */			\
+	bs_notimpl_bs_sm_1,			\
+	bs_notimpl_bs_sm_2,			\
+	bs_notimpl_bs_sm_4,			\
+	bs_notimpl_bs_sm_8,			\
+						\
+	/* set region */			\
+	bs_notimpl_bs_sr_1,			\
+	generic_armv4_bs_sr_2,			\
+	generic_bs_sr_4,			\
+	bs_notimpl_bs_sr_8,			\
+						\
+	/* copy */				\
+	bs_notimpl_bs_c_1,			\
+	generic_armv4_bs_c_2,			\
+	bs_notimpl_bs_c_4,			\
+	bs_notimpl_bs_c_8,
+
+
+struct bus_space mvsoc_bs_tag = {
+	/* cookie */
+	(void *)0,
+
+	MVSOC_BUS_SPACE_DEFAULT_FUNCS
+};
+
+#if NMVPEX > 0
+#if defined(ORION)
+struct bus_space orion_pex0_mem_bs_tag = {
+	/* cookie */
+	(void *)ORION_TAG_PEX0_MEM,
+
+	MVSOC_BUS_SPACE_DEFAULT_FUNCS
+};
+struct bus_space orion_pex0_io_bs_tag = {
+	/* cookie */
+	(void *)ORION_TAG_PEX0_IO,
+
+	MVSOC_BUS_SPACE_DEFAULT_FUNCS
+};
+struct bus_space orion_pex1_mem_bs_tag = {
+	/* cookie */
+	(void *)ORION_TAG_PEX1_MEM,
+
+	MVSOC_BUS_SPACE_DEFAULT_FUNCS
+};
+struct bus_space orion_pex1_io_bs_tag = {
+	/* cookie */
+	(void *)ORION_TAG_PEX1_IO,
+
+	MVSOC_BUS_SPACE_DEFAULT_FUNCS
+};
+#endif
+
+#if defined(KIRKWOOD)
+struct bus_space kirkwood_pex_mem_bs_tag = {
+	/* cookie */
+	(void *)KIRKWOOD_TAG_PEX_MEM,
+
+	MVSOC_BUS_SPACE_DEFAULT_FUNCS
+};
+struct bus_space kirkwood_pex_io_bs_tag = {
+	/* cookie */
+	(void *)KIRKWOOD_TAG_PEX_IO,
+
+	MVSOC_BUS_SPACE_DEFAULT_FUNCS
+};
+#endif
+#endif
+
+#if NGTPCI > 0
+#if defined(ORION)
+struct bus_space orion_pci_mem_bs_tag = {
+	/* cookie */
+	(void *)ORION_TAG_PCI_MEM,
+
+	MVSOC_BUS_SPACE_DEFAULT_FUNCS
+};
+struct bus_space orion_pci_io_bs_tag = {
+	/* cookie */
+	(void *)ORION_TAG_PCI_IO,
+
+	MVSOC_BUS_SPACE_DEFAULT_FUNCS
+};
+#endif
+#endif
+
+
+int
+mvsoc_bs_map(void *space, bus_addr_t address, bus_size_t size, int flags,
+	     bus_space_handle_t *handlep)
+{
+	const struct pmap_devmap *pd;
+	paddr_t startpa, endpa, offset, pa;
+	pt_entry_t *pte;
+	vaddr_t va;
+	int tag = (int)space;
+
+	if (tag != 0) {
+		bus_addr_t remap;
+		uint32_t base;
+		int window;
+
+		window = mvsoc_target(tag, NULL, NULL, &base, NULL);
+		if (window == -1)
+			return ENOMEM;
+		if (window < nremap) {
+			remap = read_mlmbreg(MVSOC_MLMB_WRLR(window)) &
+			    MVSOC_MLMB_WRLR_REMAP_MASK;
+			remap |=
+			    (read_mlmbreg(MVSOC_MLMB_WRHR(window)) << 16) << 16;
+			address = address - remap + base;
+		}
+	}
+
+	if ((pd = pmap_devmap_find_pa(address, size)) != NULL) {
+		/* Device was statically mapped. */
+		*handlep = pd->pd_va + (address - pd->pd_pa);
+		return 0;
+	}
+
+	startpa = trunc_page(address);
+	endpa = round_page(address + size);
+	offset = address & PAGE_MASK;
+
+	/* XXX use extent manager to check duplicate mapping */
+
+	va = uvm_km_alloc(kernel_map, endpa - startpa, 0,
+	    UVM_KMF_VAONLY | UVM_KMF_NOWAIT);
+	if (va == 0x00000000)
+		return ENOMEM;
+
+	*handlep = va + offset;
+
+	/* Now map the pages */
+	for (pa = startpa; pa < endpa; pa += PAGE_SIZE, va += PAGE_SIZE) {
+		pmap_kenter_pa(va, pa, VM_PROT_READ | VM_PROT_WRITE, 0);
+		if ((flags & BUS_SPACE_MAP_CACHEABLE) == 0) {
+			pte = vtopte(va);
+			*pte &= ~L2_S_CACHE_MASK;
+			PTE_SYNC(pte);
+			/*
+			 * XXX: pmap_kenter_pa() also does PTE_SYNC(). a bit of
+			 *      waste.
+			 */
+		}
+	}
+	pmap_update(pmap_kernel());
+
+	return 0;
+}
+
+void
+mvsoc_bs_unmap(void *space, bus_space_handle_t handle, bus_size_t size)
+{
+	vaddr_t va, sz;
+
+	if (pmap_devmap_find_va(handle, size) != NULL)
+		/* Device was statically mapped; nothing to do. */
+		return;
+
+	va = trunc_page(handle);
+        sz = round_page(handle + size) - va;
+
+	pmap_kremove(va, sz);
+	pmap_update(pmap_kernel());
+	uvm_km_free(kernel_map, va, sz, UVM_KMF_VAONLY);
+}
+
+/* ARGSUSED */
+int
+mvsoc_bs_subregion(void *space, bus_space_handle_t handle,
+		       bus_size_t offset, bus_size_t size,
+		       bus_space_handle_t *nhandlep)
+{
+
+	*nhandlep = handle + offset;
+	return 0;
+}
+
+/* ARGSUSED */
+int
+mvsoc_bs_alloc(void *space, bus_addr_t reg_start, bus_addr_t reg_end,
+	       bus_size_t size, bus_size_t alignment, bus_size_t boundary,
+	       int flags, bus_addr_t *addrp, bus_space_handle_t *handlep)
+{
+
+	panic("%s(): not implemented\n", __func__);
+}
+
+/* ARGSUSED */
+void
+mvsoc_bs_free(void *space, bus_space_handle_t handle, bus_size_t size)
+{
+
+	panic("%s(): not implemented\n", __func__);
+}
+
+/* ARGSUSED */
+void
+mvsoc_bs_barrier(void *space, bus_space_handle_t handle, bus_size_t offset,
+		 bus_size_t length, int flags)
+{
+
+	/* Nothing to do. */
+}
+
+/* ARGSUSED */
+void *
+mvsoc_bs_vaddr(void *space, bus_space_handle_t handle)
+{
+
+	return (void *)handle;
+}
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/sys/arch/arm/marvell/mvsocgpp.c	Sat Oct 09 03:31:35 2010 +0000
@@ -0,0 +1,455 @@
+/*	$NetBSD: mvsocgpp.c,v 1.1.2.2 2010/10/09 03:31:40 yamt Exp $	*/
+/*
+ * Copyright (c) 2008, 2010 KIYOHARA Takashi
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>
+__KERNEL_RCSID(0, "$NetBSD: mvsocgpp.c,v 1.1.2.2 2010/10/09 03:31:40 yamt Exp $");
+
+#include "gpio.h"
+
+#define _INTR_PRIVATE
+
+#include <sys/param.h>
+#include <sys/bus.h>
+#include <sys/device.h>
+#include <sys/errno.h>
+#include <sys/evcnt.h>
+#include <sys/gpio.h>
+#include <sys/kmem.h>
+
+#include <machine/intr.h>
+
+#include <arm/marvell/mvsocreg.h>
+#include <arm/marvell/mvsocvar.h>
+#include <arm/marvell/mvsocgppreg.h>
+#include <arm/marvell/mvsocgppvar.h>
+#include <arm/pic/picvar.h>
+
+#include <dev/marvell/marvellvar.h>
+
+#if NGPIO > 0
+#include <sys/gpio.h>
+#include <dev/gpio/gpiovar.h>
+#endif
+
+#define MVSOCGPP_DUMPREG
+
+#define MVSOCGPP_READ(sc, reg) \
+	bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg))
+#define MVSOCGPP_WRITE(sc, reg, val) \
+	bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
+
+struct mvsocgpp_softc {
+	device_t sc_dev;
+
+	bus_space_tag_t sc_iot;
+	bus_space_handle_t sc_ioh;
+
+	struct mvsocgpp_pic {
+		struct pic_softc gpio_pic;
+		int group;
+		uint32_t edge;
+		uint32_t level;
+	} *sc_pic;
+
+#if NGPIO > 0
+	struct gpio_chipset_tag sc_gpio_chipset;
+	gpio_pin_t *sc_pins;
+#endif
+};
+
+static int mvsocgpp_match(device_t, struct cfdata *, void *);
+static void mvsocgpp_attach(device_t, device_t, void *);
+
+#ifdef MVSOCGPP_DUMPREG
+static void mvsocgpp_dump_reg(struct mvsocgpp_softc *);
+#endif
+
+static void gpio_pic_unblock_irqs(struct pic_softc *, size_t, uint32_t);
+static void gpio_pic_block_irqs(struct pic_softc *, size_t, uint32_t);
+static int gpio_pic_find_pending_irqs(struct pic_softc *);
+static void gpio_pic_establish_irq(struct pic_softc *, struct intrsource *);
+
+static struct pic_ops gpio_pic_ops = {
+	.pic_unblock_irqs = gpio_pic_unblock_irqs,
+	.pic_block_irqs = gpio_pic_block_irqs,
+	.pic_find_pending_irqs = gpio_pic_find_pending_irqs,
+	.pic_establish_irq = gpio_pic_establish_irq,
+};
+
+static struct mvsocgpp_softc *mvsocgpp_softc;	/* One unit per One SoC */
+int gpp_irqbase = 0;
+int gpp_npins = 0;
+
+
+CFATTACH_DECL_NEW(mvsocgpp, sizeof(struct mvsocgpp_softc),
+    mvsocgpp_match, mvsocgpp_attach, NULL, NULL);
+
+
+/* ARGSUSED */
+static int
+mvsocgpp_match(device_t parent, struct cfdata *match, void *aux)
+{
+	struct marvell_attach_args *mva = aux;
+
+	if (strcmp(mva->mva_name, match->cf_name) != 0)
+		return 0;
+	if (mva->mva_offset == MVA_OFFSET_DEFAULT ||
+	    mva->mva_irq == MVA_IRQ_DEFAULT)
+		return 0;
+
+	mva->mva_size = MVSOC_GPP_SIZE;
+	return 1;
+}
+
+/* ARGSUSED */
+static void
+mvsocgpp_attach(device_t parent, device_t self, void *aux)
+{
+	struct mvsocgpp_softc *sc = device_private(self);
+	struct marvell_attach_args *mva = aux;
+	struct pic_softc *gpio_pic;
+#if NGPIO > 0
+	struct gpiobus_attach_args gba;
+	gpio_pin_t *pins;
+	uint32_t dir, valin, valout, polarity, mask;
+#endif
+	int i, j;
+	void *ih;
+
+	aprint_normal(": Marvell SoC General Purpose I/O Port Interface\n");
+	aprint_naive("\n");
+
+	sc->sc_dev = self;
+	sc->sc_iot = mva->mva_iot;
+	/* Map I/O registers for oriongpp */
+	if (bus_space_subregion(mva->mva_iot, mva->mva_ioh,
+				mva->mva_offset, mva->mva_size, &sc->sc_ioh)) {
+		aprint_error_dev(self, "can't map registers\n");
+		return;
+	}
+
+	if (gpp_npins > 0)
+		aprint_normal_dev(self, "%d gpio pins\n", gpp_npins);
+	else {
+		aprint_error_dev(self, "gpp_npins not initialized\n");
+		return;
+	}
+
+	mvsocgpp_softc = sc;
+
+	for (i = 0; i < gpp_npins; i += 32)
+		MVSOCGPP_WRITE(sc, MVSOCGPP_GPIOIC(i), 0);
+
+	sc->sc_pic =
+	    kmem_zalloc(sizeof(struct mvsocgpp_pic) * gpp_npins / 8, KM_SLEEP);
+	for (i = 0, j = 0; i < gpp_npins; i += 8, j++) {
+		gpio_pic = &(sc->sc_pic + j)->gpio_pic;
+		gpio_pic->pic_ops = &gpio_pic_ops;
+		snprintf(gpio_pic->pic_name, sizeof(gpio_pic->pic_name),
+		    "%s[%d:%d]", device_xname(self), i + 7, i);
+		gpio_pic->pic_maxsources =
+		    (gpp_npins - i) > 8 ? 8 : gpp_npins - i;
+		pic_add(gpio_pic, gpp_irqbase + i);
+		aprint_normal_dev(self, "interrupts %d..%d",
+		    gpp_irqbase + i, gpp_irqbase + i + 7);
+		ih = intr_establish(mva->mva_irq + j,
+		    IPL_HIGH, IST_LEVEL_HIGH, pic_handle_intr, gpio_pic);
+		aprint_normal(", intr %d\n", mva->mva_irq + j);
+
+		(sc->sc_pic + j)->group = j;
+	}
+
+#ifdef MVSOCGPP_DUMPREG
+	mvsocgpp_dump_reg(sc);
+#endif
+
+#if NGPIO > 0
+	sc->sc_pins = kmem_alloc(sizeof(gpio_pin_t) * gpp_npins, KM_SLEEP);
+
+	for (i = 0; i < gpp_npins; i += 32) {
+		dir = MVSOCGPP_READ(sc, MVSOCGPP_GPIODOEC(i));
+		valin = MVSOCGPP_READ(sc, MVSOCGPP_GPIODI(i));
+		valout = MVSOCGPP_READ(sc, MVSOCGPP_GPIODO(i));
+		polarity = MVSOCGPP_READ(sc, MVSOCGPP_GPIODIP(i));
+	}
+	for (i = 0, mask = 1; i < gpp_npins; i++, mask <<= 1) {
+		pins = &sc->sc_pins[i];
+		pins->pin_num = i;
+		pins->pin_caps =
+		    (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT | GPIO_PIN_INVIN);
+		if(dir & mask) {
+			pins->pin_flags = GPIO_PIN_INPUT;
+			pins->pin_state =
+			    (valin & mask) ? GPIO_PIN_HIGH : GPIO_PIN_LOW;
+		} else {
+			pins->pin_flags = GPIO_PIN_OUTPUT;
+			pins->pin_state =
+			    (valout & mask) ? GPIO_PIN_HIGH : GPIO_PIN_LOW;
+		}
+	}
+	sc->sc_gpio_chipset.gp_cookie = sc;
+	sc->sc_gpio_chipset.gp_pin_read = mvsocgpp_pin_read;
+	sc->sc_gpio_chipset.gp_pin_write = mvsocgpp_pin_write;
+	sc->sc_gpio_chipset.gp_pin_ctl = mvsocgpp_pin_ctl;
+	gba.gba_gc = &sc->sc_gpio_chipset;
+	gba.gba_pins = sc->sc_pins;
+	gba.gba_npins = gpp_npins;
+	config_found_ia(self, "gpiobus", &gba, gpiobus_print);
+#endif
+}
+
+/*
+ * arch/arm/pic functions.
+ */
+
+static void
+gpio_pic_unblock_irqs(struct pic_softc *pic, size_t irqbase, uint32_t irq_mask)
+{
+	struct mvsocgpp_softc *sc = mvsocgpp_softc;
+	struct mvsocgpp_pic *mvsocgpp_pic = (struct mvsocgpp_pic *)pic;
+	uint32_t mask;
+	int pin = mvsocgpp_pic->group << 3;
+
+	MVSOCGPP_WRITE(sc, MVSOCGPP_GPIOIC(pin),
+	    MVSOCGPP_READ(sc, MVSOCGPP_GPIOIC(pin)) & ~irq_mask);
+	if (irq_mask & mvsocgpp_pic->edge) {
+		mask = MVSOCGPP_READ(sc, MVSOCGPP_GPIOIM(pin));
+		mask |= (irq_mask & mvsocgpp_pic->edge);
+		MVSOCGPP_WRITE(sc, MVSOCGPP_GPIOIM(pin), mask);
+	}
+	if (irq_mask & mvsocgpp_pic->level) {
+		mask = MVSOCGPP_READ(sc, MVSOCGPP_GPIOILM(pin));
+		mask |= (irq_mask & mvsocgpp_pic->level);
+		MVSOCGPP_WRITE(sc, MVSOCGPP_GPIOILM(pin), mask);
+	}
+}
+
+/* ARGSUSED */
+static void
+gpio_pic_block_irqs(struct pic_softc *pic, size_t irqbase, uint32_t irq_mask)
+{
+	struct mvsocgpp_softc *sc = mvsocgpp_softc;
+	struct mvsocgpp_pic *mvsocgpp_pic = (struct mvsocgpp_pic *)pic;
+	int pin = mvsocgpp_pic->group << 3;
+
+	MVSOCGPP_WRITE(sc, MVSOCGPP_GPIOIM(pin),
+	    MVSOCGPP_READ(sc, MVSOCGPP_GPIOIM(pin)) & ~irq_mask);
+	MVSOCGPP_WRITE(sc, MVSOCGPP_GPIOILM(pin),
+	    MVSOCGPP_READ(sc, MVSOCGPP_GPIOILM(pin)) & ~irq_mask);
+}
+
+static int
+gpio_pic_find_pending_irqs(struct pic_softc *pic)
+{
+	struct mvsocgpp_softc *sc = mvsocgpp_softc;
+	struct mvsocgpp_pic *mvsocgpp_pic = (struct mvsocgpp_pic *)pic;
+	uint32_t pending;
+	int pin = mvsocgpp_pic->group << 3;
+
+	pending = MVSOCGPP_READ(sc, MVSOCGPP_GPIOIC(pin));
+	pending &= (0xff << mvsocgpp_pic->group);
+	pending &= (MVSOCGPP_READ(sc, MVSOCGPP_GPIOIM(pin)) |
+		    MVSOCGPP_READ(sc, MVSOCGPP_GPIOILM(pin)));
+	if (pending == 0)
+		return 0;
+	pic_mark_pending_sources(pic, 0, pending);
+	return 1;
+}
+
+static void
+gpio_pic_establish_irq(struct pic_softc *pic, struct intrsource *is)
+{
+	struct mvsocgpp_softc *sc = mvsocgpp_softc;
+	struct mvsocgpp_pic *mvsocgpp_pic = (struct mvsocgpp_pic *)pic;
+	uint32_t im, ilm, mask;
+	int type, pin;
+
+	type = is->is_type;
+	pin = pic->pic_irqbase + is->is_irq - gpp_irqbase;
+	mask = MVSOCGPP_GPIOPIN(pin);
+
+	switch (type) {
+	case IST_LEVEL_LOW:
+	case IST_EDGE_FALLING:
+		mvsocgpp_pin_ctl(NULL, pin, GPIO_PIN_INPUT | GPIO_PIN_INVIN);
+		break;
+
+	case IST_LEVEL_HIGH:
+	case IST_EDGE_RISING:
+		mvsocgpp_pin_ctl(NULL, pin, GPIO_PIN_INPUT);
+		break;
+
+	default:
+		panic("unknwon interrupt type %d for pin %d.\n", type, pin);
+	}
+
+	im = MVSOCGPP_READ(sc, MVSOCGPP_GPIOIM(pin));
+	ilm = MVSOCGPP_READ(sc, MVSOCGPP_GPIOILM(pin));
+	switch (type) {
+	case IST_EDGE_FALLING:
+	case IST_EDGE_RISING:
+		im |= mask;
+		ilm &= ~mask;
+		mvsocgpp_pic->edge |= mask;
+		mvsocgpp_pic->level &= ~mask;
+		break;
+
+	case IST_LEVEL_LOW:
+	case IST_LEVEL_HIGH:
+		im &= ~mask;
+		ilm |= mask;
+		mvsocgpp_pic->edge &= ~mask;
+		mvsocgpp_pic->level |= mask;
+		break;
+	}
+	MVSOCGPP_WRITE(sc, MVSOCGPP_GPIOIM(pin), im);
+	MVSOCGPP_WRITE(sc, MVSOCGPP_GPIOILM(pin), ilm);
+}
+
+
+/*
+ * gpio(4) functions, and can call you.
+ */
+
+/* ARGSUSED */
+int
+mvsocgpp_pin_read(void *arg, int pin)
+{
+	struct mvsocgpp_softc *sc = mvsocgpp_softc;
+	uint32_t val;
+
+	KASSERT(sc != NULL);
+
+	val = MVSOCGPP_READ(sc, MVSOCGPP_GPIODI(pin));
+	return (val & MVSOCGPP_GPIOPIN(pin)) != 0;
+}
+
+/* ARGSUSED */
+void
+mvsocgpp_pin_write(void *arg, int pin, int value)
+{
+	struct mvsocgpp_softc *sc = mvsocgpp_softc;
+	uint32_t old, new, mask = MVSOCGPP_GPIOPIN(pin);
+
+	KASSERT(sc != NULL);
+
+	old = MVSOCGPP_READ(sc, MVSOCGPP_GPIODO(pin));
+	if (value)
+		new = old | mask;
+	else
+		new = old & ~mask;
+	if (new != old)
+		MVSOCGPP_WRITE(sc, MVSOCGPP_GPIODO(pin), new);
+}
+
+/* ARGSUSED */
+void
+mvsocgpp_pin_ctl(void *arg, int pin, int flags)
+{
+	struct mvsocgpp_softc *sc = mvsocgpp_softc;
+	uint32_t old, new, mask = MVSOCGPP_GPIOPIN(pin);
+
+	KASSERT(sc != NULL);
+
+	old = MVSOCGPP_READ(sc, MVSOCGPP_GPIODOEC(pin));
+	switch (flags & (GPIO_PIN_INPUT|GPIO_PIN_OUTPUT)) {
+	case GPIO_PIN_INPUT:
+		new = old | mask;
+		break;
+
+	case GPIO_PIN_OUTPUT:
+		new = old & ~mask;
+		break;
+
+	default:
+		return;
+	}
+	if (new != old)
+		MVSOCGPP_WRITE(sc, MVSOCGPP_GPIODOEC(pin), new);
+
+	/* Blink every 2^24 TCLK */
+	old = MVSOCGPP_READ(sc, MVSOCGPP_GPIOBE(pin));
+	if (flags & GPIO_PIN_PULSATE)
+		new = old | mask;
+	else
+		new = old & ~mask;
+	if (new != old)
+		MVSOCGPP_WRITE(sc, MVSOCGPP_GPIOBE(pin), new);
+
+	old = MVSOCGPP_READ(sc, MVSOCGPP_GPIODIP(pin));
+	if (flags & GPIO_PIN_INVIN)
+		new = old | mask;
+	else
+		new = old & ~mask;
+	if (new != old)
+		MVSOCGPP_WRITE(sc, MVSOCGPP_GPIODIP(pin), new);
+}
+
+
+#ifdef MVSOCGPP_DUMPREG
+static void
+mvsocgpp_dump_reg(struct mvsocgpp_softc *sc)
+{
+
+	aprint_normal_dev(sc->sc_dev, "  Data Out:                 \t0x%08x\n",
+	    MVSOCGPP_READ(sc, MVSOCGPP_GPIODO(0)));
+	aprint_normal_dev(sc->sc_dev, "  Data Out Enable Control:  \t0x%08x\n",
+	    MVSOCGPP_READ(sc, MVSOCGPP_GPIODOEC(0)));
+	aprint_normal_dev(sc->sc_dev, "  Data Blink Enable:        \t0x%08x\n",
+	    MVSOCGPP_READ(sc, MVSOCGPP_GPIOBE(0)));
+	aprint_normal_dev(sc->sc_dev, "  Data In Polarity:         \t0x%08x\n",
+	    MVSOCGPP_READ(sc, MVSOCGPP_GPIODIP(0)));
+	aprint_normal_dev(sc->sc_dev, "  Data In:                  \t0x%08x\n",
+	    MVSOCGPP_READ(sc, MVSOCGPP_GPIODI(0)));
+	aprint_normal_dev(sc->sc_dev, "  Interrupt Cause:          \t0x%08x\n",
+	    MVSOCGPP_READ(sc, MVSOCGPP_GPIOIC(0)));
+	aprint_normal_dev(sc->sc_dev, "  Interrupt Mask:           \t0x%08x\n",
+	    MVSOCGPP_READ(sc, MVSOCGPP_GPIOIM(0)));
+	aprint_normal_dev(sc->sc_dev, "  Interrupt Level Mask:     \t0x%08x\n",
+	    MVSOCGPP_READ(sc, MVSOCGPP_GPIOILM(0)));
+
+	if (gpp_npins <= 32)
+		return;
+
+	aprint_normal_dev(sc->sc_dev, "  High Data Out:            \t0x%08x\n",
+	    MVSOCGPP_READ(sc, MVSOCGPP_GPIODO(32)));
+	aprint_normal_dev(sc->sc_dev, "  High Data Out Enable Ctrl:\t0x%08x\n",
+	    MVSOCGPP_READ(sc, MVSOCGPP_GPIODOEC(32)));
+	aprint_normal_dev(sc->sc_dev, "  High Blink Enable:        \t0x%08x\n",
+	    MVSOCGPP_READ(sc, MVSOCGPP_GPIOBE(32)));
+	aprint_normal_dev(sc->sc_dev, "  High Data In Polarity:    \t0x%08x\n",
+	    MVSOCGPP_READ(sc, MVSOCGPP_GPIODIP(32)));
+	aprint_normal_dev(sc->sc_dev, "  High Data In:             \t0x%08x\n",
+	    MVSOCGPP_READ(sc, MVSOCGPP_GPIODI(32)));
+	aprint_normal_dev(sc->sc_dev, "  High Interrupt Cause:     \t0x%08x\n",
+	    MVSOCGPP_READ(sc, MVSOCGPP_GPIOIC(32)));
+	aprint_normal_dev(sc->sc_dev, "  High Interrupt Mask:      \t0x%08x\n",
+	    MVSOCGPP_READ(sc, MVSOCGPP_GPIOIM(32)));
+	aprint_normal_dev(sc->sc_dev, "  High Interrupt Level Mask:\t0x%08x\n",
+	    MVSOCGPP_READ(sc, MVSOCGPP_GPIOILM(32)));
+}
+#endif
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/sys/arch/arm/marvell/mvsocgppreg.h	Sat Oct 09 03:31:35 2010 +0000
@@ -0,0 +1,67 @@
+/*	$NetBSD: mvsocgppreg.h,v 1.1.2.2 2010/10/09 03:31:40 yamt Exp $	*/
+/*
+ * Copyright (c) 2008 KIYOHARA Takashi
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _MVSOCGPPREG_H_
+#define _MVSOCGPPREG_H_
+
+#define MVSOC_GPP_SIZE		0x100
+
+/*
+ * General Purpose Port Registers
+ */
+/* GPIO Register Map */
+					/* GPIO Data Out */
+#define MVSOCGPP_GPIODO(p)	((((p) & 0x20) << 1) + 0x00)
+					/* GPIO Data Out Enable Control */
+#define MVSOCGPP_GPIODOEC(p)	((((p) & 0x20) << 1) + 0x04)
+					/* GPIO Blink Enable Control */
+#define MVSOCGPP_GPIOBE(p)	((((p) & 0x20) << 1) + 0x08)
+					/* GPIO Data In Polarity */
+#define MVSOCGPP_GPIODIP(p)	((((p) & 0x20) << 1) + 0x0c)
+					/* GPIO Data In */
+#define MVSOCGPP_GPIODI(p)	((((p) & 0x20) << 1) + 0x10)
+					/* GPIO Interrupt Cause */
+#define MVSOCGPP_GPIOIC(p)	((((p) & 0x20) << 1) + 0x14)
+					/* GPIO Interrupt Mask */
+#define MVSOCGPP_GPIOIM(p)	((((p) & 0x20) << 1) + 0x18)
+					/* GPIO Interrupt Level Mask */
+#define MVSOCGPP_GPIOILM(p)	((((p) & 0x20) << 1) + 0x1c)
+
+#define MVSOCGPP_GPIOPIN(pin)		(1 << ((pin) & 0x1f))
+
+/* Out Enable */
+#define MVSOCGPP_GPIODOE_OUT		0
+#define MVSOCGPP_GPIODOE_IN		1
+
+/* Polarity */
+#define MVSOCGPP_GPIODIP_INVERT		1
+
+/* Interrupt Mask */
+#define MVSOCGPP_GPIOIM_EDGE		0
+#define MVSOCGPP_GPIOIM_LEVEL		1
+
+#endif	/* _ORIONPCIREG_H_ */
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/sys/arch/arm/marvell/mvsocgppvar.h	Sat Oct 09 03:31:35 2010 +0000
@@ -0,0 +1,45 @@
+/*	$NetBSD: mvsocgppvar.h,v 1.1.2.2 2010/10/09 03:31:40 yamt Exp $	*/
+/*
+ * Copyright (c) 2008, 2008 KIYOHARA Takashi
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _MVSOCGPPVAR_H_
+#define _MVSOCGPPVAR_H_
+
+
+static __inline void *
+mvsocgpp_intr_establish(int pin, int ipl, int type,
+			int (*func)(void *), void *arg)
+{
+
+	return intr_establish(gpp_irqbase + pin, ipl, type, func, arg);
+}
+#define mvsocgpp_intr_disestablish(ih)	intr_disestablish(ih)
+
+int mvsocgpp_pin_read(void *, int);
+void mvsocgpp_pin_write(void *, int, int);
+void mvsocgpp_pin_ctl(void *, int, int);
+
+#endif	/* _MVSOCGPPVAR_H_ */
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/sys/arch/arm/marvell/mvsocreg.h	Sat Oct 09 03:31:35 2010 +0000
@@ -0,0 +1,134 @@
+/*	$NetBSD: mvsocreg.h,v 1.1.2.2 2010/10/09 03:31:40 yamt Exp $	*/
+/*
+ * Copyright (c) 2007, 2008 KIYOHARA Takashi
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _MVSOCREG_H_
+#define _MVSOCREG_H_
+
+#define MVSOC_UNITID_MASK		0xf
+#define MVSOC_UNITID_DDR		0x0	/* DDR registers */
+#define MVSOC_UNITID_DEVBUS		0x1	/* Device Bus registers */
+#define MVSOC_UNITID_MLMB		0x2	/* Mbus-L to Mbus Bridge reg */
+#define MVSOC_UNITID_PEX		0x4	/* PCI Express Interface reg */
+
+
+/*
+ * Physical address of integrated peripherals
+ */
+
+#define UNITID2PHYS(uid)	((MVSOC_UNITID_ ## uid) << 16)
+
+/*
+ * DDR SDRAM Controller Registers
+ */
+#define MVSOC_DDR_BASE		(UNITID2PHYS(DDR))	/* 0x00000 */
+
+/* DDR SDRAM Contriller Address Decode Registers */
+#define MVSOC_DSC_BASE			0x01500	/* DDR SDRAM Ctrl Addr Reg */
+#define MVSOC_DSC_NCS			4
+#define MVSOC_DSC_CSBAR(x)		((x) * 8)
+#define MVSOC_DSC_CSBAR_BASE_MASK	0xff000000
+#define MVSOC_DSC_CSSR(x)		((x) * 8 + 4)
+#define MVSOC_DSC_CSSR_WINEN		0x00000001
+#define MVSOC_DSC_CSSR_SIZE_MASK	0xff000000
+
+
+/*
+ * Device Bus
+ */
+#define MVSOC_DEVBUS_BASE	(UNITID2PHYS(DEVBUS))	/* 0x10000 */
+
+/*
+ * General Purpose Port Registers
+ */
+#define MVSOC_GPP_BASE			(MVSOC_DEVBUS_BASE + 0x0100)
+
+/*
+ * Two-Wire Serial Interface Registers
+ */
+#define MVSOC_TWSI_BASE			(MVSOC_DEVBUS_BASE + 0x1000)
+
+/*
+ * UART Interface Registers
+ */
+					/* NS16550 compatible */
+#define MVSOC_COM0_BASE			(MVSOC_DEVBUS_BASE + 0x2000)
+#define MVSOC_COM1_BASE			(MVSOC_DEVBUS_BASE + 0x2100)
+
+/*
+ * Mbus-L to Mbus Bridge Registers
+ */
+#define MVSOC_MLMB_BASE		(UNITID2PHYS(MLMB))	/* 0x20000 */
+
+/* CPU Address Map Registers */
+#define MVSOC_MLMB_WCR(w)		  (((w) << 4) + 0x0)
+#define MVSOC_MLMB_WCR_WINEN			(1 << 0)
+#define MVSOC_MLMB_WCR_TARGET(t)		(((t) & 0xf) << 4)
+#define MVSOC_MLMB_WCR_ATTR(a)			(((a) & 0xff) << 8)
+#define MVSOC_MLMB_WCR_SIZE_MASK		0xffff0000
+#define MVSOC_MLMB_WCR_SIZE(s)		  (((s) - 1) & MVSOC_MLMB_WCR_SIZE_MASK)
+#define MVSOC_MLMB_WBR(w)		  (((w) << 4) + 0x4)
+#define MVSOC_MLMB_WBR_BASE_MASK		0xffff0000
+#define MVSOC_MLMB_WRLR(w)		  (((w) << 4) + 0x8)
+#define MVSOC_MLMB_WRLR_REMAP_MASK		0xffff0000
+#define MVSOC_MLMB_WRHR(w)		  (((w) << 4) + 0xc)
+#define MVSOC_MLMB_IRBAR		  0x080 /* Internal regs Base Address */
+#define MVSOC_MLMB_IRBAR_BASE_MASK	0xfff00000
+
+/* CPU Control and Status Registers */
+#define MVSOC_MLMB_CPUCR		  0x100	/* CPU Configuration Register */
+#define MVSOC_MLMB_CPUCSR		  0x104	/* CPU Control/Status Register*/
+#define MVSOC_MLMB_RSTOUTNMASKR		  0x108 /* RSTOUTn Mask Register */
+#define MVSOC_MLMB_SSRR			  0x10c	/* System Soft Reset Register */
+#define MVSOC_MLMB_MLMBICR		  0x110	/*Mb-L to Mb Bridge Intr Cause*/
+#define MVSOC_MLMB_MLMBIMR		  0x114	/*Mb-L to Mb Bridge Intr Mask */
+
+#define MVSOC_MLMB_L2CFG		  0x128	/* L2 Cache Config */
+
+#define MVSOC_TMR_BASE			(MVSOC_MLMB_BASE + 0x0300)
+
+/* CPU Doorbell Registers */
+#define MVSOC_MLMB_H2CDR		  0x400	/* Host-to-CPU Doorbell */
+#define MVSOC_MLMB_H2CDMR		  0x404	/* Host-to-CPU Doorbell Mask */
+#define MVSOC_MLMB_C2HDR		  0x408	/* CPU-to-Host Doorbell */
+#define MVSOC_MLMB_C2HDMR		  0x40c	/* CPU-to-Host Doorbell Mask */
+
+/* Local to System Bridge Interrupt {Cause,Mask} Register bits */
+#define MVSOC_MLMB_MLMBI_CPUSELFINT		0
+#define MVSOC_MLMB_MLMBI_CPUTIMER0INTREQ	1
+#define MVSOC_MLMB_MLMBI_CPUTIMER1INTREQ	2
+#define MVSOC_MLMB_MLMBI_CPUWDTIMERINTREQ	3
+#define MVSOC_MLMB_MLMBI_ACCESSERR		4
+#define MVSOC_MLMB_MLMBI_BIT64ERR		5
+
+#define MVSOC_MLMB_MLMBI_NIRQ			6
+
+/*
+ * PCI-Express Interface Registers
+ */
+#define MVSOC_PEX_BASE		(UNITID2PHYS(PEX))	/* 0x40000 */
+
+#endif	/* _MVSOCREG_H_ */
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/sys/arch/arm/marvell/mvsoctmr.c	Sat Oct 09 03:31:35 2010 +0000
@@ -0,0 +1,305 @@
+/*	$NetBSD: mvsoctmr.c,v 1.1.2.2 2010/10/09 03:31:40 yamt Exp $	*/
+/*
+ * Copyright (c) 2007, 2008 KIYOHARA Takashi
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+#include <sys/cdefs.h>
+__KERNEL_RCSID(0, "$NetBSD: mvsoctmr.c,v 1.1.2.2 2010/10/09 03:31:40 yamt Exp $");
+
+#include <sys/param.h>
+#include <sys/atomic.h>
+#include <sys/bus.h>
+#include <sys/device.h>
+#include <sys/errno.h>
+#include <sys/kernel.h>
+#include <sys/time.h>
+#include <sys/timetc.h>
+#include <sys/systm.h>
+
+#include <machine/intr.h>
+
+#include <arm/cpufunc.h>
+
+#include <arm/marvell/mvsocreg.h>
+#include <arm/marvell/mvsocvar.h>
+#include <arm/marvell/mvsoctmrreg.h>
+
+#include <dev/marvell/marvellvar.h>
+
+
+struct mvsoctmr_softc {
+	device_t sc_dev;
+
+	bus_space_tag_t sc_iot;
+	bus_space_handle_t sc_ioh;
+};
+
+
+static int mvsoctmr_match(device_t, struct cfdata *, void *);
+static void mvsoctmr_attach(device_t, device_t, void *);
+
+static int clockhandler(void *);
+static int statclockhandler(void *);
+
+static u_int mvsoctmr_get_timecount(struct timecounter *);
+
+static void mvsoctmr_cntl(struct mvsoctmr_softc *, int, u_int, int, int);
+
+#ifndef STATHZ
+#define STATHZ	64
+#endif
+
+static struct mvsoctmr_softc *mvsoctmr_sc;
+static uint32_t clock_ticks, statclock_ticks;
+static struct timecounter mvsoctmr_timecounter = {
+	mvsoctmr_get_timecount,	/* get_timecount */
+	0,			/* no poll_pps */
+	~0u,			/* counter_mask */
+	0,			/* frequency  (set by cpu_initclocks()) */
+	"mvsoctmr",		/* name */
+	100,			/* quality */
+	NULL,			/* prev */
+	NULL,			/* next */
+};
+static volatile uint32_t mvsoctmr_base;
+
+CFATTACH_DECL_NEW(mvsoctmr, sizeof(struct mvsoctmr_softc),
+    mvsoctmr_match, mvsoctmr_attach, NULL, NULL);
+
+
+/* ARGSUSED */
+static int
+mvsoctmr_match(device_t parent, struct cfdata *match, void *aux)
+{
+	struct marvell_attach_args *mva = aux;
+
+	if (strcmp(mva->mva_name, match->cf_name) != 0)
+		return 0;
+	if (mva->mva_offset == MVA_OFFSET_DEFAULT)
+		return 0;
+
+	mva->mva_size = MVSOCTMR_SIZE;
+	return 1;
+}
+
+/* ARGSUSED */
+static void
+mvsoctmr_attach(device_t parent, device_t self, void *aux)
+{
+        struct mvsoctmr_softc *sc = device_private(self);
+	struct marvell_attach_args *mva = aux;
+
+	aprint_naive("\n");
+	aprint_normal(": Marvell SoC Timer\n");
+
+	if (mvsoctmr_sc == NULL)
+		mvsoctmr_sc = sc;
+
+	sc->sc_dev = self;
+	sc->sc_iot = mva->mva_iot;
+	if (bus_space_subregion(mva->mva_iot, mva->mva_ioh,
+	    mva->mva_offset, mva->mva_size, &sc->sc_ioh))
+		panic("%s: Cannot map registers", device_xname(self));
+}
+
+/*
+ * clockhandler:
+ *
+ *	Handle the hardclock interrupt.
+ */
+static int
+clockhandler(void *arg)
+{
+	struct clockframe *frame = arg;
+
+	atomic_add_32(&mvsoctmr_base, clock_ticks);
+
+	hardclock(frame);
+
+	return 1;
+}
+
+/*
+ * statclockhandler:
+ *
+ *	Handle the statclock interrupt.
+ */
+static int
+statclockhandler(void *arg)
+{
+	struct clockframe *frame = arg;
+
+	statclock(frame);
+
+	return 1;
+}
+
+
+/*
+ * setstatclockrate:
+ *
+ *	Set the rate of the statistics clock.
+ *
+ *	We assume that hz is either stathz or profhz, and that neither
+ *	will change after being set by cpu_initclocks().  We could
+ *	recalculate the intervals here, but that would be a pain.
+ */
+/* ARGSUSED */
+void
+setstatclockrate(int newhz)
+{
+	struct mvsoctmr_softc *sc = mvsoctmr_sc;
+	const int en = 1, autoen = 1;
+
+	statclock_ticks = mvTclk / newhz;
+
+	mvsoctmr_cntl(sc, MVSOCTMR_TIMER1, statclock_ticks, en, autoen);
+}
+
+/*
+ * cpu_initclocks:
+ *
+ *	Initialize the clock and get them going.
+ */
+void
+cpu_initclocks()
+{
+	struct mvsoctmr_softc *sc;
+	void *clock_ih;
+	const int en = 1, autoen = 1;
+
+	sc = mvsoctmr_sc;
+	if (sc == NULL)
+		panic("cpu_initclocks: mvsoctmr not found");
+
+	stathz = profhz = STATHZ;
+	mvsoctmr_timecounter.tc_frequency = mvTclk;
+	clock_ticks = mvTclk / hz;
+
+	mvsoctmr_cntl(sc, MVSOCTMR_TIMER0, clock_ticks, en, autoen);
+
+	clock_ih = mvsoc_bridge_intr_establish(MVSOC_MLMB_MLMBI_CPUTIMER0INTREQ,
+	    IPL_CLOCK, clockhandler, NULL);
+	if (clock_ih == NULL)
+		panic("cpu_initclocks: unable to register timer interrupt");
+
+	if (stathz) {
+		setstatclockrate(stathz);
+		clock_ih = mvsoc_bridge_intr_establish(
+		    MVSOC_MLMB_MLMBI_CPUTIMER1INTREQ, IPL_HIGH,
+		    statclockhandler, NULL);
+		if (clock_ih == NULL)
+			panic("cpu_initclocks:"
+			    " unable to register statclock timer interrupt");
+	}
+
+	tc_init(&mvsoctmr_timecounter);
+}
+
+void
+delay(unsigned int n)
+{
+	struct mvsoctmr_softc *sc;
+	unsigned int cur_tick, initial_tick;
+	int remaining;
+
+	sc = mvsoctmr_sc;
+#ifdef DEBUG
+	if (sc == NULL) {
+		printf("%s: called before start mvsoctmr\n", __func__);
+		return;
+	}
+#endif
+
+	/*
+	 * Read the counter first, so that the rest of the setup overhead is
+	 * counted.
+	 */
+	initial_tick = bus_space_read_4(sc->sc_iot, sc->sc_ioh,
+	    MVSOCTMR_TIMER(MVSOCTMR_TIMER0));
+
+	if (n <= UINT_MAX / mvTclk) {
+		/*
+		 * For unsigned arithmetic, division can be replaced with
+		 * multiplication with the inverse and a shift.
+		 */
+		remaining = n * mvTclk / 1000000;
+	} else {
+		/*
+		 * This is a very long delay.
+		 * Being slow here doesn't matter.
+		 */
+		remaining = (unsigned long long) n * mvTclk / 1000000;
+	}
+
+	while (remaining > 0) {
+		cur_tick = bus_space_read_4(sc->sc_iot, sc->sc_ioh,
+		    MVSOCTMR_TIMER(MVSOCTMR_TIMER0));
+		if (cur_tick > initial_tick)
+			remaining -= clock_ticks - cur_tick + initial_tick;
+		else
+			remaining -= (initial_tick - cur_tick);
+		initial_tick = cur_tick;
+	}
+}
+
+static u_int
+mvsoctmr_get_timecount(struct timecounter *tc)
+{
+	struct mvsoctmr_softc *sc = mvsoctmr_sc;
+	uint32_t counter, base;
+	u_int intrstat;
+
+	intrstat = disable_interrupts(I32_bit);
+	base = mvsoctmr_base;
+	counter = bus_space_read_4(sc->sc_iot, sc->sc_ioh,
+	    MVSOCTMR_TIMER(MVSOCTMR_TIMER0));
+	restore_interrupts(intrstat);
+
+	return base - counter;
+}
+
+
+static void
+mvsoctmr_cntl(struct mvsoctmr_softc *sc, int num, u_int ticks, int en,
+	      int autoen)
+{
+	uint32_t ctrl;
+
+	bus_space_write_4(sc->sc_iot, sc->sc_ioh, MVSOCTMR_RELOAD(num),
+	    ticks);
+
+	bus_space_write_4(sc->sc_iot, sc->sc_ioh, MVSOCTMR_TIMER(num), ticks);
+
+	ctrl = bus_space_read_4(sc->sc_iot, sc->sc_ioh, MVSOCTMR_CTCR);
+	if (en)
+		ctrl |= MVSOCTMR_CTCR_CPUTIMEREN(num);
+	else
+		ctrl &= ~MVSOCTMR_CTCR_CPUTIMEREN(num);
+	if (autoen)
+		ctrl |= MVSOCTMR_CTCR_CPUTIMERAUTO(num);
+	else
+		ctrl &= ~MVSOCTMR_CTCR_CPUTIMERAUTO(num);
+	bus_space_write_4(sc->sc_iot, sc->sc_ioh, MVSOCTMR_CTCR, ctrl);
+}
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/sys/arch/arm/marvell/mvsoctmrreg.h	Sat Oct 09 03:31:35 2010 +0000
@@ -0,0 +1,45 @@
+/*	$NetBSD: mvsoctmrreg.h,v 1.1.2.2 2010/10/09 03:31:40 yamt Exp $	*/
+/*
+ * Copyright (c) 2007 KIYOHARA Takashi
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef _MVSOCTMRREG_H_
+#define _MVSOCTMRREG_H_
+
+#define MVSOCTMR_SIZE		0x100
+
+#define MVSOCTMR_CTCR		0x00		/* CPU Timers Control */
+#define MVSOCTMR_RELOAD(n)	(0x10 + (n) * 8)/* CPU Timer(n) Reload */
+#define MVSOCTMR_TIMER(n)	(0x14 + (n) * 8)/* CPU Timer(n) */
+
+#define MVSOCTMR_TIMER0		0
+#define MVSOCTMR_TIMER1		1
+#define MVSOCTMR_WATCHDOG	2
+
+
+/* CPU Timers Control Register (MVSOCTMR_CTCR) */
+#define MVSOCTMR_CTCR_CPUTIMEREN(n)	(1 << (n * 2))
+#define MVSOCTMR_CTCR_CPUTIMERAUTO(n)	(1 << (n * 2 + 1))
+
+#endif	/* !_MVSOCTMRREG_H_ */
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/sys/arch/arm/marvell/mvsocvar.h	Sat Oct 09 03:31:35 2010 +0000
@@ -0,0 +1,92 @@
+/*	$NetBSD: mvsocvar.h,v 1.1.2.2 2010/10/09 03:31:40 yamt Exp $	*/
+/*
+ * Copyright (c) 2007, 2010 KIYOHARA Takashi
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _MVSOCVAR_H_
+#define _MVSOCVAR_H_
+
+#include <machine/bus.h>
+
+struct mvsoc_softc {
+        device_t sc_dev;
+
+	bus_addr_t sc_addr;
+	bus_space_tag_t sc_iot;
+	bus_space_handle_t sc_ioh;
+	bus_dma_tag_t sc_dmat;
+};
+
+typedef int (*mvsoc_irq_handler_t)(void *);
+
+extern uint32_t mvPclk, mvSysclk, mvTclk;
+extern vaddr_t mlmb_base;
+extern int nwindow, nremap;
+extern int gpp_npins, gpp_irqbase;
+extern struct bus_space mvsoc_bs_tag;
+extern struct arm32_bus_dma_tag mvsoc_bus_dma_tag;
+
+#define read_mlmbreg(o)		(*(volatile uint32_t *)(mlmb_base + (o)))
+#define write_mlmbreg(o, v)	(*(volatile uint32_t *)(mlmb_base + (o)) = (v))
+
+void mvsoc_bootstrap(bus_addr_t);
+uint16_t mvsoc_model(void);
+uint8_t mvsoc_rev(void);
+void * mvsoc_bridge_intr_establish(int, int, int (*)(void *), void *);
+
+#include <dev/marvell/marvellvar.h>
+
+enum mvsoc_tags {
+	MVSOC_TAG_INTERNALREG  = MARVELL_TAG_MAX,
+
+	ORION_TAG_PEX0_MEM,
+	ORION_TAG_PEX0_IO,
+	ORION_TAG_PEX1_MEM,
+	ORION_TAG_PEX1_IO,
+	ORION_TAG_PCI_MEM,
+	ORION_TAG_PCI_IO,
+	ORION_TAG_DEVICE_CS0,
+	ORION_TAG_DEVICE_CS1,
+	ORION_TAG_DEVICE_CS2,
+	ORION_TAG_FLASH_CS,
+	ORION_TAG_DEVICE_BOOTCS,
+	ORION_TAG_CRYPT,
+
+	KIRKWOOD_TAG_PEX_MEM,
+	KIRKWOOD_TAG_PEX_IO,
+	KIRKWOOD_TAG_NAND,
+	KIRKWOOD_TAG_SPI,
+	KIRKWOOD_TAG_BOOTROM,
+	KIRKWOOD_TAG_CRYPT,
+};
+int mvsoc_target(int, uint32_t *, uint32_t *, uint32_t *, uint32_t *);
+
+void orion_getclks(bus_addr_t);
+void orion_intr_bootstrap(void);
+
+void kirkwood_getclks(bus_addr_t);
+void kirkwood_intr_bootstrap(void);
+
+#endif	/* _MVSOCVAR_H_ */
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/sys/arch/arm/marvell/orion.c	Sat Oct 09 03:31:35 2010 +0000
@@ -0,0 +1,257 @@
+/*	$NetBSD: orion.c,v 1.1.2.2 2010/10/09 03:31:40 yamt Exp $	*/
+/*
+ * Copyright (c) 2010 KIYOHARA Takashi
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>
+__KERNEL_RCSID(0, "$NetBSD: orion.c,v 1.1.2.2 2010/10/09 03:31:40 yamt Exp $");
+
+#define _INTR_PRIVATE
+
+#include "mvsocgpp.h"
+
+#include <sys/param.h>
+#include <sys/bus.h>
+
+#include <machine/intr.h>
+
+#include <arm/pic/picvar.h>
+#include <arm/pic/picvar.h>
+
+#include <arm/marvell/mvsocreg.h>
+#include <arm/marvell/mvsocvar.h>
+#include <arm/marvell/orionreg.h>
+
+#include <dev/marvell/marvellreg.h>
+
+
+static void orion_intr_init(void);
+
+static void orion_pic_unblock_irqs(struct pic_softc *, size_t, uint32_t);
+static void orion_pic_block_irqs(struct pic_softc *, size_t, uint32_t);
+static void orion_pic_establish_irq(struct pic_softc *, struct intrsource *);
+static void orion_pic_source_name(struct pic_softc *, int, char *, size_t);
+
+static int orion_find_pending_irqs(void);
+
+static const char * const sources[64] = {
+    "Bridge(0)",       "Host2CPU DB(1)",  "CPU2Host DB(2)",  "UART0(3)",
+    "UART1(4)",        "TWSI(5)",         "GPIO7_0(6)",      "GPIO15_8(7)",
+    "GPIO23_16(8)",    "GPIO31_24(9)",    "PEX0Err(10)",     "PEX0INT(11)",
+    "PEX1Err/USBCnt1", "PEX1INT(13)",     "DEVErr(14)",      "PCIErr(15)",
+    "USBBr(16)",       "USBCnt0(17)",     "GbERx(18)",       "GbETx(19)",
+    "GbEMisc(20)",     "GbESum(21)",      "GbEErr(22)",      "DMAErr(23)",
+    "IDMA0(24)",       "IDMA1(25)",       "IDMA2(26)",       "IDMA3(27)",
+    "SecIntr(28)",     "SataIntr(29)",    "XOR0(30)",        "XOR1(31)"
+};
+
+static struct pic_ops orion_picops = {
+	.pic_unblock_irqs = orion_pic_unblock_irqs,
+	.pic_block_irqs = orion_pic_block_irqs,
+	.pic_establish_irq = orion_pic_establish_irq,
+	.pic_source_name = orion_pic_source_name,
+};
+static struct pic_softc orion_pic = {
+	.pic_ops = &orion_picops,
+	.pic_maxsources = 32,
+	.pic_name = "orion_pic",
+};
+
+
+/*
+ * orion_intr_bootstrap:
+ *
+ *	Initialize the rest of the interrupt subsystem, making it
+ *	ready to handle interrupts from devices.
+ */
+void
+orion_intr_bootstrap()
+{
+	extern void (*mvsoc_intr_init)(void);
+
+	/* disable all interrupts */
+	write_mlmbreg(ORION_MLMB_MIRQIMR, 0);
+
+	/* disable all bridge interrupts */
+	write_mlmbreg(MVSOC_MLMB_MLMBIMR, 0);
+
+	mvsoc_intr_init = orion_intr_init;
+
+#if NMVSOCGPP > 0
+	gpp_npins = 32;
+	gpp_irqbase = 64;	/* Main(32) + Bridge(32) */
+#endif
+}
+
+static void
+orion_intr_init(void)
+{
+	extern struct pic_softc mvsoc_bridge_pic;
+	void *ih;
+
+	pic_add(&orion_pic, 0);
+
+	pic_add(&mvsoc_bridge_pic, 32);
+	ih = intr_establish(ORION_IRQ_BRIDGE, IPL_HIGH, IST_LEVEL_HIGH,
+	    pic_handle_intr, &mvsoc_bridge_pic);
+	KASSERT(ih != NULL);
+
+	find_pending_irqs = orion_find_pending_irqs;
+}
+
+/* ARGSUSED */
+static void
+orion_pic_unblock_irqs(struct pic_softc *pic, size_t irqbase, uint32_t irq_mask)
+{
+
+	write_mlmbreg(ORION_MLMB_MIRQIMR,
+	    read_mlmbreg(ORION_MLMB_MIRQIMR) | irq_mask);
+}
+
+/* ARGSUSED */
+static void
+orion_pic_block_irqs(struct pic_softc *pic, size_t irqbase, uint32_t irq_mask)
+{
+
+	write_mlmbreg(ORION_MLMB_MIRQIMR,
+	    read_mlmbreg(ORION_MLMB_MIRQIMR) & ~irq_mask);
+}
+
+/* ARGSUSED */
+static void
+orion_pic_establish_irq(struct pic_softc *pic, struct intrsource *is)
+{
+	/* Nothing */
+}
+
+static void
+orion_pic_source_name(struct pic_softc *pic, int irq, char *buf, size_t len)
+{
+
+	strlcpy(buf, sources[pic->pic_irqbase + irq], len);
+}
+
+/*
+ * Called with interrupts disabled
+ */
+static int
+orion_find_pending_irqs(void)
+{
+	uint32_t pending;
+
+	pending =
+	    read_mlmbreg(ORION_MLMB_MICR) & read_mlmbreg(ORION_MLMB_MIRQIMR);
+	if (pending == 0)
+		return 0;
+
+	return pic_mark_pending_sources(&orion_pic, 0, pending);
+}
+
+/*
+ * Clock functions
+ */
+
+void
+orion_getclks(bus_addr_t iobase)
+{
+	static struct {
+		int armddrclkval;
+		uint32_t pclk;
+		uint32_t sysclk;
+	} sysclktbl[] = {
+		{ ORION_PMISMPL_ARMDDRCLK_333_167, 333000000, 166666667 },
+		{ ORION_PMISMPL_ARMDDRCLK_400_200, 400000000, 200000000 },
+		{ ORION_PMISMPL_ARMDDRCLK_400_133, 400000000, 133333334 },
+		{ ORION_PMISMPL_ARMDDRCLK_500_167, 500000000, 166666667 },
+		{ ORION_PMISMPL_ARMDDRCLK_533_133, 533000000, 133333334 },
+		{ ORION_PMISMPL_ARMDDRCLK_600_200, 600000000, 200000000 },
+		{ ORION_PMISMPL_ARMDDRCLK_667_167, 667000000, 166666667 },
+		{ ORION_PMISMPL_ARMDDRCLK_800_200, 800000000, 200000000 },
+		{ ORION_PMISMPL_ARMDDRCLK_480_160, 480000000, 160000000 },
+		{ ORION_PMISMPL_ARMDDRCLK_550_183, 550000000, 183333334 },
+		{ ORION_PMISMPL_ARMDDRCLK_525_175, 525000000, 175000000 },
+		{ ORION_PMISMPL_ARMDDRCLK_466_233, 466000000, 233000000 },
+		{ ORION_PMISMPL_ARMDDRCLK_500_250, 500000000, 250000000 },
+		{ ORION_PMISMPL_ARMDDRCLK_533_266, 533000000, 266000000 },
+		{ ORION_PMISMPL_ARMDDRCLK_600_300, 600000000, 300000000 },
+		{ ORION_PMISMPL_ARMDDRCLK_450_150, 450000000, 150000000 },
+		{ ORION_PMISMPL_ARMDDRCLK_533_178, 533000000, 178000000 },
+		{ ORION_PMISMPL_ARMDDRCLK_575_192, 575000000, 192000000 },
+		{ ORION_PMISMPL_ARMDDRCLK_700_175, 700000000, 175000000 },
+		{ ORION_PMISMPL_ARMDDRCLK_733_183, 733000000, 183333334 },
+		{ ORION_PMISMPL_ARMDDRCLK_750_187, 750000000, 187000000 },
+		{ ORION_PMISMPL_ARMDDRCLK_775_194, 775000000, 194000000 },
+		{ ORION_PMISMPL_ARMDDRCLK_500_125, 500000000, 125000000 },
+		{ ORION_PMISMPL_ARMDDRCLK_500_100, 500000000, 100000000 },
+		{ ORION_PMISMPL_ARMDDRCLK_600_150, 600000000, 150000000 },
+
+		{ 0, 0, 0 },
+	};
+	uint32_t reg, armddrclk, tclk;
+	uint16_t model;
+	int armddrclk_shift, tclk_shift, i;
+
+	model = mvsoc_model();
+	if (model == MARVELL_ORION_1_88F1181 ||
+	    model == MARVELL_ORION_2_88F1281) {
+		armddrclk_shift = 6;
+		tclk_shift = 10;
+	} else {
+		armddrclk_shift = 4;
+		tclk_shift = 8;
+	}
+
+	reg = *(volatile uint32_t *)(iobase + ORION_PMI_BASE +
+	    ORION_PMI_SAMPLE_AT_RESET);
+	armddrclk = (reg >> armddrclk_shift) & ORION_PMISMPL_ARMDDRCLK_MASK;
+	if (model == PCI_PRODUCT_MARVELL_88F5281)
+		if (reg & ORION_PMISMPL_ARMDDRCLK_H_MASK)
+			armddrclk |= 0x00000010;	/* set to bit4 */
+	for (i = 0; sysclktbl[i].pclk != 0; i++)
+		if (armddrclk == sysclktbl[i].armddrclkval) {
+			mvPclk = sysclktbl[i].pclk;
+			mvSysclk = sysclktbl[i].sysclk;
+			break;
+		}
+
+	tclk = (reg >> tclk_shift) & ORION_PMISMPL_TCLK_MASK;
+	switch (tclk) {
+	case ORION_PMISMPL_TCLK_133:
+		mvTclk = 133333334;	/* 133MHz */
+		break;
+
+	case ORION_PMISMPL_TCLK_150:
+		mvTclk = 150000000;	/* 150MHz */
+		break;
+
+	case ORION_PMISMPL_TCLK_166:
+		mvTclk = 166666667;	/* 166MHz */
+		break;
+
+	default:
+		mvTclk = 100000000;	/* 100MHz */
+		break;
+	}
+}
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/sys/arch/arm/marvell/orionreg.h	Sat Oct 09 03:31:35 2010 +0000
@@ -0,0 +1,206 @@
+/*	$NetBSD: orionreg.h,v 1.1.2.2 2010/10/09 03:31:40 yamt Exp $	*/
+/*
+ * Copyright (c) 2007, 2008 KIYOHARA Takashi
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _ORIONREG_H_
+#define _ORIONREG_H_
+
+#include <arm/marvell/mvsocreg.h>
+
+/*
+ *        Ver  GbE SATA  USB  PCI PCIe IDMA XORE CESA
+ * 1181:    1   -,   -,   -,   -,  x2,   ?,   -,   -
+ * 1281:    2   -,   -,   -,   -,  x2,   ?,   -,   -
+ * 5082:    1  x1,  x1,  x2,   -,  x1,   o,   -,   o
+ * 5180N:   1  x1,   -,  x1,  x1,  x1,   o,   -,   -
+ * 5181:    1  x1,   -,  x1,  x1,  x1,   o,   -,   o
+ * 5182:    1  x1,  x1,  x2,  x1,  x1,   o,   o,   o
+ * 5281:    2  x1,   -,  x1,  x1,  x1,   o,   -,   -
+ * 6082:    1  x2?, x1,  x1,   -,  x1,   -,   -,   o
+ * 6183:    1   ?,   -,  x?,   ?,   ?,   ?,   -,   -
+ * 8660:    1  x1,   -,  x1,  x1,  x1,   o,   -,   -
+ */
+
+#define ORION_UNITID_DDR		MVSOC_UNITID_DDR
+#define ORION_UNITID_DEVBUS		MVSOC_UNITID_DEVBUS
+#define ORION_UNITID_MLMB		MVSOC_UNITID_MLMB
+#define ORION_UNITID_PEX1		0x3			/* 1181 only */
+#define ORION_UNITID_PCI		0x3	/* PCI registers */
+#define ORION_UNITID_PEX		MVSOC_UNITID_PEX
+#define ORION_UNITID_USB0		0x5	/* USB registers Port0 */
+#define ORION_UNITID_IDMA		0x6	/* IDMA registers */
+#define ORION_UNITID_XOR		0x6	/* XOR registers */
+#define ORION_UNITID_GBE		0x7	/* Gigabit Ethernet registers */
+#define ORION_UNITID_SATA		0x8	/* SATA registers */
+#define ORION_UNITID_CRYPT		0x9	/* Cryptographic Engine reg */
+#define ORION_UNITID_SA			0x9	/* Security Accelerator reg */
+#define ORION_UNITID_USB1		0xa	/* USB registers Port1 */
+
+#define ORION_ATTR_DEVICE_CS0		0x1e
+#define ORION_ATTR_DEVICE_CS1		0x1d
+#define ORION_ATTR_DEVICE_CS2		0x1b
+#define ORION_ATTR_FLASH_CS		0x1b
+#define ORION_ATTR_BOOT_CS		0x0f
+#define ORION_ATTR_PEX_CFG		0x79	/* bug workaround ?? */
+#define ORION_ATTR_PEX_MEM		0x59
+#define ORION_ATTR_PEX_IO		0x51
+#define ORION_ATTR_PCI_MEM		0x59
+#define ORION_ATTR_PCI_IO		0x51
+#define ORION_ATTR_CRYPT		0x00
+
+/*
+ * Interrupt numbers
+ */
+#define ORION_IRQ_BRIDGE		0	/* Local to System Bridge */
+#define ORION_IRQ_HOST2CPU		1	/* Doorbell (Host-to-CPU) */
+#define ORION_IRQ_CPU2HOST		2	/* Doorbell (CPU-to-Host) */
+#define ORION_IRQ_UART0			3
+#define ORION_IRQ_UART1			4
+#define ORION_IRQ_TWSI			5	/* Two-Wire Serial Interface */
+#define ORION_IRQ_GPIO7_0		6	/* GPIO[7:0] */
+#define ORION_IRQ_GPIO15_8		7	/* GPIO[15:8] */
+#define ORION_IRQ_GPIO23_16		8	/* GPIO[23:16] not 1181 */
+#define ORION_IRQ_GPIO31_24		9	/* GPIO[31:24] not 1181 */
+#define ORION_IRQ_PEX0ERR		10	/* PCI Express error */
+#define ORION_IRQ_PEX0INT		11	/* PCIe INTA, B, C, D message */
+#define ORION_IRQ_PEX1ERR		12			/* 1181 only */
+#define ORION_IRQ_USBCNT1		12	/* USB Port1 controller (5182)*/
+#define ORION_IRQ_PEX1INT		13			/* 1181 only */
+#define ORION_IRQ_DEVERR		14	/* Device bus error */
+#define ORION_IRQ_PCIERR		15	/* PCI error */
+#define ORION_IRQ_USBBR			16	/* USB bridge Port0 or1 error */
+#define ORION_IRQ_USBCNT0		17	/* USB Port0 controller */
+#define ORION_IRQ_GBERX			18	/* GbE receive interrupt */
+#define ORION_IRQ_GBETX			19	/* GbE transmit interrupt */
+#define ORION_IRQ_GBEMISC		20	/* GbE miscellaneous intr */
+#define ORION_IRQ_GBESUM		21	/* GbE summary */
+#define ORION_IRQ_GBEERR		22	/* GbE error */
+#define ORION_IRQ_DMAERR		23	/* DMA or XOR error */
+#define ORION_IRQ_IDMA0			24	/* IDMA Channel0 completion */
+#define ORION_IRQ_IDMA1			25	/* IDMA Channel1 completion */
+#define ORION_IRQ_IDMA2			26	/* IDMA Channel2 completion */
+#define ORION_IRQ_IDMA3			27	/* IDMA Channel3 completion */
+#define ORION_IRQ_SECURITYINTR		28	/* Security accelerator intr */
+#define ORION_IRQ_SATAINTR		29	/* Serial-ATA interrupt */
+#define ORION_IRQ_XOR0			30	/* XOR engine 0 interrupt */
+#define ORION_IRQ_XOR1			31	/* XOR engine 1 interrupt */
+
+
+/*
+ * Physical address of integrated peripherals
+ */
+
+#define ORION_UNITID2PHYS(uid)	((ORION_UNITID_ ## uid) << 16)
+
+/*
+ * Pin Multiplexing Interface Registers
+ */
+#define ORION_PMI_BASE			(MVSOC_DEVBUS_BASE + 0x0000)
+#define ORION_PMI_SIZE			  0x100		/* XXXX */
+#define ORION_PMI_MPPCR0		   0x00
+#define ORION_PMI_MPPCR1		   0x04
+#define ORION_PMI_MPPCR2		   0x50
+#define ORION_PMI_DEVMULTICR		   0x08
+#define ORION_PMI_SAMPLE_AT_RESET	   0x10
+#define ORION_PMISMPL_ARMDDRCLK_MASK		0x0f
+#define ORION_PMISMPL_ARMDDRCLK_H_MASK		(1 << 23)
+#define ORION_PMISMPL_ARMDDRCLK_333_167		0x00
+#define ORION_PMISMPL_ARMDDRCLK_400_200		0x01
+#define ORION_PMISMPL_ARMDDRCLK_400_133		0x02
+#define ORION_PMISMPL_ARMDDRCLK_500_167		0x03
+#define ORION_PMISMPL_ARMDDRCLK_533_133		0x04
+#define ORION_PMISMPL_ARMDDRCLK_600_200		0x05
+#define ORION_PMISMPL_ARMDDRCLK_667_167		0x06
+#define ORION_PMISMPL_ARMDDRCLK_800_200		0x07
+#define ORION_PMISMPL_ARMDDRCLK_480_160		0x0c
+#define ORION_PMISMPL_ARMDDRCLK_550_183		0x0d
+#define ORION_PMISMPL_ARMDDRCLK_525_175		0x0e
+#define ORION_PMISMPL_ARMDDRCLK_466_233		0x11
+#define ORION_PMISMPL_ARMDDRCLK_500_250		0x12
+#define ORION_PMISMPL_ARMDDRCLK_533_266		0x13
+#define ORION_PMISMPL_ARMDDRCLK_600_300		0x14
+#define ORION_PMISMPL_ARMDDRCLK_450_150		0x15
+#define ORION_PMISMPL_ARMDDRCLK_533_178		0x16
+#define ORION_PMISMPL_ARMDDRCLK_575_192		0x17
+#define ORION_PMISMPL_ARMDDRCLK_700_175		0x18
+#define ORION_PMISMPL_ARMDDRCLK_733_183		0x19
+#define ORION_PMISMPL_ARMDDRCLK_750_187		0x1a
+#define ORION_PMISMPL_ARMDDRCLK_775_194		0x1b
+#define ORION_PMISMPL_ARMDDRCLK_500_125		0x1c
+#define ORION_PMISMPL_ARMDDRCLK_500_100		0x1d
+#define ORION_PMISMPL_ARMDDRCLK_600_150		0x1e
+#define ORION_PMISMPL_TCLK_MASK			0x3
+#define ORION_PMISMPL_TCLK_133			0x0
+#define ORION_PMISMPL_TCLK_150			0x1
+#define ORION_PMISMPL_TCLK_166			0x2
+
+/*
+ * Mbus-L to Mbus Bridge Registers
+ */
+/* CPU Address Map Registers */
+#define ORION_MLMB_NWINDOW		8          
+#define ORION_MLMB_NREMAP		2
+
+/* Main Interrupt Controller Registers */
+#define ORION_MLMB_MICR			  0x200	/* Main Interrupt Cause reg */
+#define ORION_MLMB_MIRQIMR		  0x204	/* Main IRQ Interrupt Mask */
+#define ORION_MLMB_MFIQIMR		  0x208	/* Main FIQ Interrupt Mask */
+#define ORION_MLMB_EIMR			  0x20c	/* Endpoint Interrupt Mask */
+
+/*
+ * PCI Express Interface Registers
+ *   or PCI Interface Registers
+ */
+#define ORION_PEX1_BASE		(ORION_UNITID2PHYS(PEX1))	/* 0x30000 */
+#define ORION_PCI_BASE		(ORION_UNITID2PHYS(PCI))	/* 0x30000 */
+
+/*
+ * USB 2.0 Interface Registers
+ */
+#define ORION_USB0_BASE		(ORION_UNITID2PHYS(USB0))	/* 0x50000 */
+#define ORION_USB1_BASE		(ORION_UNITID2PHYS(USB1))	/* 0xa0000 */
+
+/*
+ * IDMA Controller and XOR Engine Registers
+ */
+#define ORION_IDMAC_BASE	(ORION_UNITID2PHYS(IDMA))	/* 0x60000 */
+
+/*
+ * Gigabit Ethernet Registers
+ */
+#define ORION_GBE_BASE		(ORION_UNITID2PHYS(GBE))	/* 0x70000 */
+
+/*
+ * Serial-ATA Host Controller (SATAHC) Registers
+ */
+#define ORION_SATAHC_BASE	(ORION_UNITID2PHYS(SATA))	/* 0x80000 */
+
+/*
+ * Cryptographic Engine and Security Accelerator Registers
+ */
+#define ORION_CESA_BASE		(ORION_UNITID2PHYS(CRYPT))	/* 0x90000 */
+
+#endif	/* _ORIONREG_H_ */
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/sys/arch/arm/marvell/pci_machdep.c	Sat Oct 09 03:31:35 2010 +0000
@@ -0,0 +1,419 @@
+/*	$NetBSD: pci_machdep.c,v 1.1.2.2 2010/10/09 03:31:40 yamt Exp $	*/
+/*
+ * Copyright (c) 2008 KIYOHARA Takashi
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>
+__KERNEL_RCSID(0, "$NetBSD: pci_machdep.c,v 1.1.2.2 2010/10/09 03:31:40 yamt Exp $");
+
+#include "opt_mvsoc.h"
+#include "gtpci.h"
+#include "mvpex.h"
+#include "pci.h"
+
+#include <sys/param.h>
+#include <sys/device.h>
+#include <sys/extent.h>
+
+#include <dev/pci/pcivar.h>
+#include <dev/pci/pciconf.h>
+
+#include <arm/marvell/mvsocreg.h>
+#include <arm/marvell/mvsocvar.h>
+#include <arm/marvell/mvsocgppvar.h>
+#if NGTPCI > 0
+#include <dev/marvell/gtpcireg.h>
+#include <dev/marvell/gtpcivar.h>
+#endif
+#if NMVPEX > 0
+#include <dev/marvell/mvpexreg.h>
+#include <dev/marvell/mvpexvar.h>
+#endif
+
+#include <machine/pci_machdep.h>
+
+#if defined(ORION)
+#include <arm/marvell/orionreg.h>
+#endif
+#if defined(KIRKWOOD)
+#include <arm/marvell/kirkwoodreg.h>
+#endif
+#include <dev/marvell/marvellreg.h>
+
+
+#if NGTPCI > 0
+#if NGTPCI_MBUS > 0
+static pcireg_t gtpci_mbus_conf_read(void *, pcitag_t, int);
+static void gtpci_mbus_conf_write(void *, pcitag_t, int, pcireg_t);
+#endif
+static int gtpci_gpp_intr_map(struct pci_attach_args *, pci_intr_handle_t *);
+static const char *gtpci_gpp_intr_string(void *, pci_intr_handle_t);
+static const struct evcnt *gtpci_gpp_intr_evcnt(void *, pci_intr_handle_t);
+static void *gtpci_gpp_intr_establish(void *, pci_intr_handle_t, int, int (*)(void *), void *);
+static void gtpci_gpp_intr_disestablish(void *, void *);
+
+struct arm32_pci_chipset arm32_gtpci_chipset = {
+	NULL,	/* conf_v */
+	gtpci_attach_hook,
+	gtpci_bus_maxdevs,
+	gtpci_make_tag,
+	gtpci_decompose_tag,
+#if NGTPCI_MBUS > 0
+	gtpci_mbus_conf_read,		/* XXXX: always this functions */
+	gtpci_mbus_conf_write,
+#else
+	gtpci_conf_read,
+	gtpci_conf_write,
+#endif
+	NULL,	/* intr_v */
+	gtpci_gpp_intr_map,
+	gtpci_gpp_intr_string,
+	gtpci_gpp_intr_evcnt,
+	gtpci_gpp_intr_establish,
+	gtpci_gpp_intr_disestablish,
+#ifdef __HAVE_PCI_CONF_HOOK
+	gtpci_conf_hook,
+#endif
+};
+#endif
+
+#if NMVPEX > 0
+#if NMVPEX_MBUS > 0
+static pcireg_t mvpex_mbus_conf_read(void *, pcitag_t, int);
+#endif
+
+struct arm32_pci_chipset arm32_mvpex0_chipset = {
+	NULL,	/* conf_v */
+	mvpex_attach_hook,
+	mvpex_bus_maxdevs,
+	mvpex_make_tag,
+	mvpex_decompose_tag,
+#if NMVPEX_MBUS > 0
+	mvpex_mbus_conf_read,		/* XXXX: always this functions */
+#else
+	mvpex_conf_read,
+#endif
+	mvpex_conf_write,
+	NULL,	/* intr_v */
+	mvpex_intr_map,
+	mvpex_intr_string,
+	mvpex_intr_evcnt,
+	mvpex_intr_establish,
+	mvpex_intr_disestablish,
+#ifdef __HAVE_PCI_CONF_HOOK
+	mvpex_conf_hook,
+#endif
+};
+struct arm32_pci_chipset arm32_mvpex1_chipset = {
+	NULL,	/* conf_v */
+	mvpex_attach_hook,
+	mvpex_bus_maxdevs,
+	mvpex_make_tag,
+	mvpex_decompose_tag,
+#if NMVPEX_MBUS > 0
+	mvpex_mbus_conf_read,		/* XXXX: always this functions */
+#else
+	mvpex_conf_read,
+#endif
+	mvpex_conf_write,
+	NULL,	/* intr_v */
+	mvpex_intr_map,
+	mvpex_intr_string,
+	mvpex_intr_evcnt,
+	mvpex_intr_establish,
+	mvpex_intr_disestablish,
+#ifdef __HAVE_PCI_CONF_HOOK
+	mvpex_conf_hook,
+#endif
+};
+#endif
+
+
+void
+pci_conf_interrupt(pci_chipset_tag_t v, int bus, int dev, int pin, int swiz,
+		   int *iline)
+{
+
+	/* nothing */
+}
+
+
+#if NGTPCI > 0
+#if NGTPCI_MBUS > 0
+#define GTPCI_MBUS_CA		0x0c78	/* Configuration Address */
+#define GTPCI_MBUS_CD		0x0c7c	/* Configuration Data */
+
+static pcireg_t
+gtpci_mbus_conf_read(void *v, pcitag_t tag, int reg)
+{
+	struct gtpci_softc *sc = v;
+	const pcireg_t addr = tag | reg;
+
+	bus_space_write_4(sc->sc_iot, sc->sc_ioh, GTPCI_MBUS_CA,
+	    addr | GTPCI_CA_CONFIGEN);
+	if ((addr | GTPCI_CA_CONFIGEN) !=
+	    bus_space_read_4(sc->sc_iot, sc->sc_ioh, GTPCI_MBUS_CA))
+		return -1;
+
+	return bus_space_read_4(sc->sc_iot, sc->sc_ioh, GTPCI_MBUS_CD);
+}
+
+static void
+gtpci_mbus_conf_write(void *v, pcitag_t tag, int reg, pcireg_t data)
+{
+	struct gtpci_softc *sc = v;
+	pcireg_t addr = tag | (reg & 0xfc);
+
+	bus_space_write_4(sc->sc_iot, sc->sc_ioh, GTPCI_MBUS_CA,
+	    addr | GTPCI_CA_CONFIGEN);
+	if ((addr | GTPCI_CA_CONFIGEN) !=
+	    bus_space_read_4(sc->sc_iot, sc->sc_ioh, GTPCI_MBUS_CA))
+		return;
+
+	bus_space_write_4(sc->sc_iot, sc->sc_ioh, GTPCI_MBUS_CD, data);
+}
+#endif	/* NGTPCI_MBUS */
+
+/*
+ * We assume to use GPP interrupt as PCI interrupts.
+ *   pci_intr_map() shall returns number of GPP between 0 and 31.  However
+ *   returns 0xff, because we do not know the connected pin number for GPP
+ *   of your board.
+ *   pci_intr_string() shall returns string "gpp <num>".
+ *   pci_intr_establish() established interrupt in the pin of all GPP.
+ *   Moreover, the return value will be disregarded.  For instance, the
+ *   setting for interrupt is not done.
+ */
+
+/* ARGSUSED */
+static int
+gtpci_gpp_intr_map(struct pci_attach_args *pa, pci_intr_handle_t *ihp)
+{
+
+	*ihp = pa->pa_intrpin;
+	return 0;
+}
+
+/* ARGSUSED */
+static const char *
+gtpci_gpp_intr_string(void *v, pci_intr_handle_t pin)
+{
+	struct gtpci_softc *sc = v;
+	prop_array_t int2gpp;
+	prop_object_t gpp;
+	static char intrstr[8];
+
+	int2gpp = prop_dictionary_get(device_properties(sc->sc_dev), "int2gpp");
+	gpp = prop_array_get(int2gpp, pin);
+	sprintf(intrstr, "gpp %d", (int)prop_number_integer_value(gpp));
+
+	return intrstr;
+}
+
+/* ARGSUSED */
+static const struct evcnt *
+gtpci_gpp_intr_evcnt(void *v, pci_intr_handle_t pin)
+{
+
+	return NULL;
+}
+
+static void *
+gtpci_gpp_intr_establish(void *v, pci_intr_handle_t int_pin, int ipl,
+		         int (*intrhand)(void *), void *intrarg)
+{
+	struct gtpci_softc *sc = v;
+	prop_array_t int2gpp;
+	prop_object_t gpp;
+	int gpp_pin;
+
+	int2gpp = prop_dictionary_get(device_properties(sc->sc_dev), "int2gpp");
+	gpp = prop_array_get(int2gpp, int_pin);
+	gpp_pin = prop_number_integer_value(gpp);
+	return mvsocgpp_intr_establish(gpp_pin, ipl, 0, intrhand, intrarg);
+}
+
+static void
+gtpci_gpp_intr_disestablish(void *v, void *ih)
+{
+
+	mvsocgpp_intr_disestablish(ih);
+}
+#endif
+
+#if NMVPEX_MBUS > 0
+static pcireg_t
+mvpex_mbus_conf_read(void *v, pcitag_t tag, int reg)
+{
+	struct mvpex_softc *sc = v;
+	pcireg_t addr, data, pci_cs;
+	uint32_t stat;
+	int bus, dev, func, pexbus, pexdev;
+
+	mvpex_decompose_tag(v, tag, &bus, &dev, &func);
+
+	stat = bus_space_read_4(sc->sc_iot, sc->sc_ioh, MVPEX_STAT);
+	pexbus = MVPEX_STAT_PEXBUSNUM(stat);
+	pexdev = MVPEX_STAT_PEXDEVNUM(stat);
+	if (bus != pexbus || dev != pexdev)
+		if (stat & MVPEX_STAT_DLDOWN)
+			return -1;
+
+	if (bus == pexbus) {
+		if (pexdev == 0) {
+			if (dev != 1 && dev != pexdev)
+				return -1;
+		} else {
+			if (dev != 0 && dev != pexdev)
+				return -1;
+		}
+		if (func != 0)
+			return -1;
+	}
+
+	addr = ((reg & 0xf00) << 24)  | tag | (reg & 0xfc);
+
+#if defined(ORION)
+	/*
+	 * Guideline (GL# PCI Express-1) Erroneous Read Data on Configuration
+	 * This guideline is relevant for all devices except of the following
+	 * devices:
+	 *     88F5281-BO and above, and 88F5181L-A0 and above
+	 */
+	if ((bus != pexbus || dev != pexdev) &&
+	    !(sc->sc_model == MARVELL_ORION_2_88F5281 && sc->sc_rev == 1) &&
+	    !(sc->sc_model == MARVELL_ORION_1_88F5181 && sc->sc_rev == 8)) {
+
+		/* PCI-Express configuration read work-around */
+		/*
+		 * We will use one of the Punit (AHBToMbus) windows to
+		 * access the xbar and read the data from there
+		 *
+		 * Need to configure the 2 free Punit (AHB to MBus bridge)
+		 * address decoding windows:
+		 * Configure the flash Window to handle Configuration space
+		 * requests for PEX0/1:
+		 *
+		 * Configuration transactions from the CPU should write/read
+		 * the data to/from address of the form:
+		 *	addr[31:28]: 0x5 (for PEX0) or 0x6 (for PEX1)
+		 *	addr[27:24]: extended register number
+		 *	addr[23:16]: bus number
+		 *	addr[15:11]: device number
+		 *	addr[10: 8]: function number
+		 *	addr[ 7: 0]: register number
+		 */
+
+		struct mvsoc_softc *soc =
+		    device_private(device_parent(sc->sc_dev));;
+		bus_space_handle_t pcicfg_ioh;
+		uint32_t remapl, remaph, wc, pcicfg_addr, pcicfg_size;
+		int window, target, attr, base, size, s;
+		const int pex_pcicfg_tag =
+		    (sc->sc_model == MARVELL_ORION_1_88F1181) ?
+		    ORION_TAG_FLASH_CS : ORION_TAG_PEX0_MEM;
+
+		window = mvsoc_target(pex_pcicfg_tag,
+		    &target, &attr, &base, &size);
+		if (window >= nwindow) {
+			aprint_error_dev(sc->sc_dev,
+			    "can't read pcicfg space\n");
+			return -1;
+		}
+
+		s = splhigh();
+
+		remapl = remaph = 0;
+		if (window == 0 || window == 1) {
+			remapl = read_mlmbreg(MVSOC_MLMB_WRLR(window));
+			remaph = read_mlmbreg(MVSOC_MLMB_WRHR(window));
+		}
+
+		wc =
+		    MVSOC_MLMB_WCR_WINEN			|
+		    MVSOC_MLMB_WCR_ATTR(ORION_ATTR_PEX_CFG)	|
+		    MVSOC_MLMB_WCR_TARGET((soc->sc_addr + sc->sc_offset) >> 16);
+		if (sc->sc_model == MARVELL_ORION_1_88F1181) {
+			pcicfg_addr = base;
+			pcicfg_size = size;
+		} else if (sc->sc_model == MARVELL_ORION_1_88F5182) {
+#define PEX_PCICFG_RW_WA_BASE		0x50000000
+#define PEX_PCICFG_RW_WA_5182_BASE	0xf0000000
+#define PEX_PCICFG_RW_WA_SIZE		(16 * 1024 * 1024)
+			pcicfg_addr = PEX_PCICFG_RW_WA_5182_BASE;
+			pcicfg_size = PEX_PCICFG_RW_WA_SIZE;
+		} else {
+			pcicfg_addr = PEX_PCICFG_RW_WA_BASE;
+			pcicfg_size = PEX_PCICFG_RW_WA_SIZE;
+		}
+		write_mlmbreg(MVSOC_MLMB_WCR(window),
+		    wc | MVSOC_MLMB_WCR_SIZE(pcicfg_size));
+		write_mlmbreg(MVSOC_MLMB_WBR(window), pcicfg_addr);
+
+		if (window == 0 || window == 1) {
+			write_mlmbreg(MVSOC_MLMB_WRLR(window), pcicfg_addr);
+			write_mlmbreg(MVSOC_MLMB_WRHR(window), 0);
+		}
+
+		if (bus_space_map(sc->sc_iot, pcicfg_addr, pcicfg_size, 0,
+		    &pcicfg_ioh) == 0) {
+			data = bus_space_read_4(sc->sc_iot, pcicfg_ioh, addr);
+			bus_space_unmap(sc->sc_iot, pcicfg_ioh, pcicfg_size);
+		} else
+			data = -1;
+
+		write_mlmbreg(MVSOC_MLMB_WCR(window),
+		    MVSOC_MLMB_WCR_WINEN		|
+		    MVSOC_MLMB_WCR_ATTR(attr)		|
+		    MVSOC_MLMB_WCR_TARGET(target)	|
+		    MVSOC_MLMB_WCR_SIZE(size));
+		write_mlmbreg(MVSOC_MLMB_WBR(window), base);
+		if (window == 0 || window == 1) {
+			write_mlmbreg(MVSOC_MLMB_WRLR(window), remapl);
+			write_mlmbreg(MVSOC_MLMB_WRHR(window), remaph);
+		}
+
+		splx(s);
+#else
+	if (0) {
+#endif
+	} else {
+		bus_space_write_4(sc->sc_iot, sc->sc_ioh, MVPEX_CA,
+		    addr | MVPEX_CA_CONFIGEN);
+		if ((addr | MVPEX_CA_CONFIGEN) !=
+		    bus_space_read_4(sc->sc_iot, sc->sc_ioh, MVPEX_CA))
+			return -1;
+
+		pci_cs = bus_space_read_4(sc->sc_iot, sc->sc_ioh,
+		    PCI_COMMAND_STATUS_REG);
+		bus_space_write_4(sc->sc_iot, sc->sc_ioh,
+		    PCI_COMMAND_STATUS_REG, pci_cs | PCI_STATUS_MASTER_ABORT);
+
+		data = bus_space_read_4(sc->sc_iot, sc->sc_ioh, MVPEX_CD);
+	}
+
+	return data;
+}
+#endif
--- a/sys/arch/arm/omap/files.omap2	Sun Sep 26 03:58:54 2010 +0000
+++ b/sys/arch/arm/omap/files.omap2	Sat Oct 09 03:31:35 2010 +0000
@@ -1,4 +1,4 @@
-#	$NetBSD: files.omap2,v 1.1.22.3 2010/08/11 22:51:42 yamt Exp $
+#	$NetBSD: files.omap2,v 1.1.22.4 2010/10/09 03:31:40 yamt Exp $
 #
 # Configuration info for Texas Instruments OMAP2/OMAP3 CPU support
 # Based on xscale/files.pxa2x0
@@ -19,9 +19,9 @@
 defflag opt_omap.h				OMAP_3530: OMAP3
 
 # OBIO just an attach point
-device obio { [addr=-1], [size=0], [intr=-1], [mult=1], [intrbase=-1], [nobyteacc=0]
+device	obio { [addr=-1], [size=0], [intr=-1], [mult=1], [intrbase=-1], [nobyteacc=0]
 	     } : bus_space_generic
-attach obio at mainbus
+attach	obio at mainbus
 file	arch/arm/omap/omap2_obio.c		obio needs-count
 
 # OBIO files
@@ -59,33 +59,38 @@
 
 # Watchdog timers
 
-device omapwdt32k: sysmon_wdog
-file arch/arm/omap/omap_wdt.c			omapwdt32k needs-flag
+device	omapwdt32k: sysmon_wdog
+file	arch/arm/omap/omap_wdt.c		omapwdt32k needs-flag
 
-attach omapwdt32k at obio with obiowdt32k
-file arch/arm/omap/obio_wdt.c			obiowdt32k
+attach	omapwdt32k at obio with obiowdt32k
+file	arch/arm/omap/obio_wdt.c		obiowdt32k
 
 # L3 Interconnect
-device L3i { [addr=-1], [size=0], [intr=-1], [mult=1], [nobyteacc=0]
-	     } : bus_space_generic
-attach L3i at mainbus
+device	L3i { [addr=-1], [size=0], [intr=-1], [mult=1], [nobyteacc=0]
+	      } : bus_space_generic
+attach	L3i at mainbus
 file	arch/arm/omap/omap2_l3i.c		omap2 | omap3
 
 # General Purpose Memory Controller
 # XXX some addl. chip select config parms may be desired here (e.g. timing)
 # XXX so far we just use the setup established by boot firmware
-device gpmc { [addr=-1], [size=0], [intr=-1], [mult=1], [nobyteacc=0]
-	     } : bus_space_generic
-attach gpmc at mainbus
+device	gpmc { [addr=-1], [size=0], [intr=-1], [mult=1], [nobyteacc=0]
+	      } : bus_space_generic
+attach	gpmc at mainbus
 file	arch/arm/omap/omap2_gpmc.c		gpmc
 
+# PRCM interface
+device	prcm
+attach	prcm at obio
+file	arch/arm/omap/omap2_prcm.c		prcm needs-flag
+
 # OHCI USB controller
 ##attach	ohci at obio with obioohci:		omapgpio
 attach	ohci at obio with obioohci
 file	arch/arm/omap/obio_ohci.c		obioohci
 
-device omapfb: rasops16, rasops8, wsemuldisplaydev, vcons
-attach omapfb at obio
+device	omapfb: rasops16, rasops8, wsemuldisplaydev, vcons
+attach	omapfb at obio
 file	arch/arm/omap/omapfb.c			omapfb
 
 # these bus space methods are not bus-specific ...
--- a/sys/arch/arm/omap/omap2_gpmc.c	Sun Sep 26 03:58:54 2010 +0000
+++ b/sys/arch/arm/omap/omap2_gpmc.c	Sat Oct 09 03:31:35 2010 +0000
@@ -1,7 +1,7 @@
-/*	$Id: omap2_gpmc.c,v 1.1.22.3 2010/08/11 22:51:42 yamt Exp $	*/
+/*	$Id: omap2_gpmc.c,v 1.1.22.4 2010/10/09 03:31:40 yamt Exp $	*/
 
 /* adapted from: */
-/*	$NetBSD: omap2_gpmc.c,v 1.1.22.3 2010/08/11 22:51:42 yamt Exp $ */
+/*	$NetBSD: omap2_gpmc.c,v 1.1.22.4 2010/10/09 03:31:40 yamt Exp $ */
 
 
 /*
@@ -102,7 +102,7 @@
 
 #include "opt_omap.h"
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: omap2_gpmc.c,v 1.1.22.3 2010/08/11 22:51:42 yamt Exp $");
+__KERNEL_RCSID(0, "$NetBSD: omap2_gpmc.c,v 1.1.22.4 2010/10/09 03:31:40 yamt Exp $");
 
 #include "locators.h"
 
@@ -200,7 +200,7 @@
 	rev = bus_space_read_4(sc->sc_iot, ioh, GPMC_REVISION);
 
 	aprint_normal(", rev %d.%d\n",
-		GPMC_REVISION_REV_MAJ(rev), 
+		GPMC_REVISION_REV_MAJ(rev),
 		GPMC_REVISION_REV_MIN(rev));
 
 	sc->sc_ioh = ioh;
@@ -222,7 +222,6 @@
 	gpmc_csconfig_t *cs;
 	uint32_t r;
 	int i;
-	
 
 	cs = &sc->sc_csconfig[0];
 	for (i=0; i < GPMC_NCS; i++) {
@@ -317,3 +316,15 @@
 
 	return UNCONF;
 }
+
+uint32_t
+gpmc_register_read(struct gpmc_softc *sc, bus_size_t reg)
+{
+	return bus_space_read_4(sc->sc_iot, sc->sc_ioh, reg);
+}
+
+void
+gpmc_register_write(struct gpmc_softc *sc, bus_size_t reg, const uint32_t data)
+{
+	bus_space_write_4(sc->sc_iot, sc->sc_ioh, reg, data);
+}
--- a/sys/arch/arm/omap/omap2_gpmcreg.h	Sun Sep 26 03:58:54 2010 +0000
+++ b/sys/arch/arm/omap/omap2_gpmcreg.h	Sat Oct 09 03:31:35 2010 +0000
@@ -1,4 +1,4 @@
-/*	$NetBSD: omap2_gpmcreg.h,v 1.2.12.3 2010/08/11 22:51:42 yamt Exp $	*/
+/*	$NetBSD: omap2_gpmcreg.h,v 1.2.12.4 2010/10/09 03:31:40 yamt Exp $	*/
 /*
  * Copyright (c) 2007 Microsoft
  * All rights reserved.
@@ -198,6 +198,12 @@
 #define GPMC_CONFIG7_BASEADDRESS	__BITS(5,0)
 #define GPMC_CONFIG7_CSVALID		__BIT(6)
 #define GPMC_CONFIG7_MASKADDRESS	__BITS(11,8)
+#define GPMC_CONFIG7(m, b)		(((m) << 8) | (((b) >> 24) & 0x3f))
+#define GPMC_CONFIG7_MASK_256M		0x0
+#define GPMC_CONFIG7_MASK_128M		0x8
+#define GPMC_CONFIG7_MASK_64M		0xc
+#define GPMC_CONFIG7_MASK_32M		0xe
+#define GPMC_CONFIG7_MASK_16M		0xf
 
 static __inline ulong
 omap_gpmc_config7_addr(uint32_t r)
@@ -213,16 +219,16 @@
 		uint  mask;
 		ulong size;
 	} gpmc_config7_size_tab[5] = {
-		{ 0x0, (256 << 20) },		/* 256 MB */
-		{ 0x8, (128 << 20) },		/* 128 MB */
-		{ 0xc, ( 64 << 20) },		/*  64 MB */
-		{ 0xe, ( 32 << 20) },		/*  32 MB */
-		{ 0xf, ( 16 << 20) },		/*  16 MB */
+		{ GPMC_CONFIG7_MASK_256M, (256 << 20) },
+		{ GPMC_CONFIG7_MASK_128M, (128 << 20) },
+		{ GPMC_CONFIG7_MASK_64M,  ( 64 << 20) },
+		{ GPMC_CONFIG7_MASK_32M,  ( 32 << 20) },
+		{ GPMC_CONFIG7_MASK_16M,  ( 16 << 20) },
 	};
 	mask = ((r) & GPMC_CONFIG7_MASKADDRESS) >> 8;
 	for (i=0; i < 5; i++) {
 		if (gpmc_config7_size_tab[i].mask == mask)
-		return gpmc_config7_size_tab[i].size;
+			return gpmc_config7_size_tab[i].size;
 	}
 	return 0;
 }
--- a/sys/arch/arm/omap/omap2_gpmcvar.h	Sun Sep 26 03:58:54 2010 +0000
+++ b/sys/arch/arm/omap/omap2_gpmcvar.h	Sat Oct 09 03:31:35 2010 +0000
@@ -1,4 +1,4 @@
-/*	$NetBSD: omap2_gpmcvar.h,v 1.1.18.3 2010/08/11 22:51:42 yamt Exp $	*/
+/*	$NetBSD: omap2_gpmcvar.h,v 1.1.18.4 2010/10/09 03:31:40 yamt Exp $	*/
 /*
  * Copyright (c) 2007 Microsoft
  * All rights reserved.
@@ -41,4 +41,10 @@
 	int		gpmc_cs;
 };
 
+struct gpmc_softc;
+
+uint32_t gpmc_register_read(struct gpmc_softc *sc, bus_size_t reg);
+void gpmc_register_write(struct gpmc_softc *sc, bus_size_t reg,
+    const uint32_t data);
+
 #endif /* _OMAP2430GPMCVAR_H */
--- a/sys/arch/arm/omap/omap2_intr.h	Sun Sep 26 03:58:54 2010 +0000
+++ b/sys/arch/arm/omap/omap2_intr.h	Sat Oct 09 03:31:35 2010 +0000
@@ -1,4 +1,4 @@
-/*	$NetBSD: omap2_intr.h,v 1.1.10.2 2009/05/04 08:10:44 yamt Exp $ */
+/*	$NetBSD: omap2_intr.h,v 1.1.10.3 2010/10/09 03:31:40 yamt Exp $ */
 
 /*
  * Define the SDP2430 specific information and then include the generic OMAP
@@ -166,7 +166,7 @@
 #define	IRQ_GPT12_3530		95	/* (3530) GPT12 */
 
 #define	PIC_MAXSOURCES		96
-#define	PIC_MAXMAXSOURCES	(96+160)
+#define	PIC_MAXMAXSOURCES	(96+192)
 
 extern void omap_irq_handler(void *);
 
--- a/sys/arch/arm/omap/omap2_obio.c	Sun Sep 26 03:58:54 2010 +0000
+++ b/sys/arch/arm/omap/omap2_obio.c	Sat Oct 09 03:31:35 2010 +0000
@@ -1,7 +1,7 @@
-/*	$Id: omap2_obio.c,v 1.1.22.3 2010/08/11 22:51:42 yamt Exp $	*/
+/*	$Id: omap2_obio.c,v 1.1.22.4 2010/10/09 03:31:40 yamt Exp $	*/
 
 /* adapted from: */
-/*	$NetBSD: omap2_obio.c,v 1.1.22.3 2010/08/11 22:51:42 yamt Exp $ */
+/*	$NetBSD: omap2_obio.c,v 1.1.22.4 2010/10/09 03:31:40 yamt Exp $ */
 
 
 /*
@@ -103,7 +103,7 @@
 
 #include "opt_omap.h"
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: omap2_obio.c,v 1.1.22.3 2010/08/11 22:51:42 yamt Exp $");
+__KERNEL_RCSID(0, "$NetBSD: omap2_obio.c,v 1.1.22.4 2010/10/09 03:31:40 yamt Exp $");
 
 #include "locators.h"
 #include "obio.h"
@@ -359,7 +359,6 @@
 #if 0
 	{ .name = "dmac", .addr = DMAC_BASE, .required = true },
 #endif
-	{ .name = "omapmputmr0", .addr = GPT2_BASE, .required = true },
 };
 
 static void
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/sys/arch/arm/omap/omap2_prcm.c	Sat Oct 09 03:31:35 2010 +0000
@@ -0,0 +1,122 @@
+/*	$NetBSD: omap2_prcm.c,v 1.1.2.2 2010/10/09 03:31:40 yamt Exp $	*/
+
+/*-
+ * Copyright (c) 2010 Adam Hoka
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include "opt_omap.h"
+#include <sys/cdefs.h>
+__KERNEL_RCSID(0, "$NetBSD: omap2_prcm.c,v 1.1.2.2 2010/10/09 03:31:40 yamt Exp $");
+
+#include <sys/param.h>
+#include <sys/device.h>
+
+#include <machine/bus.h>
+
+#include <arm/omap/omap_var.h>
+
+#include <arm/omap/omap2_obiovar.h>
+#include <arm/omap/omap2_reg.h>
+#include <arm/omap/omap2_prcm.h>
+
+#include "locators.h"
+
+struct prcm_softc {
+	device_t		sc_dev;
+	bus_space_tag_t		sc_iot;
+	bus_space_handle_t	sc_ioh;
+	bus_addr_t		sc_base;
+	bus_size_t		sc_size;
+};
+
+/* for external access to prcm operations */
+struct prcm_softc *prcm_sc;
+
+/* prototypes */
+static int	prcm_match(device_t, cfdata_t, void *);
+static void	prcm_attach(device_t, device_t, void *);
+
+/* attach structures */
+CFATTACH_DECL_NEW(prcm, sizeof(struct prcm_softc),
+	prcm_match, prcm_attach, NULL, NULL);
+
+static int
+prcm_match(device_t parent, cfdata_t match, void *aux)
+{
+	struct obio_attach_args *obio = aux;
+
+	if (obio->obio_addr != OBIOCF_ADDR_DEFAULT)
+		return 1;
+	return 0;
+}
+
+static void
+prcm_attach(device_t parent, device_t self, void *aux)
+{
+	struct obio_attach_args *obio = aux;
+
+	prcm_sc = device_private(self);
+
+	prcm_sc->sc_dev = self;
+	prcm_sc->sc_iot = &omap_bs_tag;
+
+	prcm_sc->sc_base = obio->obio_addr;
+	prcm_sc->sc_size = OMAP2_PRM_SIZE;
+	
+	/* map i/o space for PRM */
+	if (bus_space_map(prcm_sc->sc_iot, prcm_sc->sc_base, prcm_sc->sc_size,
+	    0, &prcm_sc->sc_ioh) != 0) {
+		aprint_error("prcm_attach: can't map i/o space for prm");
+		return;
+	}
+
+	aprint_normal(": Power, Reset and Clock Management\n");
+}
+
+static uint32_t
+prcm_read(bus_addr_t module, bus_addr_t reg)
+{	
+	return bus_space_read_4(prcm_sc->sc_iot, prcm_sc->sc_ioh,
+	    module + reg);
+}
+
+static void
+prcm_write(bus_addr_t module, bus_addr_t reg, uint32_t data)
+{	
+	bus_space_write_4(prcm_sc->sc_iot, prcm_sc->sc_ioh,
+	    module + reg, data);
+}
+
+void
+prcm_cold_reset()
+{
+	uint32_t val;
+	
+	val = prcm_read(OMAP3430_GR_MOD, OMAP2_RM_RSTCTRL);
+
+	val |= OMAP_RST_DPLL3;
+
+	prcm_write(OMAP3430_GR_MOD, OMAP2_RM_RSTCTRL, val);
+}
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/sys/arch/arm/omap/omap2_prcm.h	Sat Oct 09 03:31:35 2010 +0000
@@ -0,0 +1,34 @@
+/*	$NetBSD: omap2_prcm.h,v 1.1.2.2 2010/10/09 03:31:40 yamt Exp $	*/
+
+/*-
+ * Copyright (c) 2010 Adam Hoka
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#ifndef _OMAP2_PRCM_H_
+#define _OMAP2_PRCM_H_
+
+void prcm_cold_reset(void);
+
+#endif
--- a/sys/arch/arm/omap/omap2_reg.h	Sun Sep 26 03:58:54 2010 +0000
+++ b/sys/arch/arm/omap/omap2_reg.h	Sat Oct 09 03:31:35 2010 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: omap2_reg.h,v 1.1.18.3 2010/08/11 22:51:42 yamt Exp $ */
+/* $NetBSD: omap2_reg.h,v 1.1.18.4 2010/10/09 03:31:40 yamt Exp $ */
 
 /*
  * Copyright (c) 2007 Microsoft
@@ -231,6 +231,51 @@
 
 
 /*
+ * Power Management registers base, offsets, and size
+ */
+#ifdef OMAP_3530
+#define	OMAP2_PRM_BASE			0x48306000
+#endif
+
+#define OMAP2_PRM_SIZE			0x00002000 /* 8k */
+
+/* module offsets */
+#define OCP_MOD		0x0800
+#define MPU_MOD		0x0900
+#define CORE_MOD	0x0a00
+#define GFX_MOD		0x0b00
+#define WKUP_MOD	0x0c00
+#define PLL_MOD		0x0d00
+
+/* module offsets specific to chip */
+#define OMAP24XX_GR_MOD		OCP_MOD
+#define OMAP24XX_DSP_MOD	0x1000
+#define OMAP2430_MDM_MOD	0x1400
+#define OMAP3430_IVA2_MOD	0x0000 /* IVA2 before base! */
+#define OMAP3430ES2_SGX_MOD	GFX_MOD
+#define OMAP3430_CCR_MOD	PLL_MOD
+#define OMAP3430_DSS_MOD	0x0e00
+#define OMAP3430_CAM_MOD	0x0f00
+#define OMAP3430_PER_MOD	0x1000
+#define OMAP3430_EMU_MOD	0x1100
+#define OMAP3430_GR_MOD		0x1200
+#define OMAP3430_NEON_MOD	0x1300
+#define OMAP3430ES2_USBHOST_MOD	0x1400
+
+#define OMAP2_RM_RSTCTRL	0x50
+#define OMAP2_RM_RSTTIME	0x54
+#define OMAP2_RM_RSTST		0x58
+#define OMAP2_PM_WKDEP		0xc8
+#define OMAP2_PM_PWSTCTRL	0xe0
+#define OMAP2_PM_PWSTST		0xe4
+#define OMAP2_PM_PREPWSTST	0xe8
+#define OMAP2_PRM_IRQSTATUS	0xf8
+#define OMAP2_PRM_IRQENABLE	0xfc
+
+#define OMAP_RST_DPLL3		__BIT(2)
+#define OMAP_RST_GS		__BIT(1)
+
+/*
  * L3 Interconnect Target Agent Common Registers
  */
 #define OMAP2_TA_GPMC		0x68002400
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/sys/arch/arm/omap/omapfb.c	Sat Oct 09 03:31:35 2010 +0000
@@ -0,0 +1,690 @@
+/*	$NetBSD: omapfb.c,v 1.1.2.2 2010/10/09 03:31:40 yamt Exp $	*/
+
+/*
+ * Copyright (c) 2010 Michael Lorenz
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ * A console driver for OMAP 3530's built-in video controller
+ * tested on beagleboard only so far
+ */
+
+#include <sys/cdefs.h>
+__KERNEL_RCSID(0, "$NetBSD: omapfb.c,v 1.1.2.2 2010/10/09 03:31:40 yamt Exp $");
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/kernel.h>
+#include <sys/device.h>
+#include <sys/malloc.h>
+#include <sys/lwp.h>
+#include <sys/kauth.h>
+
+#include <uvm/uvm_extern.h>
+
+#include <dev/videomode/videomode.h>
+
+#include <machine/bus.h>
+#include <arm/omap/omapfbreg.h>
+#include <arm/omap/omap2_obiovar.h>
+#include <arm/omap/omap2_obioreg.h>
+
+#include <dev/wscons/wsdisplayvar.h>
+#include <dev/wscons/wsconsio.h>
+#include <dev/wsfont/wsfont.h>
+#include <dev/rasops/rasops.h>
+#include <dev/wscons/wsdisplay_vconsvar.h>
+
+struct omapfb_softc {
+	device_t sc_dev;
+
+	bus_space_tag_t sc_iot;
+	bus_dma_tag_t sc_dmat;
+	bus_space_handle_t sc_regh;
+	bus_dmamap_t sc_dmamap;
+	bus_dma_segment_t sc_dmamem[1];
+	size_t sc_vramsize;
+
+	int sc_width, sc_height, sc_depth, sc_stride;
+	int sc_locked;
+	void *sc_fbaddr, *sc_vramaddr;
+	uint32_t *sc_clut;
+	struct vcons_screen sc_console_screen;
+	struct wsscreen_descr sc_defaultscreen_descr;
+	const struct wsscreen_descr *sc_screens[1];
+	struct wsscreen_list sc_screenlist;
+	struct vcons_data vd;
+	int sc_mode;
+	uint8_t sc_cmap_red[256], sc_cmap_green[256], sc_cmap_blue[256];
+};
+
+static int	omapfb_match(device_t, cfdata_t, void *);
+static void	omapfb_attach(device_t, device_t, void *);
+
+CFATTACH_DECL_NEW(omapfb, sizeof(struct omapfb_softc),
+    omapfb_match, omapfb_attach, NULL, NULL);
+
+static int	omapfb_ioctl(void *, void *, u_long, void *, int,
+			     struct lwp *);
+static paddr_t	omapfb_mmap(void *, void *, off_t, int);
+static void	omapfb_init_screen(void *, struct vcons_screen *, int, long *);
+
+static void	omapfb_init(struct omapfb_softc *);
+
+static int	omapfb_putcmap(struct omapfb_softc *, struct wsdisplay_cmap *);
+static int 	omapfb_getcmap(struct omapfb_softc *, struct wsdisplay_cmap *);
+static void	omapfb_restore_palette(struct omapfb_softc *);
+static void 	omapfb_putpalreg(struct omapfb_softc *, int, uint8_t,
+			    uint8_t, uint8_t);
+
+#if 0
+static void	omapfb_flush_engine(struct omapfb_softc *);
+static void	omapfb_rectfill(struct omapfb_softc *, int, int, int, int,
+			    uint32_t);
+static void	omapfb_bitblt(struct omapfb_softc *, int, int, int, int, int,
+			    int, int);
+
+static void	omapfb_cursor(void *, int, int, int);
+static void	omapfb_putchar(void *, int, int, u_int, long);
+static void	omapfb_copycols(void *, int, int, int, int);
+static void	omapfb_erasecols(void *, int, int, int, long);
+static void	omapfb_copyrows(void *, int, int, int);
+static void	omapfb_eraserows(void *, int, int, long);
+#endif
+
+struct wsdisplay_accessops omapfb_accessops = {
+	omapfb_ioctl,
+	omapfb_mmap,
+	NULL,	/* alloc_screen */
+	NULL,	/* free_screen */
+	NULL,	/* show_screen */
+	NULL, 	/* load_font */
+	NULL,	/* pollc */
+	NULL	/* scroll */
+};
+
+uint32_t venc_mode_ntsc[] = {
+	0x00000000, 0x00000001, 0x00008040, 0x00000359,
+	0x0000020c, 0x00000000, 0x043f2631, 0x00000000,
+	0x00000102, 0x0000016c, 0x0000012f, 0x00000043,
+	0x00000038, 0x00000007, 0x00000001, 0x00000038,
+	0x21f07c1f, 0x00000000, 0x01310011, 0x0000f003,
+	0x00000000, 0x069300f4, 0x0016020c, 0x00060107,
+	0x008e0350, 0x000f0359, 0x01a00000, 0x020701a0,
+	0x01ac0024, 0x020d01ac, 0x00000006, 0x03480078,
+	0x02060024, 0x0001008a, 0x01ac0106, 0x01060006,
+	0x00140001, 0x00010001, 0x00f90000, 0x0000000d,
+	0x00000000};
+
+extern const u_char rasops_cmap[768];
+
+static int
+omapfb_match(device_t parent, cfdata_t match, void *aux)
+{
+	struct obio_attach_args *obio = aux;
+
+	if ((obio->obio_addr == -1) || (obio->obio_size == 0))
+		return 0;
+	return 1;
+}
+
+static void
+omapfb_attach(device_t parent, device_t self, void *aux)
+{
+	struct omapfb_softc	*sc = device_private(self);
+	struct obio_attach_args *obio = aux;
+	struct rasops_info	*ri;
+	struct wsemuldisplaydev_attach_args aa;
+	prop_dictionary_t	dict;
+	unsigned long		defattr;
+	bool			is_console;
+	uint32_t		sz, reg;
+	int			segs, i, j, adr;
+
+	sc->sc_iot = obio->obio_iot;
+	sc->sc_dev = self;
+	sc->sc_dmat = obio->obio_dmat;
+	
+	printf(": OMAP onboard video\n");
+	if (bus_space_map(obio->obio_iot, obio->obio_addr, obio->obio_size, 0,
+	    &sc->sc_regh)) {
+		aprint_error(": couldn't map register space\n");
+		return;
+	}
+
+	sz = bus_space_read_4(sc->sc_iot, sc->sc_regh, OMAPFB_DISPC_GFX_SIZE);
+	sc->sc_width = (sz & 0xfff) + 1;
+	sc->sc_height = ((sz & 0x0fff0000 ) >> 16) + 1;
+	sc->sc_depth = 16;
+	sc->sc_stride = sc->sc_width << 1;
+
+	printf("%s: firmware set up %d x %d\n", device_xname(self),
+	    sc->sc_width, sc->sc_height);
+#if 0
+	printf("DSS revision: %08x\n",
+	    bus_space_read_4(sc->sc_iot, sc->sc_regh, OMAPFB_DSS_REVISION));
+#endif	
+	dict = device_properties(self);
+	prop_dictionary_get_bool(dict, "is_console", &is_console);
+	is_console = 1;
+
+	/* setup video DMA */
+	sc->sc_vramsize = (12 << 20) + 0x1000; /* 12MB + CLUT */
+
+	if (bus_dmamem_alloc(sc->sc_dmat, sc->sc_vramsize, 0, 0,
+	    sc->sc_dmamem, 1, &segs, BUS_DMA_NOWAIT) != 0) {
+		panic("boo!\n");
+		aprint_error_dev(sc->sc_dev,
+		"failed to allocate video memory\n");
+		return;
+	}
+
+	if (bus_dmamem_map(sc->sc_dmat, sc->sc_dmamem, 1, sc->sc_vramsize, 
+	    &sc->sc_vramaddr, BUS_DMA_NOWAIT | BUS_DMA_COHERENT) != 0) {
+		aprint_error_dev(sc->sc_dev, "failed to map video RAM\n");
+		return;
+	}
+	sc->sc_fbaddr = (uint8_t *)sc->sc_vramaddr + 0x1000;
+	sc->sc_clut = sc->sc_vramaddr;
+
+	if (bus_dmamap_create(sc->sc_dmat, sc->sc_vramsize, 1, sc->sc_vramsize,
+	    0, BUS_DMA_NOWAIT, &sc->sc_dmamap) != 0) {
+		aprint_error_dev(sc->sc_dev, "failed to create DMA map\n");
+		return;
+	}
+
+	if (bus_dmamap_load(sc->sc_dmat, sc->sc_dmamap, sc->sc_vramaddr,
+	    sc->sc_vramsize, NULL, BUS_DMA_NOWAIT) != 0) {
+		aprint_error_dev(sc->sc_dev, "failed to load DMA map\n");
+		return;
+	}
+
+	if (sc->sc_depth == 8) {
+		j = 0;
+		for (i = 0; i < 256; i++) {
+			sc->sc_cmap_red[i] = rasops_cmap[j];
+			sc->sc_cmap_green[i] = rasops_cmap[j + 1];
+			sc->sc_cmap_blue[i] = rasops_cmap[j + 2];
+			j += 3;
+		}
+	} else {
+		for (i = 0; i < 256; i++) {
+			sc->sc_cmap_red[i] = i;
+			sc->sc_cmap_green[i] = i;
+			sc->sc_cmap_blue[i] = i;
+		}
+	}	
+	omapfb_restore_palette(sc);
+
+	/* now that we have video memory, stick it to the video controller */
+	
+	reg = bus_space_read_4(sc->sc_iot, sc->sc_regh, OMAPFB_DISPC_SYSCONFIG);
+	reg &= ~(OMAP_DISPC_SYSC_STANDBY_MASK | OMAP_DISPC_SYSC_IDLE_MASK);
+	reg |= OMAP_DISPC_SYSC_SMART_STANDBY | OMAP_DISPC_SYSC_SMART_IDLE |
+	       OMAP_DISPC_SYSC_WAKEUP_ENABLE | OMAP_SYSCONF_AUTOIDLE;
+	bus_space_write_4(sc->sc_iot, sc->sc_regh, OMAPFB_DISPC_SYSCONFIG, reg);
+
+	bus_space_write_4(sc->sc_iot, sc->sc_regh, OMAPFB_DSS_SYSCONFIG, 
+	    OMAP_SYSCONF_AUTOIDLE);
+	reg = bus_space_read_4(sc->sc_iot, sc->sc_regh, OMAPFB_DISPC_CONFIG);
+	reg = 0x8;
+	bus_space_write_4(sc->sc_iot, sc->sc_regh, OMAPFB_DISPC_CONFIG, reg);
+	
+	bus_space_write_4(sc->sc_iot, sc->sc_regh, OMAPFB_DISPC_GFX_BASE_0, 
+	    sc->sc_dmamem->ds_addr + 0x1000);
+	bus_space_write_4(sc->sc_iot, sc->sc_regh, OMAPFB_DISPC_GFX_TABLE_BASE, 
+	    sc->sc_dmamem->ds_addr);
+	bus_space_write_4(sc->sc_iot, sc->sc_regh, OMAPFB_DISPC_GFX_POSITION, 
+	    0);
+	bus_space_write_4(sc->sc_iot, sc->sc_regh, OMAPFB_DISPC_GFX_PRELOAD, 0x60);
+	bus_space_write_4(sc->sc_iot, sc->sc_regh, OMAPFB_DISPC_GFX_ATTRIBUTES, 
+	    OMAP_DISPC_ATTR_ENABLE |
+	    OMAP_DISPC_ATTR_BURST_16x32 |
+	    /*OMAP_DISPC_ATTR_8BIT*/OMAP_DISPC_ATTR_RGB16
+	    | OMAP_DISPC_ATTR_REPLICATION);
+#if 0
+	printf("dss_control: %08x\n", bus_space_read_4(sc->sc_iot, sc->sc_regh, OMAPFB_DSS_CONTROL));
+	bus_space_write_4(sc->sc_iot, sc->sc_regh, OMAPFB_DSS_CONTROL,
+	    /*OMAP_DSSCTRL_DISPC_CLK_SWITCH |*/
+	    OMAP_DSSCTRL_CLOCK_MODE |
+	    OMAP_DSSCTRL_VENC_CLOCK_4X |
+	    OMAP_DSSCTRL_DAC_DEMEN);
+#endif
+
+	/* VENC to NTSC mode */
+	adr = OMAPFB_VENC_F_CONTROL;
+#if 0
+	for (i = 0; i < __arraycount(venc_mode_ntsc); i++) {
+		bus_space_write_4(sc->sc_iot, sc->sc_regh, adr, 
+		    venc_mode_ntsc[i]);
+		adr += 4;
+	}
+	bus_space_write_4(sc->sc_iot, sc->sc_regh, OMAPFB_VENC_F_CONTROL, 
+		    venc_mode_ntsc[0]);
+	bus_space_write_4(sc->sc_iot, sc->sc_regh, OMAPFB_VENC_SYNC_CTRL, 
+		    venc_mode_ntsc[2]);
+		    
+	bus_space_write_4(sc->sc_iot, sc->sc_regh, OMAPFB_DISPC_DEFAULT_COLOR_1,
+	    0x00ff0000);
+#endif
+	reg = bus_space_read_4(sc->sc_iot, sc->sc_regh, OMAPFB_DISPC_CONTROL);
+	bus_space_write_4(sc->sc_iot, sc->sc_regh, OMAPFB_DISPC_CONTROL,
+	    reg | OMAP_DISPC_CTRL_GO_LCD);
+
+#ifdef OMAPFB_DEBUG
+	printf("attr: %08x\n", bus_space_read_4(sc->sc_iot, sc->sc_regh, OMAPFB_DISPC_GFX_ATTRIBUTES));
+	printf("preload: %08x\n", bus_space_read_4(sc->sc_iot, sc->sc_regh, OMAPFB_DISPC_GFX_PRELOAD));
+	printf("config: %08x\n", bus_space_read_4(sc->sc_iot, sc->sc_regh, OMAPFB_DISPC_CONFIG));
+	printf("control: %08x\n", bus_space_read_4(sc->sc_iot, sc->sc_regh, OMAPFB_DISPC_CONTROL));
+	printf("dss_control: %08x\n", bus_space_read_4(sc->sc_iot, sc->sc_regh, OMAPFB_DSS_CONTROL));
+	printf("threshold: %08x\n", bus_space_read_4(sc->sc_iot, sc->sc_regh, OMAPFB_DISPC_GFX_FIFO_THRESH));
+	printf("GFX size: %08x\n", bus_space_read_4(sc->sc_iot, sc->sc_regh, OMAPFB_DISPC_GFX_SIZE));
+	printf("row inc: %08x\n", bus_space_read_4(sc->sc_iot, sc->sc_regh, OMAPFB_DISPC_GFX_ROW_INC));
+	printf("pixel inc: %08x\n", bus_space_read_4(sc->sc_iot, sc->sc_regh, OMAPFB_DISPC_GFX_PIXEL_INC));
+#endif
+
+	sc->sc_defaultscreen_descr = (struct wsscreen_descr){
+		"default",
+		0, 0,
+		NULL,
+		8, 16,
+		WSSCREEN_WSCOLORS | WSSCREEN_HILIT,
+		NULL
+	};
+	sc->sc_screens[0] = &sc->sc_defaultscreen_descr;
+	sc->sc_screenlist = (struct wsscreen_list){1, sc->sc_screens};
+	sc->sc_mode = WSDISPLAYIO_MODE_EMUL;
+	sc->sc_locked = 0;
+
+	vcons_init(&sc->vd, sc, &sc->sc_defaultscreen_descr,
+	    &omapfb_accessops);
+	sc->vd.init_screen = omapfb_init_screen;
+
+	/* init engine here */
+	omapfb_init(sc);
+
+	ri = &sc->sc_console_screen.scr_ri;
+
+	if (is_console) {
+		vcons_init_screen(&sc->vd, &sc->sc_console_screen, 1,
+		    &defattr);
+		sc->sc_console_screen.scr_flags |= VCONS_SCREEN_IS_STATIC;
+
+#if 0
+		omapfb_rectfill(sc, 0, 0, sc->sc_width, sc->sc_height,
+		    ri->ri_devcmap[(defattr >> 16) & 0xff]);
+#endif
+		sc->sc_defaultscreen_descr.textops = &ri->ri_ops;
+		sc->sc_defaultscreen_descr.capabilities = ri->ri_caps;
+		sc->sc_defaultscreen_descr.nrows = ri->ri_rows;
+		sc->sc_defaultscreen_descr.ncols = ri->ri_cols;
+		wsdisplay_cnattach(&sc->sc_defaultscreen_descr, ri, 0, 0,
+		    defattr);
+		vcons_replay_msgbuf(&sc->sc_console_screen);
+	} else {
+		/*
+		 * since we're not the console we can postpone the rest
+		 * until someone actually allocates a screen for us
+		 */
+		(*ri->ri_ops.allocattr)(ri, 0, 0, 0, &defattr);
+	}
+
+	aa.console = is_console;
+	aa.scrdata = &sc->sc_screenlist;
+	aa.accessops = &omapfb_accessops;
+	aa.accesscookie = &sc->vd;
+
+	config_found(sc->sc_dev, &aa, wsemuldisplaydevprint);
+	
+}
+
+static int
+omapfb_ioctl(void *v, void *vs, u_long cmd, void *data, int flag,
+	struct lwp *l)
+{
+	struct vcons_data *vd = v;
+	struct omapfb_softc *sc = vd->cookie;
+	struct wsdisplay_fbinfo *wdf;
+	struct vcons_screen *ms = vd->active;
+
+	switch (cmd) {
+
+		case WSDISPLAYIO_GTYPE:
+			*(u_int *)data = WSDISPLAY_TYPE_PCIMISC;
+			return 0;
+
+		case WSDISPLAYIO_GINFO:
+			if (ms == NULL)
+				return ENODEV;
+			wdf = (void *)data;
+			wdf->height = ms->scr_ri.ri_height;
+			wdf->width = ms->scr_ri.ri_width;
+			wdf->depth = ms->scr_ri.ri_depth;
+			wdf->cmsize = 256;
+			return 0;
+
+		case WSDISPLAYIO_GETCMAP:
+			return omapfb_getcmap(sc,
+			    (struct wsdisplay_cmap *)data);
+
+		case WSDISPLAYIO_PUTCMAP:
+			return omapfb_putcmap(sc,
+			    (struct wsdisplay_cmap *)data);
+
+		case WSDISPLAYIO_LINEBYTES:
+			*(u_int *)data = sc->sc_stride;
+			return 0;
+
+		case WSDISPLAYIO_SMODE:
+			{
+				int new_mode = *(int*)data;
+
+				/* notify the bus backend */
+				if (new_mode != sc->sc_mode) {
+					sc->sc_mode = new_mode;
+					if(new_mode == WSDISPLAYIO_MODE_EMUL) {
+						vcons_redraw_screen(ms);
+					}
+				}
+			}
+			return 0;
+	}
+	return EPASSTHROUGH;
+}
+
+static paddr_t
+omapfb_mmap(void *v, void *vs, off_t offset, int prot)
+{
+	paddr_t pa = -1;
+#if 0
+	struct vcons_data *vd = v;
+	struct omapfb_softc *sc = vd->cookie;
+
+	/* 'regular' framebuffer mmap()ing */
+	if (offset < sc->sc_fbsize) {
+		pa = bus_space_mmap(sc->sc_memt, sc->sc_fb + offset, 0, prot,
+		    BUS_SPACE_MAP_LINEAR);
+		return pa;
+	}
+#endif
+	return pa;
+}
+
+static void
+omapfb_init_screen(void *cookie, struct vcons_screen *scr,
+    int existing, long *defattr)
+{
+	struct omapfb_softc *sc = cookie;
+	struct rasops_info *ri = &scr->scr_ri;
+
+	ri->ri_depth = sc->sc_depth;
+	ri->ri_width = sc->sc_width;
+	ri->ri_height = sc->sc_height;
+	ri->ri_stride = sc->sc_stride;
+	ri->ri_flg = RI_CENTER | RI_FULLCLEAR;
+
+	ri->ri_bits = (char *)sc->sc_fbaddr;
+
+	scr->scr_flags |= VCONS_DONT_READ;
+
+	if (existing) {
+		ri->ri_flg |= RI_CLEAR;
+	}
+
+	rasops_init(ri, sc->sc_height / 8, sc->sc_width / 8);
+	ri->ri_caps = WSSCREEN_WSCOLORS;
+
+	rasops_reconfig(ri, sc->sc_height / ri->ri_font->fontheight,
+		    sc->sc_width / ri->ri_font->fontwidth);
+
+	ri->ri_hw = scr;
+#if 0
+	ri->ri_ops.copyrows = omapfb_copyrows;
+	ri->ri_ops.copycols = omapfb_copycols;
+	ri->ri_ops.eraserows = omapfb_eraserows;
+	ri->ri_ops.erasecols = omapfb_erasecols;
+	ri->ri_ops.cursor = omapfb_cursor;
+	ri->ri_ops.putchar = omapfb_putchar;
+#endif
+}
+
+static int
+omapfb_putcmap(struct omapfb_softc *sc, struct wsdisplay_cmap *cm)
+{
+	u_char *r, *g, *b;
+	u_int index = cm->index;
+	u_int count = cm->count;
+	int i, error;
+	u_char rbuf[256], gbuf[256], bbuf[256];
+
+	if (cm->index >= 256 || cm->count > 256 ||
+	    (cm->index + cm->count) > 256)
+		return EINVAL;
+	error = copyin(cm->red, &rbuf[index], count);
+	if (error)
+		return error;
+	error = copyin(cm->green, &gbuf[index], count);
+	if (error)
+		return error;
+	error = copyin(cm->blue, &bbuf[index], count);
+	if (error)
+		return error;
+
+	memcpy(&sc->sc_cmap_red[index], &rbuf[index], count);
+	memcpy(&sc->sc_cmap_green[index], &gbuf[index], count);
+	memcpy(&sc->sc_cmap_blue[index], &bbuf[index], count);
+
+	r = &sc->sc_cmap_red[index];
+	g = &sc->sc_cmap_green[index];
+	b = &sc->sc_cmap_blue[index];
+
+	for (i = 0; i < count; i++) {
+		omapfb_putpalreg(sc, index, *r, *g, *b);
+		index++;
+		r++, g++, b++;
+	}
+	return 0;
+}
+
+static int
+omapfb_getcmap(struct omapfb_softc *sc, struct wsdisplay_cmap *cm)
+{
+	u_int index = cm->index;
+	u_int count = cm->count;
+	int error;
+
+	if (index >= 255 || count > 256 || index + count > 256)
+		return EINVAL;
+
+	error = copyout(&sc->sc_cmap_red[index],   cm->red,   count);
+	if (error)
+		return error;
+	error = copyout(&sc->sc_cmap_green[index], cm->green, count);
+	if (error)
+		return error;
+	error = copyout(&sc->sc_cmap_blue[index],  cm->blue,  count);
+	if (error)
+		return error;
+
+	return 0;
+}
+
+static void
+omapfb_restore_palette(struct omapfb_softc *sc)
+{
+	int i;
+
+	for (i = 0; i < (1 << sc->sc_depth); i++) {
+		omapfb_putpalreg(sc, i, sc->sc_cmap_red[i],
+		    sc->sc_cmap_green[i], sc->sc_cmap_blue[i]);
+	}
+}
+
+static void
+omapfb_putpalreg(struct omapfb_softc *sc, int idx, uint8_t r, uint8_t g,
+    uint8_t b)
+{
+	uint32_t reg;
+
+	if ((idx < 0) || (idx > 255))
+		return;
+	/* whack the DAC */
+	reg = (r << 16) | (g << 8) | b;
+	sc->sc_clut[idx] = reg;
+	
+}
+
+static void
+omapfb_init(struct omapfb_softc *sc)
+{
+}
+
+#if 0
+static void
+omapfb_rectfill(struct omapfb_softc *sc, int x, int y, int wi, int he,
+     uint32_t colour)
+{
+}
+
+static void
+omapfb_bitblt(struct omapfb_softc *sc, int xs, int ys, int xd, int yd,
+    int wi, int he, int rop)
+{
+}
+
+static void
+omapfb_cursor(void *cookie, int on, int row, int col)
+{
+	struct rasops_info *ri = cookie;
+	struct vcons_screen *scr = ri->ri_hw;
+	struct omapfb_softc *sc = scr->scr_cookie;
+	int x, y, wi, he;
+	
+	wi = ri->ri_font->fontwidth;
+	he = ri->ri_font->fontheight;
+	
+	if (sc->sc_mode == WSDISPLAYIO_MODE_EMUL) {
+		x = ri->ri_ccol * wi + ri->ri_xorigin;
+		y = ri->ri_crow * he + ri->ri_yorigin;
+		if (ri->ri_flg & RI_CURSOR) {
+			omapfb_bitblt(sc, x, y, x, y, wi, he, 3);
+			ri->ri_flg &= ~RI_CURSOR;
+		}
+		ri->ri_crow = row;
+		ri->ri_ccol = col;
+		if (on) {
+			x = ri->ri_ccol * wi + ri->ri_xorigin;
+			y = ri->ri_crow * he + ri->ri_yorigin;
+			omapfb_bitblt(sc, x, y, x, y, wi, he, 3);
+			ri->ri_flg |= RI_CURSOR;
+		}
+	} else {
+		scr->scr_ri.ri_crow = row;
+		scr->scr_ri.ri_ccol = col;
+		scr->scr_ri.ri_flg &= ~RI_CURSOR;
+	}
+
+}
+
+#if 0
+static void
+omapfb_putchar(void *cookie, int row, int col, u_int c, long attr)
+{
+}
+#endif
+
+static void
+omapfb_copycols(void *cookie, int row, int srccol, int dstcol, int ncols)
+{
+	struct rasops_info *ri = cookie;
+	struct vcons_screen *scr = ri->ri_hw;
+	struct omapfb_softc *sc = scr->scr_cookie;
+	int32_t xs, xd, y, width, height;
+	
+	if ((sc->sc_locked == 0) && (sc->sc_mode == WSDISPLAYIO_MODE_EMUL)) {
+		xs = ri->ri_xorigin + ri->ri_font->fontwidth * srccol;
+		xd = ri->ri_xorigin + ri->ri_font->fontwidth * dstcol;
+		y = ri->ri_yorigin + ri->ri_font->fontheight * row;
+		width = ri->ri_font->fontwidth * ncols;
+		height = ri->ri_font->fontheight;
+		omapfb_bitblt(sc, xs, y, xd, y, width, height, 12);
+	}
+}
+
+static void
+omapfb_erasecols(void *cookie, int row, int startcol, int ncols, long fillattr)
+{
+	struct rasops_info *ri = cookie;
+	struct vcons_screen *scr = ri->ri_hw;
+	struct omapfb_softc *sc = scr->scr_cookie;
+	int32_t x, y, width, height, fg, bg, ul;
+	
+	if ((sc->sc_locked == 0) && (sc->sc_mode == WSDISPLAYIO_MODE_EMUL)) {
+		x = ri->ri_xorigin + ri->ri_font->fontwidth * startcol;
+		y = ri->ri_yorigin + ri->ri_font->fontheight * row;
+		width = ri->ri_font->fontwidth * ncols;
+		height = ri->ri_font->fontheight;
+		rasops_unpack_attr(fillattr, &fg, &bg, &ul);
+
+		omapfb_rectfill(sc, x, y, width, height, ri->ri_devcmap[bg]);
+	}
+}
+
+static void
+omapfb_copyrows(void *cookie, int srcrow, int dstrow, int nrows)
+{
+	struct rasops_info *ri = cookie;
+	struct vcons_screen *scr = ri->ri_hw;
+	struct omapfb_softc *sc = scr->scr_cookie;
+	int32_t x, ys, yd, width, height;
+
+	if ((sc->sc_locked == 0) && (sc->sc_mode == WSDISPLAYIO_MODE_EMUL)) {
+		x = ri->ri_xorigin;
+		ys = ri->ri_yorigin + ri->ri_font->fontheight * srcrow;
+		yd = ri->ri_yorigin + ri->ri_font->fontheight * dstrow;
+		width = ri->ri_emuwidth;
+		height = ri->ri_font->fontheight*nrows;
+		omapfb_bitblt(sc, x, ys, x, yd, width, height, 12);
+	}
+}
+
+static void
+omapfb_eraserows(void *cookie, int row, int nrows, long fillattr)
+{
+	struct rasops_info *ri = cookie;
+	struct vcons_screen *scr = ri->ri_hw;
+	struct omapfb_softc *sc = scr->scr_cookie;
+	int32_t x, y, width, height, fg, bg, ul;
+	
+	if ((sc->sc_locked == 0) && (sc->sc_mode == WSDISPLAYIO_MODE_EMUL)) {
+		x = ri->ri_xorigin;
+		y = ri->ri_yorigin + ri->ri_font->fontheight * row;
+		width = ri->ri_emuwidth;
+		height = ri->ri_font->fontheight * nrows;
+		rasops_unpack_attr(fillattr, &fg, &bg, &ul);
+
+		omapfb_rectfill(sc, x, y, width, height, ri->ri_devcmap[bg]);
+	}
+}
+#endif
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/sys/arch/arm/omap/omapfbreg.h	Sat Oct 09 03:31:35 2010 +0000
@@ -0,0 +1,310 @@
+/*	$NetBSD: omapfbreg.h,v 1.1.2.2 2010/10/09 03:31:40 yamt Exp $ */
+
+/*-
+ * Copyright (c) 2010 Michael Lorenz
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>
+__KERNEL_RCSID(0, "$NetBSD: omapfbreg.h,v 1.1.2.2 2010/10/09 03:31:40 yamt Exp $");
+
+#ifndef OMAPFB_REG_H
+#define OMAPFB_REG_H
+
+#define OMAPFB_DSS_REVISION		0x0000
+#define OMAPFB_DSS_SYSCONFIG		0x0010
+#define OMAPFB_DSS_SYSSTATUS		0x0014
+#define OMAPFB_DSS_IRQSTATUS		0x0018
+#define OMAPFB_DSS_CONTROL		0x0040
+#define OMAPFB_DSS_SDI_CONTROL		0x0044
+#define OMAPFB_DSS_PLL_CONTROL		0x0048
+#define OMAPFB_DSS_SDI_STATUS		0x005c
+
+/* display controller */
+#define OMAPFB_DISPC_REVISION		0x0400
+#define OMAPFB_DISPC_SYSCONFIG		0x0410
+#define OMAPFB_DISPC_SYSSTATUS		0x0414
+#define OMAPFB_DISPC_IRQSTATUS		0x0418
+#define OMAPFB_DISPC_IRQENABLE		0x041c
+#define OMAPFB_DISPC_CONTROL		0x0440
+#define OMAPFB_DISPC_CONFIG		0x0444
+#define OMAPFB_DISPC_DEFAULT_COLOR_0	0x044c
+#define OMAPFB_DISPC_DEFAULT_COLOR_1	0x0450
+#define OMAPFB_DISPC_TRANS_COLOR_0	0x0454
+#define OMAPFB_DISPC_TRANS_COLOR_1	0x0458
+#define OMAPFB_DISPC_LINE_STATUS	0x045c
+#define OMAPFB_DISPC_LINE_NUMBER	0x0460
+#define OMAPFB_DISPC_TIMING_H		0x0464
+#define OMAPFB_DISPC_TIMING_V		0x0468
+#define OMAPFB_DISPC_POL_FREQ		0x046c
+#define OMAPFB_DISPC_DIVISOR		0x0470
+#define OMAPFB_DISPC_GLOBAL_ALPHA	0x0474
+#define OMAPFB_DISPC_SIZE_DIG		0x0478
+#define OMAPFB_DISPC_SIZE_LCD		0x047c
+#define OMAPFB_DISPC_GFX_BASE_0		0x0480
+#define OMAPFB_DISPC_GFX_BASE_1		0x0484
+#define OMAPFB_DISPC_GFX_POSITION	0x0488
+#define OMAPFB_DISPC_GFX_SIZE		0x048c
+#define OMAPFB_DISPC_GFX_ATTRIBUTES	0x04a0
+#define OMAPFB_DISPC_GFX_FIFO_THRESH	0x04a4
+#define OMAPFB_DISPC_GFX_FIFO_SZ_STATUS	0x04a8
+#define OMAPFB_DISPC_GFX_ROW_INC	0x04ac
+#define OMAPFB_DISPC_GFX_PIXEL_INC	0x04b0
+#define OMAPFB_DISPC_GFX_WINDOW_SKIP	0x04b4
+#define OMAPFB_DISPC_GFX_TABLE_BASE	0x04b8
+#define OMAPFB_DISPC_DATA_CYCLE_0	0x05d4
+#define OMAPFB_DISPC_DATA_CYCLE_1	0x05d8
+#define OMAPFB_DISPC_DATA_CYCLE_2	0x05dc
+#define OMAPFB_DISPC_CPR_COEFF_R	0x0620
+#define OMAPFB_DISPC_CPR_COEFF_G	0x0624
+#define OMAPFB_DISPC_CPR_COEFF_B	0x0628
+#define OMAPFB_DISPC_GFX_PRELOAD	0x062c
+
+/* VID1 */
+#define OMAPFB_DISPC_VID1_BASE0		0x04bc
+#define OMAPFB_DISPC_VID1_BASE1		0x04c0
+#define OMAPFB_DISPC_VID1_POSITION	0x04c4
+#define OMAPFB_DISPC_VID1_SIZE		0x04c8
+#define OMAPFB_DISPC_VID1_ATTRIBUTES	0x04cc
+#define OMAPFB_DISPC_VID1_FIFO_THRESH	0x04d0
+#define OMAPFB_DISPC_VID1_FIFO_SZ_STAT	0x04d4
+#define OMAPFB_DISPC_VID1_ROW_INC	0x04d8
+#define OMAPFB_DISPC_VID1_PIXEL_INC	0x04dc
+#define OMAPFB_DISPC_VID1_FIR		0x04e0
+#define OMAPFB_DISPC_VID1_PICTURE_SIZE	0x04e4
+#define OMAPFB_DISPC_VID1_ACCU_0	0x04e8
+#define OMAPFB_DISPC_VID1_ACCU_1	0x04ec
+#define OMAPFB_DISPC_VID1_COEFF_H_0	0x04d0
+#define OMAPFB_DISPC_VID1_COEFF_HV_0	0x04d4
+#define OMAPFB_DISPC_VID1_COEFF_H_1	0x04d8
+#define OMAPFB_DISPC_VID1_COEFF_HV_1	0x04dc
+#define OMAPFB_DISPC_VID1_COEFF_H_2	0x04e0
+#define OMAPFB_DISPC_VID1_COEFF_HV_2	0x04e4
+#define OMAPFB_DISPC_VID1_COEFF_H_3	0x04e8
+#define OMAPFB_DISPC_VID1_COEFF_HV_3	0x04ec
+#define OMAPFB_DISPC_VID1_COEFF_H_4	0x04f0
+#define OMAPFB_DISPC_VID1_COEFF_HV_4	0x04f4
+#define OMAPFB_DISPC_VID1_COEFF_H_5	0x04f8
+#define OMAPFB_DISPC_VID1_COEFF_HV_5	0x04fc
+#define OMAPFB_DISPC_VID1_COEFF_H_6	0x0500
+#define OMAPFB_DISPC_VID1_COEFF_HV_6	0x0504
+#define OMAPFB_DISPC_VID1_COEFF_H_7	0x0508
+#define OMAPFB_DISPC_VID1_COEFF_HV_7	0x050c
+#define OMAPFB_DISPC_VID1_CONV_COEFF_0	0x0530
+#define OMAPFB_DISPC_VID1_CONV_COEFF_1	0x0534
+#define OMAPFB_DISPC_VID1_CONV_COEFF_2	0x0538
+#define OMAPFB_DISPC_VID1_CONV_COEFF_3	0x053c
+#define OMAPFB_DISPC_VID1_CONV_COEFF_4	0x0540
+#define OMAPFB_DISPC_VID1_FIR_COEFF_V0	0x05e0
+#define OMAPFB_DISPC_VID1_FIR_COEFF_V1	0x05e4
+#define OMAPFB_DISPC_VID1_FIR_COEFF_V2	0x05e8
+#define OMAPFB_DISPC_VID1_FIR_COEFF_V3	0x05ec
+#define OMAPFB_DISPC_VID1_FIR_COEFF_V4	0x05f0
+#define OMAPFB_DISPC_VID1_FIR_COEFF_V5	0x05f4
+#define OMAPFB_DISPC_VID1_FIR_COEFF_V6	0x05f8
+#define OMAPFB_DISPC_VID1_FIR_COEFF_V7	0x05fc
+#define OMAPFB_DISPC_VID1_PRELOAD	0x0630
+
+/* VID2 */
+#define OMAPFB_DISPC_VID2_BASE0		0x054c
+#define OMAPFB_DISPC_VID2_BASE1		0x0550
+#define OMAPFB_DISPC_VID2_POSITION	0x0554
+#define OMAPFB_DISPC_VID2_SIZE		0x0558
+#define OMAPFB_DISPC_VID2_ATTRIBUTES	0x055c
+#define OMAPFB_DISPC_VID2_FIFO_THRESH	0x0560
+#define OMAPFB_DISPC_VID2_FIFO_SZ_STAT	0x0564
+#define OMAPFB_DISPC_VID2_ROW_INC	0x0568
+#define OMAPFB_DISPC_VID2_PIXEL_INC	0x056c
+#define OMAPFB_DISPC_VID2_FIR		0x0570
+#define OMAPFB_DISPC_VID2_PICTURE_SIZE	0x0574
+#define OMAPFB_DISPC_VID2_ACCU_0	0x0578
+#define OMAPFB_DISPC_VID2_ACCU_1	0x057c
+#define OMAPFB_DISPC_VID2_COEFF_H_0	0x0580
+#define OMAPFB_DISPC_VID2_COEFF_HV_0	0x0584
+#define OMAPFB_DISPC_VID2_COEFF_H_1	0x0588
+#define OMAPFB_DISPC_VID2_COEFF_HV_1	0x058c
+#define OMAPFB_DISPC_VID2_COEFF_H_2	0x0590
+#define OMAPFB_DISPC_VID2_COEFF_HV_2	0x0594
+#define OMAPFB_DISPC_VID2_COEFF_H_3	0x0598
+#define OMAPFB_DISPC_VID2_COEFF_HV_3	0x059c
+#define OMAPFB_DISPC_VID2_COEFF_H_4	0x05a0
+#define OMAPFB_DISPC_VID2_COEFF_HV_4	0x05a4
+#define OMAPFB_DISPC_VID2_COEFF_H_5	0x05a8
+#define OMAPFB_DISPC_VID2_COEFF_HV_5	0x05ac
+#define OMAPFB_DISPC_VID2_COEFF_H_6	0x05b0
+#define OMAPFB_DISPC_VID2_COEFF_HV_6	0x05b4
+#define OMAPFB_DISPC_VID2_COEFF_H_7	0x05b8
+#define OMAPFB_DISPC_VID2_COEFF_HV_7	0x05bc
+#define OMAPFB_DISPC_VID2_CONV_COEFF_0	0x05c0
+#define OMAPFB_DISPC_VID2_CONV_COEFF_1	0x05c4
+#define OMAPFB_DISPC_VID2_CONV_COEFF_2	0x05c8
+#define OMAPFB_DISPC_VID2_CONV_COEFF_3	0x05cc
+#define OMAPFB_DISPC_VID2_CONV_COEFF_4	0x05d0
+#define OMAPFB_DISPC_VID2_FIR_COEFF_V0	0x0670
+#define OMAPFB_DISPC_VID2_FIR_COEFF_V1	0x0674
+#define OMAPFB_DISPC_VID2_FIR_COEFF_V2	0x0678
+#define OMAPFB_DISPC_VID2_FIR_COEFF_V3	0x067c
+#define OMAPFB_DISPC_VID2_FIR_COEFF_V4	0x0680
+#define OMAPFB_DISPC_VID2_FIR_COEFF_V5	0x0684
+#define OMAPFB_DISPC_VID2_FIR_COEFF_V6	0x0688
+#define OMAPFB_DISPC_VID2_FIR_COEFF_V7	0x068c
+#define OMAPFB_DISPC_VID2_PRELOAD	0x0634
+
+/* video encoder */
+#define OMAPFB_VENC_REV_ID		0x0c00
+#define OMAPFB_VENC_STATUS		0x0c04
+#define OMAPFB_VENC_F_CONTROL		0x0c08
+#define OMAPFB_VENC_VIDOUT_CTRL		0x0c10
+#define OMAPFB_VENC_SYNC_CTRL		0x0c14
+#define OMAPFB_VENC_LLEN		0x0c1c
+#define OMAPFB_VENC_FLENS		0x0c20
+#define OMAPFB_VENC_HFLTR_CTRL		0x0c24
+#define OMAPFB_VENC_CC_CARR_WSS_CARR	0x0c28
+#define OMAPFB_VENC_C_PHASE		0x0c2c
+#define OMAPFB_VENC_GAIN_U		0x0c30
+#define OMAPFB_VENC_GAIN_V		0x0c34
+#define OMAPFB_VENC_GAIN_Y		0x0c38
+#define OMAPFB_VENC_BLACK_LEVEL		0x0c3c
+#define OMAPFB_VENC_BLANK_LEVEL		0x0c40
+#define OMAPFB_VENC_X_COLOR		0x0c44
+#define OMAPFB_VENC_M_CONTROL		0x0c48
+#define OMAPFB_VENC_BSTAMP_WSS_DATA	0x0c4c
+#define OMAPFB_VENC_S_CARR		0x0c50
+#define OMAPFB_VENC_LINE21		0x0c54
+#define OMAPFB_VENC_LN_SEL		0x0c58
+#define OMAPFB_VENC_L21_WC_CTL		0x0c5c
+#define OMAPFB_VENC_HTRIGGER_VTRIGGER	0x0c60
+#define OMAPFB_VENC_SAVID_EAVID		0x0c64
+#define OMAPFB_VENC_FLEN_FAL		0x0c68
+#define OMAPFB_VENC_LAL_PHASE_RESET	0x0c6c
+#define OMAPFB_VENC_HS_INT_START_STOP_X	0x0c70
+#define OMAPFB_VENC_HS_EXT_START_STOP_X	0x0c74
+#define OMAPFB_VENC_VS_INT_START	0x0c78
+#define OMAPFB_VENC_VS_INT_STOP_X_VS_INT_START_Y	0x0c7c
+#define OMAPFB_VENC_VS_INT_STOP_Y_VS_EXT_START_X	0x0c80
+#define OMAPFB_VENC_VS_EXT_STOP_X_VS_EXT_START_Y	0x0c84
+#define OMAPFB_VENC_VS_EXT_STOP_Y	0x0c88
+#define OMAPFB_VENC_AVID_START_STOP_X	0x0c90
+#define OMAPFB_VENC_AVID_START_STOP_Y	0x0c94
+#define OMAPFB_VENC_FID_START_X_FID_START_Y		0x0ca0
+#define OMAPFB_VENC_FID_INT_OFFSET_Y_FID_EXT_START_X	0x0ca4
+#define OMAPFB_VENC_FID_EXT_START_Y_FID_EXT_OFFSET_Y	0x0ca8
+#define OMAPFB_VENC_TVDETGP_INT_START_STOP_X		0x0cb0
+#define OMAPFB_VENC_TVDETGP_INT_START_STOP_Y		0x0cb4
+#define OMAPFB_VENC_GEN_CTRL		0x0cb8
+#define OMAPFB_VENC_OUTPUT_CONTROL	0x0cc4
+#define OMAPFB_VENC_OUTPUT_TEST		0x0cc8
+
+/* revision registers */
+#define OMAP_REVISION_MINOR_MASK	0x0000000f
+#define OMAP_REVISION_MAJOR_MASK	0x000000f0
+
+/* sysconfig registers */
+#define OMAP_SYSCONF_AUTOIDLE		0x00000001
+#define OMAP_SYSCONF_SOFTRESET		0x00000002
+
+/* sysstatus registers */
+#define OMAP_SYSSTAT_RESET_DONE		0x00000001
+
+/* OMAPFB_DSS_IRQSTATUS */
+#define OMAP_DSSIRQ_DISPC		0x00000001
+#define OMAP_DSSIRQ_DSI			0x00000002
+
+/* OMAPFB_DSS_CONTROL */
+#define OMAP_DSSCTRL_VENC_SVIDEO	0x00000040 /* composite otherwise */
+#define OMAP_DSSCTRL_POWERDN_BGZ	0x00000020 /* power-down band gap up */
+#define OMAP_DSSCTRL_DAC_DEMEN		0x00000010 /* dynamic element match */
+#define OMAP_DSSCTRL_VENC_CLOCK_4X	0x00000008
+#define OMAP_DSSCTRL_CLOCK_MODE		0x00000004
+#define OMAP_DSSCTRL_DSI_CLK_SWITCH	0x00000002 /* use DSI PLL */
+#define OMAP_DSSCTRL_DISPC_CLK_SWITCH	0x00000001 /* use DSI PLL */
+
+/* additional bits in OMAPFB_DISPC_SYSCONFIG */
+#define OMAP_DISPC_SYSC_FORCE_STANDBY	0x00000000
+#define OMAP_DISPC_SYSC_NO_STANDBY	0x00001000
+#define OMAP_DISPC_SYSC_SMART_STANDBY	0x00002000
+#define OMAP_DISPC_SYSC_STANDBY_MASK	0x00003000
+#define OMAP_DISPC_SYSC_CLOCKS_OFF	0x00000000
+#define OMAP_DISPC_SYSC_FCLOCK_OFF	0x00000100
+#define OMAP_DISPC_SYSC_ICLOCK_OFF	0x00000200
+#define OMAP_DISPC_SYSC_CLOCK_ON	0x00000300
+#define OMAP_DISPC_SYSC_CLOCK_MASK	0x00000300
+#define OMAP_DISPC_SYSC_FORCE_IDLE	0x00000000
+#define OMAP_DISPC_SYSC_NO_IDLE		0x00000008
+#define OMAP_DISPC_SYSC_SMART_IDLE	0x00000010
+#define OMAP_DISPC_SYSC_IDLE_MASK	0x00000018
+#define OMAP_DISPC_SYSC_WAKEUP_ENABLE	0x00000004
+
+/* OMAPFB_DISPC_GFX_ATTRIBUTES */
+#define OMAP_DISPC_ATTR_REFRESH_FIFO	0x00008000 /* refresh from FIFO only */
+#define OMAP_DISPC_ATTR_PRIORITY_HIGH	0x00004000
+#define OMAP_DISPC_ATTR_ROT_NONE	0x00000000
+#define OMAP_DISPC_ATTR_ROT_90		0x00001000 /* for 24bit packed only */
+#define OMAP_DISPC_ATTR_ROT_180		0x00002000
+#define OMAP_DISPC_ATTR_ROT_270		0x00003000
+#define OMAP_DISPC_ATTR_FIFO_PRELOAD	0x00000800 /* use threshold for FIFO */
+#define OMAP_DISPC_ATTR_BIG_ENDIAN	0x00000400 /* little endian otherwise */
+#define OMAP_DISPC_ATTR_NIBBLE		0x00000200 /* for < 8 bit only */
+#define OMAP_DISPC_ATTR_24BIT_OUT	0x00000100 /* LCD otherwise */
+#define OMAP_DISPC_ATTR_BURST_4x32	0x00000000
+#define OMAP_DISPC_ATTR_BURST_8x32	0x00000040
+#define OMAP_DISPC_ATTR_BURST_16x32	0x00000080
+#define OMAP_DISPC_ATTR_REPLICATION	0x00000020
+#define OMAP_DISPC_ATTR_8BIT		0x00000006
+#define OMAP_DISPC_ATTR_RGB12		0x00000008
+#define OMAP_DISPC_ATTR_ARGB16		0x0000000a
+#define OMAP_DISPC_ATTR_RGB16		0x0000000c
+#define OMAP_DISPC_ATTR_RGB24		0x00000010 /* 32bit pixels */
+#define OMAP_DISPC_ATTR_RGB24P		0x00000012 /* 24bit packed */
+#define OMAP_DISPC_ATTR_ARGB32		0x00000018
+#define OMAP_DISPC_ATTR_RGBA32		0x0000001a
+#define OMAP_DISPC_ATTR_RGBX		0x0000001c
+#define OMAP_DISPC_ATTR_ENABLE		0x00000001
+
+/* OMAPFB_DISPC_CONTROL */
+#define OMAP_DISPC_CTRL_LCD_ACTIVE_HIGH	0x20000000
+#define OMAP_DISPC_CTRL_LCD_SIGNAL	0x10000000
+#define OMAP_DISPC_CTRL_PIXEL_CLOCK	0x08000000
+#define OMAP_DISPC_CTRL_GO_DIGITAL	0x00000040
+#define OMAP_DISPC_CTRL_GO_LCD		0x00000020
+#define OMAP_DISPC_CTRL_MONO		0x00000004
+#define OMAP_DISPC_CTRL_DIGITAL_ENABLE	0x00000002
+#define OMAP_DISPC_CTRL_LCD_ENABLE	0x00000001
+
+/* OMAPFB_VENC_F_CONTROL */
+#define OMAP_VENCFCTL_RESET		0x00000100
+#define OMAP_VENCFCTL_VID_EXTERNAL	0x00000000
+#define OMAP_VENCFCTL_VID_COLOR_BAR	0x00000040
+#define OMAP_VENCFCTL_VID_BACKGROUND	0x00000080
+#define OMAP_VENCFCTL_RGBF		0x00000020
+#define OMAP_VENCFCTL_BG_COLOR_MASK	0x0000001c
+#define OMAP_VENCFCTL_FMT_444RGB	0x00000000
+#define OMAP_VENCFCTL_FMT_444		0x00000001
+#define OMAP_VENCFCTL_FMT_422		0x00000002
+#define OMAP_VENCFCTL_FMT_ITU_422	0x00000003
+
+/* OMAPFB_DISPC_CONFIG */
+#define OMAP_DISPC_CFG_FUNCGATED	0x00000200	/* functional clocks */
+
+#endif /* OMAPFB_REG_H */
--- a/sys/arch/arm/pic/pic.c	Sun Sep 26 03:58:54 2010 +0000
+++ b/sys/arch/arm/pic/pic.c	Sat Oct 09 03:31:35 2010 +0000
@@ -1,4 +1,4 @@
-/*	$NetBSD: pic.c,v 1.1.24.2 2009/05/04 08:10:44 yamt Exp $	*/
+/*	$NetBSD: pic.c,v 1.1.24.3 2010/10/09 03:31:41 yamt Exp $	*/
 /*-
  * Copyright (c) 2008 The NetBSD Foundation, Inc.
  * All rights reserved.
@@ -28,7 +28,7 @@
  * POSSIBILITY OF SUCH DAMAGE.
  */
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: pic.c,v 1.1.24.2 2009/05/04 08:10:44 yamt Exp $");
+__KERNEL_RCSID(0, "$NetBSD: pic.c,v 1.1.24.3 2010/10/09 03:31:41 yamt Exp $");
 
 #define _INTR_PRIVATE
 #include <sys/param.h>
@@ -193,6 +193,7 @@
 	size_t irq_base;
 #if PIC_MAXSOURCES > 32
 	size_t irq_count;
+	int poi = 0;		/* Possibility of interrupting */
 #endif
 	uint32_t pending_irqs;
 	uint32_t blocked_irqs;
@@ -214,14 +215,20 @@
 		if (pending_irqs == 0) {
 #if PIC_MAXSOURCES > 32
 			irq_count += 32;
-			if (__predict_true(irq_count >= pic->pic_maxsources))
-				break;
-			irq_base += 32;
-			ipending++;
-			iblocked++;
-			if (irq_base >= pic->pic_maxsources) {
+			if (__predict_true(irq_count >= pic->pic_maxsources)) {
+				if (!poi)
+					/*Interrupt at this level was handled.*/
+					break;
+				irq_base = 0;
+				irq_count = 0;
+				poi = 0;
 				ipending = pic->pic_pending_irqs;
 				iblocked = pic->pic_blocked_irqs;
+			} else {
+				irq_base += 32;
+				ipending++;
+				iblocked++;
+				KASSERT(irq_base <= pic->pic_maxsources);
 			}
 			continue;
 #else
@@ -229,7 +236,7 @@
 #endif
 		}
 		progress = true;
-		blocked_irqs = pending_irqs;
+		blocked_irqs = 0;
 		do {
 			irq = ffs(pending_irqs) - 1;
 			KASSERT(irq >= 0);
@@ -240,9 +247,16 @@
 				cpsie(I32_bit);
 				pic_dispatch(is, frame);
 				cpsid(I32_bit);
+#if PIC_MAXSOURCES > 32
+				/*
+				 * There is a possibility of interrupting
+				 * from cpsie() to cpsid().
+				 */
+				poi = 1;
+#endif
+				blocked_irqs |= __BIT(irq);
 			} else {
 				KASSERT(0);
-				blocked_irqs &= ~__BIT(irq);
 			}
 			pending_irqs = pic_find_pending_irqs_by_ipl(pic,
 			    irq_base, *ipending, ipl);
--- a/sys/arch/arm/sa11x0/sa11x0_com.c	Sun Sep 26 03:58:54 2010 +0000
+++ b/sys/arch/arm/sa11x0/sa11x0_com.c	Sat Oct 09 03:31:35 2010 +0000
@@ -1,4 +1,4 @@
-/*      $NetBSD: sa11x0_com.c,v 1.42.10.4 2010/03/11 15:02:07 yamt Exp $        */
+/*      $NetBSD: sa11x0_com.c,v 1.42.10.5 2010/10/09 03:31:41 yamt Exp $        */
 
 /*-
  * Copyright (c) 1998, 1999, 2001 The NetBSD Foundation, Inc.
@@ -64,7 +64,7 @@
  */
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: sa11x0_com.c,v 1.42.10.4 2010/03/11 15:02:07 yamt Exp $");
+__KERNEL_RCSID(0, "$NetBSD: sa11x0_com.c,v 1.42.10.5 2010/10/09 03:31:41 yamt Exp $");
 
 #include "opt_com.h"
 #include "opt_ddb.h"
@@ -159,7 +159,7 @@
 
 #ifdef hpcarm
 /* HPCARM specific functions */
-static void	sacom_j720_init(struct sa11x0_softc *, struct sacom_softc *);
+static void	sacom_j720_init(device_t, device_t);
 #endif
 
 #define COMUNIT_MASK	0x7ffff
@@ -234,7 +234,7 @@
 
 #ifdef hpcarm
 	struct platid_data *p;
-	void (*mdinit)(device_t, struct sacom_softc *);
+	void (*mdinit)(device_t, device_t);
 #endif
 
 	aprint_normal("\n");
@@ -270,7 +270,7 @@
 	/* Do hpcarm specific initialization, if any */
 	if ((p = platid_search_data(&platid, sacom_platid_table)) != NULL) {
 		mdinit = p->data;
-		(mdinit)(parent, sc);
+		(*mdinit)(parent, self);
 	}
 #endif
 
@@ -1400,12 +1400,16 @@
 }
 
 static void
-sacom_j720_init(struct sa11x0_softc *parent, struct sacom_softc *sc) {
+sacom_j720_init(device_t parent, device_t self)
+{
+	struct sa11x0_softc *sasc;
+
+	sasc = device_private(parent);
 
 	/* XXX  this should be done at sc->enable function */
-	bus_space_write_4(parent->sc_iot, parent->sc_gpioh,
+	bus_space_write_4(sasc->sc_iot, sasc->sc_gpioh,
 	    SAGPIO_PCR, 0xa0000);
-	bus_space_write_4(parent->sc_iot, parent->sc_gpioh,
+	bus_space_write_4(sasc->sc_iot, sasc->sc_gpioh,
 	    SAGPIO_PSR, 0x100);
 }
 
--- a/sys/arch/arm/xscale/pxa2x0_mci.c	Sun Sep 26 03:58:54 2010 +0000
+++ b/sys/arch/arm/xscale/pxa2x0_mci.c	Sat Oct 09 03:31:35 2010 +0000
@@ -1,4 +1,4 @@
-/*	$NetBSD: pxa2x0_mci.c,v 1.1.4.5 2010/08/11 22:51:42 yamt Exp $	*/
+/*	$NetBSD: pxa2x0_mci.c,v 1.1.4.6 2010/10/09 03:31:41 yamt Exp $	*/
 /*	$OpenBSD: pxa2x0_mmc.c,v 1.5 2009/02/23 18:09:55 miod Exp $	*/
 
 /*
@@ -54,7 +54,7 @@
  */
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: pxa2x0_mci.c,v 1.1.4.5 2010/08/11 22:51:42 yamt Exp $");
+__KERNEL_RCSID(0, "$NetBSD: pxa2x0_mci.c,v 1.1.4.6 2010/10/09 03:31:41 yamt Exp $");
 
 #include <sys/param.h>
 #include <sys/device.h>
@@ -101,6 +101,7 @@
 static int	pxamci_bus_power(sdmmc_chipset_handle_t, uint32_t);
 static int	pxamci_bus_clock(sdmmc_chipset_handle_t, int);
 static int	pxamci_bus_width(sdmmc_chipset_handle_t, int);
+static int	pxamci_bus_rod(sdmmc_chipset_handle_t, int);
 static void	pxamci_exec_command(sdmmc_chipset_handle_t,
 		    struct sdmmc_command *);
 static void	pxamci_card_enable_intr(sdmmc_chipset_handle_t, int);
@@ -124,6 +125,7 @@
 	.bus_power		= pxamci_bus_power,
 	.bus_clock		= pxamci_bus_clock,
 	.bus_width		= pxamci_bus_width,
+	.bus_rod		= pxamci_bus_rod,
 
 	/* command execution */
 	.exec_command		= pxamci_exec_command,
@@ -305,7 +307,7 @@
 	saa.saa_clkmax = sc->sc_clkmax;
 	saa.saa_caps = 0;
 	if (!ISSET(sc->sc_caps, PMC_CAPS_NO_DMA))
-		SET(saa.saa_caps, SMC_CAPS_DMA);
+		SET(saa.saa_caps, SMC_CAPS_DMA | SMC_CAPS_MULTI_SEG_DMA);
 	if (CPU_IS_PXA270 && ISSET(sc->sc_caps, PMC_CAPS_4BIT))
 		SET(saa.saa_caps, SMC_CAPS_4BIT_MODE);
 
@@ -548,6 +550,14 @@
 	return rv;
 }
 
+static int
+pxamci_bus_rod(sdmmc_chipset_handle_t sch, int on)
+{
+
+	/* not support */
+	return -1;
+}
+
 static void
 pxamci_exec_command(sdmmc_chipset_handle_t sch, struct sdmmc_command *cmd)
 {
--- a/sys/arch/atari/conf/std.atari	Sun Sep 26 03:58:54 2010 +0000
+++ b/sys/arch/atari/conf/std.atari	Sat Oct 09 03:31:35 2010 +0000
@@ -1,15 +1,13 @@
-#	$NetBSD: std.atari,v 1.24 2005/12/11 12:16:54 christos Exp $
+#	$NetBSD: std.atari,v 1.24.78.1 2010/10/09 03:31:41 yamt Exp $
 #
 # standard atari information
 #
 machine		atari m68k
-include		"conf/std"	# MI standard options
+include		"conf/std"			# MI standard options
+include		"arch/m68k/conf/std.m68k"	# m68k standard options
 
 options 	_ATARIHW_		# Original Atari like mainboard hw.
 
-options 	EXEC_SCRIPT		# Support #!
-options 	EXEC_ELF32		# 32-bit ELF executables
-
 mainbus0	at root
 
 clock0		at mainbus0		# system clock
--- a/sys/arch/atari/conf/std.hades	Sun Sep 26 03:58:54 2010 +0000
+++ b/sys/arch/atari/conf/std.hades	Sat Oct 09 03:31:35 2010 +0000
@@ -1,15 +1,13 @@
-#	$NetBSD: std.hades,v 1.6 2005/12/11 12:16:54 christos Exp $
+#	$NetBSD: std.hades,v 1.6.78.1 2010/10/09 03:31:41 yamt Exp $
 #
 # standard Hades information
 #
 machine		atari m68k
-include		"conf/std"	# MI standard options
+include		"conf/std"			# MI standard options
+include		"arch/m68k/conf/std.m68k"	# m68k standard options
 
 options 	_ATARIHW_		# Original Atari like mainboard hw.
 
-options 	EXEC_SCRIPT		# Support #!
-options 	EXEC_ELF32		# 32-bit ELF executables
-
 mainbus0	at root
 
 clock0		at mainbus0		# system clock
--- a/sys/arch/atari/conf/std.milan	Sun Sep 26 03:58:54 2010 +0000
+++ b/sys/arch/atari/conf/std.milan	Sat Oct 09 03:31:35 2010 +0000
@@ -1,15 +1,13 @@
-#	$NetBSD: std.milan,v 1.5 2005/12/11 12:16:54 christos Exp $
+#	$NetBSD: std.milan,v 1.5.78.1 2010/10/09 03:31:41 yamt Exp $
 #
 # standard atari information
 #
 machine		atari m68k
-include		"conf/std"	# MI standard options
+include		"conf/std"			# MI standard options
+include		"arch/m68k/conf/std.m68k"	# m68k standard options
 
 options 	_MILANHW_
 
-options 	EXEC_SCRIPT		# Support #!
-options 	EXEC_ELF32		# 32-bit ELF executables
-
 mainbus0	at root
 
 clock0		at mainbus0		# system clock
--- a/sys/arch/atari/stand/tostools/libtos/exec_elf.h	Sun Sep 26 03:58:54 2010 +0000
+++ b/sys/arch/atari/stand/tostools/libtos/exec_elf.h	Sat Oct 09 03:31:35 2010 +0000
@@ -1,4 +1,4 @@
-/*	$NetBSD: exec_elf.h,v 1.4.78.1 2008/05/16 02:22:06 yamt Exp $	*/
+/*	$NetBSD: exec_elf.h,v 1.4.78.2 2010/10/09 03:31:42 yamt Exp $	*/
 
 /*-
  * Copyright (c) 1994 The NetBSD Foundation, Inc.
@@ -95,10 +95,8 @@
 #define	ELF64_FSZ_XWORD	8
 typedef	__uint64_t	Elf64_Xword;
 #define	ELF64_FSZ_XWORD	8
-typedef	__uint32_t	Elf64_Half;
-#define	ELF64_FSZ_HALF	4
-typedef	__uint16_t	Elf64_Quarter;
-#define	ELF64_FSZ_QUARTER 2
+typedef	__uint16_t	Elf64_Half;
+#define	ELF64_FSZ_HALF 2
 
 /*
  * ELF Header
--- a/sys/arch/cesfic/conf/std.cesfic	Sun Sep 26 03:58:54 2010 +0000
+++ b/sys/arch/cesfic/conf/std.cesfic	Sat Oct 09 03:31:35 2010 +0000
@@ -1,11 +1,10 @@
-#	$NetBSD: std.cesfic,v 1.4 2005/12/11 12:17:05 christos Exp $
+#	$NetBSD: std.cesfic,v 1.4.78.1 2010/10/09 03:31:42 yamt Exp $
 #
 # Options/devices that all cesfics should have
 #
 
 machine cesfic m68k
-include		"conf/std"	# MI standard options
+include		"conf/std"			# MI standard options
+include		"arch/m68k/conf/std.m68k"	# m68k standard options
 
-options 	EXEC_ELF32
 options 	EXEC_AOUT	# support for exec'ing a.out
-options 	EXEC_SCRIPT	# support for #! scripts
--- a/sys/arch/dreamcast/conf/GENERIC	Sun Sep 26 03:58:54 2010 +0000
+++ b/sys/arch/dreamcast/conf/GENERIC	Sat Oct 09 03:31:35 2010 +0000
@@ -1,4 +1,4 @@
-# $NetBSD: GENERIC,v 1.82.10.5 2010/08/11 22:51:49 yamt Exp $
+# $NetBSD: GENERIC,v 1.82.10.6 2010/10/09 03:31:42 yamt Exp $
 #
 # GENERIC machine description file
 # 
@@ -50,7 +50,7 @@
 #options 	KGDB			# remote debugger
 #options 	"KGDB_DEVNAME=\"scif\"",KGDB_DEVRATE=57600
 #makeoptions	DEBUG="-g"	# compile full symbol table
-options 	SYMTAB_SPACE=308000
+options 	SYMTAB_SPACE=310000
 #options 	SYSCALL_DEBUG
 #options 	UVMHIST
 #options 	UVMHIST_PRINT
--- a/sys/arch/dreamcast/conf/Makefile.dreamcast.inc	Sun Sep 26 03:58:54 2010 +0000
+++ b/sys/arch/dreamcast/conf/Makefile.dreamcast.inc	Sat Oct 09 03:31:35 2010 +0000
@@ -1,6 +1,11 @@
-#	$NetBSD: Makefile.dreamcast.inc,v 1.9.78.1 2010/08/11 22:51:49 yamt Exp $
+#	$NetBSD: Makefile.dreamcast.inc,v 1.9.78.2 2010/10/09 03:31:42 yamt Exp $
 
 MACHINE_ARCH=sh3el
 
 TEXTADDR?=8c010000
 LINKFORMAT=	-N
+
+SYSTEM_LD_TAIL_EXTRA+=;							\
+	echo ${OBJCOPY} -O binary $@ $@.bin;				\
+	${OBJCOPY} -O binary $@ $@.bin;					\
+	chmod 755 $@.bin
--- a/sys/arch/dreamcast/dev/g2/g2rtc.c	Sun Sep 26 03:58:54 2010 +0000
+++ b/sys/arch/dreamcast/dev/g2/g2rtc.c	Sat Oct 09 03:31:35 2010 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: g2rtc.c,v 1.2.10.2 2010/03/11 15:02:13 yamt Exp $ */
+/* $NetBSD: g2rtc.c,v 1.2.10.3 2010/10/09 03:31:43 yamt Exp $ */
 
 /*-
  * Copyright (c) 2002 The NetBSD Foundation, Inc.
@@ -27,7 +27,7 @@
  */
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: g2rtc.c,v 1.2.10.2 2010/03/11 15:02:13 yamt Exp $");
+__KERNEL_RCSID(0, "$NetBSD: g2rtc.c,v 1.2.10.3 2010/10/09 03:31:43 yamt Exp $");
 
 #include <sys/param.h>
 #include <sys/systm.h>
@@ -46,36 +46,30 @@
 #define G2RTC_OFFSET	(20 * SECYR + 5 * SECDAY)
 
 struct g2rtc_softc {
-	struct device sc_dev;
+	device_t sc_dev;
 
 	bus_space_tag_t sc_bt;
 	bus_space_handle_t sc_bh;
+	struct todr_chip_handle sc_tch;
 };
 
 /* autoconf glue */
-static int g2rtc_match(struct device *, struct cfdata *, void *);
-static void g2rtc_attach(struct device *, struct device *, void *);
+static int g2rtc_match(device_t, cfdata_t, void *);
+static void g2rtc_attach(device_t, device_t, void *);
 
-CFATTACH_DECL(g2rtc, sizeof(struct g2rtc_softc),
-	      g2rtc_match, g2rtc_attach, NULL, NULL);
+CFATTACH_DECL_NEW(g2rtc, sizeof(struct g2rtc_softc),
+    g2rtc_match, g2rtc_attach, NULL, NULL);
 
 
 /* todr(9) methods */
 static int g2rtc_todr_gettime(todr_chip_handle_t, struct timeval *);
 static int g2rtc_todr_settime(todr_chip_handle_t, struct timeval *);
 
-static struct todr_chip_handle g2rtc_todr_handle = {
-	.cookie       = NULL,	/* set on attach */
-	.todr_gettime = g2rtc_todr_gettime,
-	.todr_settime = g2rtc_todr_settime,
-};
-
-
 static inline uint32_t g2rtc_read(bus_space_tag_t, bus_space_handle_t);
 
 
 static int
-g2rtc_match(struct device *parent, struct cfdata *cf, void *aux)
+g2rtc_match(device_t parent, cfdata_t cf, void *aux)
 {
 	static int g2rtc_matched = 0;
 
@@ -88,22 +82,26 @@
 
 
 static void
-g2rtc_attach(struct device *parent, struct device *self, void *aux)
+g2rtc_attach(device_t parent, device_t self, void *aux)
 {
-	struct g2rtc_softc *sc = (void *)self;
+	struct g2rtc_softc *sc = device_private(self);
 	struct g2bus_attach_args *ga = aux;
+	todr_chip_handle_t tch;
 
+	sc->sc_dev = self;
 	sc->sc_bt = ga->ga_memt;
 	if (bus_space_map(sc->sc_bt, G2RTC_REG_BASE, G2RTC_REG_SIZE, 0,
-			  &sc->sc_bh) != 0)
-	{
+	    &sc->sc_bh) != 0) {
 		printf(": unable to map registers\n");
 		return;
 	}
 	printf(": time-of-day clock\n");
 
-	g2rtc_todr_handle.cookie = sc;
-	todr_attach(&g2rtc_todr_handle);
+	tch = &sc->sc_tch;
+	tch->cookie = sc;
+	tch->todr_gettime = g2rtc_todr_gettime,
+	tch->todr_settime = g2rtc_todr_settime,
+	todr_attach(tch);
 }
 
 
@@ -112,7 +110,7 @@
 {
 	
 	return ((bus_space_read_4(bt, bh, 0) & 0xffff) << 16)
-		| (bus_space_read_4(bt, bh, 4) & 0xffff);
+	    | (bus_space_read_4(bt, bh, 4) & 0xffff);
 }
 
 
@@ -173,5 +171,4 @@
 	}
 
 	return EIO;
-
 }
--- a/sys/arch/dreamcast/dev/gdrom.c	Sun Sep 26 03:58:54 2010 +0000
+++ b/sys/arch/dreamcast/dev/gdrom.c	Sat Oct 09 03:31:35 2010 +0000
@@ -1,4 +1,4 @@
-/*	$NetBSD: gdrom.c,v 1.24.20.1 2009/05/04 08:10:55 yamt Exp $	*/
+/*	$NetBSD: gdrom.c,v 1.24.20.2 2010/10/09 03:31:42 yamt Exp $	*/
 
 /*-
  * Copyright (c) 2001 Marcus Comstedt
@@ -33,13 +33,14 @@
  */
 
 #include <sys/cdefs.h>			/* RCS ID & Copyright macro defns */
-__KERNEL_RCSID(0, "$NetBSD: gdrom.c,v 1.24.20.1 2009/05/04 08:10:55 yamt Exp $");
+__KERNEL_RCSID(0, "$NetBSD: gdrom.c,v 1.24.20.2 2010/10/09 03:31:42 yamt Exp $");
 
 #include <sys/param.h>
 #include <sys/systm.h>
 #include <sys/device.h>
 
 #include <sys/buf.h>
+#include <sys/bufq.h>
 #include <sys/ioctl.h>
 #include <sys/fcntl.h>
 #include <sys/disklabel.h>
@@ -50,8 +51,10 @@
 
 #include <machine/sysasicvar.h>
 
-int	gdrommatch(struct device *, struct cfdata *, void *);
-void	gdromattach(struct device *, struct device *, void *);
+#include "ioconf.h"
+
+static int  gdrommatch(device_t, cfdata_t, void *);
+static void gdromattach(device_t, device_t, void *);
 
 dev_type_open(gdromopen);
 dev_type_close(gdromclose);
@@ -71,11 +74,14 @@
 };
 
 struct gdrom_softc {
-	struct device sc_dv;	/* generic device info; must come first */
-	struct disk dkdev;	/* generic disk info */
+	device_t sc_dev;	/* generic device info */
+	struct disk sc_dk;	/* generic disk info */
+	struct bufq_state *sc_bufq;	/* device buffer queue */
 	struct buf curbuf;	/* state of current I/O operation */
 
-	int is_open, is_busy;
+	bool is_open;
+	bool is_busy;
+	bool is_active;
 	int open