sync to latest -current. jmcneill-usbmp
authormrg <mrg@NetBSD.org>
Sun, 29 Apr 2012 23:04:36 +0000
branchjmcneill-usbmp
changeset 280195 a6c1a072c759
parent 280194 d6fff92214f4
child 280196 1ba9310bc536
sync to latest -current.
sys/arch/amd64/acpi/acpi_wakecode.S
sys/arch/amd64/amd64/genassym.cf
sys/arch/amd64/amd64/locore.S
sys/arch/amd64/amd64/machdep.c
sys/arch/amd64/amd64/mptramp.S
sys/arch/amd64/amd64/vector.S
sys/arch/amd64/conf/GENERIC
sys/arch/amd64/conf/XEN3_DOM0
sys/arch/amd64/include/param.h
sys/arch/amiga/amiga/autoconf.c
sys/arch/amiga/conf/DRACO
sys/arch/amiga/conf/GENERIC
sys/arch/amiga/conf/GENERIC.in
sys/arch/amiga/conf/INSTALL
sys/arch/amiga/conf/files.amiga
sys/arch/amiga/dev/if_ne_zbus.c
sys/arch/arm/imx/files.imx51
sys/arch/arm/imx/imx31_clock.c
sys/arch/arm/imx/imx51_axi.c
sys/arch/arm/imx/imx51_ccm.c
sys/arch/arm/imx/imx51_ccmreg.h
sys/arch/arm/imx/imx51_ccmvar.h
sys/arch/arm/imx/imx51_clock.c
sys/arch/arm/imx/imx51_dpllreg.h
sys/arch/arm/imx/imx51_esdhc.c
sys/arch/arm/imx/imx51_iomux.c
sys/arch/arm/imx/imx51_iomuxreg.h
sys/arch/arm/imx/imx51_ipuv3.c
sys/arch/arm/imx/imx51_ipuv3reg.h
sys/arch/arm/imx/imx51_ipuv3var.h
sys/arch/arm/imx/imx51reg.h
sys/arch/arm/imx/imxclock.c
sys/arch/arm/imx/imxclockvar.h
sys/arch/arm/imx/imxepitreg.h
sys/arch/evbarm/conf/ADI_BRH
sys/arch/evbarm/conf/ARMADILLO210
sys/arch/evbarm/conf/ARMADILLO9
sys/arch/evbarm/conf/BEAGLEBOARD
sys/arch/evbarm/conf/CP3100
sys/arch/evbarm/conf/GEMINI
sys/arch/evbarm/conf/GEMINI_MASTER
sys/arch/evbarm/conf/GEMINI_SLAVE
sys/arch/evbarm/conf/GUMSTIX
sys/arch/evbarm/conf/HDL_G
sys/arch/evbarm/conf/IMX31LITE
sys/arch/evbarm/conf/INTEGRATOR
sys/arch/evbarm/conf/IQ31244
sys/arch/evbarm/conf/IQ80310
sys/arch/evbarm/conf/IQ80321
sys/arch/evbarm/conf/IXDP425
sys/arch/evbarm/conf/IXM1200
sys/arch/evbarm/conf/LUBBOCK
sys/arch/evbarm/conf/MMNET_GENERIC
sys/arch/evbarm/conf/MPCSA_GENERIC
sys/arch/evbarm/conf/NAPPI
sys/arch/evbarm/conf/NETWALKER
sys/arch/evbarm/conf/NETWALKER_MD
sys/arch/evbarm/conf/NSLU2
sys/arch/evbarm/conf/OSK5912
sys/arch/evbarm/conf/OVERO
sys/arch/evbarm/conf/README.evbarm
sys/arch/evbarm/conf/SMDK2410
sys/arch/evbarm/conf/SMDK2800
sys/arch/evbarm/conf/TEAMASA_NPWR
sys/arch/evbarm/conf/TEAMASA_NPWR_FC
sys/arch/evbarm/conf/TISDP2420
sys/arch/evbarm/conf/TISDP2430
sys/arch/evbarm/conf/TS7200
sys/arch/evbarm/conf/TWINTAIL
sys/arch/evbarm/conf/VIPER
sys/arch/evbarm/conf/ZAO425
sys/arch/evbarm/conf/files.netwalker
sys/arch/evbarm/conf/std.netwalker
sys/arch/evbarm/dev/plcom.c
sys/arch/evbarm/dev/plcomreg.h
sys/arch/evbarm/netwalker/netwalker_lcd.c
sys/arch/evbarm/netwalker/netwalker_machdep.c
sys/arch/evbarm/netwalker/netwalker_usb.c
sys/arch/evbppc/obs405/rbus_machdep.c
sys/arch/hp700/conf/GENERIC
sys/arch/hp700/dev/apic.c
sys/arch/hp700/dev/cpu.c
sys/arch/hp700/dev/ssio.c
sys/arch/hp700/hp700/locore.S
sys/arch/hp700/hp700/machdep.c
sys/arch/hppa/hppa/fpu.c
sys/arch/hppa/hppa/trap.S
sys/arch/hppa/hppa/trap.c
sys/arch/i386/acpi/acpi_wakecode.S
sys/arch/i386/conf/ALL
sys/arch/i386/conf/GENERIC
sys/arch/i386/conf/XEN3_DOM0
sys/arch/i386/i386/compat_16_machdep.c
sys/arch/i386/i386/genassym.cf
sys/arch/i386/i386/locore.S
sys/arch/i386/i386/mptramp.S
sys/arch/i386/include/param.h
sys/arch/ia64/conf/GENERIC
sys/arch/ia64/conf/GENERIC.SKI
sys/arch/powerpc/booke/dev/pq3etsec.c
sys/arch/powerpc/include/cpu.h
sys/arch/sandpoint/conf/GENERIC
sys/arch/sandpoint/sandpoint/satmgr.c
sys/arch/sandpoint/stand/altboot/README.altboot
sys/arch/sandpoint/stand/altboot/brdsetup.c
sys/arch/sandpoint/stand/altboot/dsk.c
sys/arch/sandpoint/stand/altboot/globals.h
sys/arch/sandpoint/stand/altboot/main.c
sys/arch/sparc/sparc/intr.c
sys/arch/sparc/sparc/machdep.c
sys/arch/sparc64/dev/ffb.c
sys/arch/sparc64/dev/gfb.c
sys/arch/sparc64/sparc64/trap.c
sys/arch/x68k/conf/GENERIC
sys/arch/x68k/conf/INSTALL
sys/arch/x68k/conf/files.x68k
sys/arch/x68k/conf/majors.x68k
sys/arch/x68k/dev/com.c
sys/arch/x68k/dev/com_intio.c
sys/arch/x68k/dev/comreg.h
sys/arch/x68k/stand/Makefile
sys/arch/x68k/stand/mboot/mboot.c
sys/arch/x68k/x68k/autoconf.c
sys/arch/x68k/x68k/locore.s
sys/arch/x68k/x68k/vectors.s
sys/arch/x86/acpi/acpi_wakeup.c
sys/arch/x86/include/cpu.h
sys/arch/x86/include/cpuvar.h
sys/arch/x86/include/pmap.h
sys/arch/x86/include/psl.h
sys/arch/x86/include/specialreg.h
sys/arch/x86/pci/amdnb_misc.c
sys/arch/x86/pci/amdtemp.c
sys/arch/x86/pci/files.pci
sys/arch/x86/pci/pchb.c
sys/arch/x86/pci/pchbvar.h
sys/arch/x86/pci/pcib.c
sys/arch/x86/x86/cpu.c
sys/arch/x86/x86/errata.c
sys/arch/x86/x86/mtrr_i686.c
sys/arch/x86/x86/pmap.c
sys/arch/x86/x86/pmap_tlb.c
sys/arch/xen/include/xenpmap.h
sys/arch/xen/x86/cpu.c
sys/arch/xen/x86/x86_xpmap.c
sys/arch/xen/x86/xen_pmap.c
sys/arch/xen/xen/hypervisor.c
sys/arch/zaurus/conf/GENERIC
sys/arch/zaurus/conf/INSTALL
sys/coda/coda_psdev.c
sys/coda/coda_subr.c
sys/coda/coda_venus.c
sys/coda/coda_vfsops.c
sys/coda/coda_vnops.c
sys/coda/coda_vnops.h
sys/compat/netbsd32/netbsd32.h
sys/compat/netbsd32/netbsd32_execve.c
sys/compat/netbsd32/netbsd32_syscall.h
sys/compat/netbsd32/netbsd32_syscallargs.h
sys/compat/netbsd32/netbsd32_syscalls.c
sys/compat/netbsd32/netbsd32_sysent.c
sys/compat/netbsd32/syscalls.master
sys/conf/files
sys/ddb/db_command.c
sys/dev/DEVNAMES
sys/dev/acpi/acpi.c
sys/dev/acpi/acpi_cpu.h
sys/dev/acpi/acpi_cpu_tstate.c
sys/dev/acpi/acpica/OsdMemory.c
sys/dev/ata/ata.c
sys/dev/audio.c
sys/dev/cardbus/files.cardbus
sys/dev/cardbus/if_bwi_cardbus.c
sys/dev/dkwedge/dk.c
sys/dev/dkwedge/dkwedge_apple.c
sys/dev/dkwedge/dkwedge_mbr.c
sys/dev/i2c/dbcool.c
sys/dev/i2c/i2c_exec.c
sys/dev/i2c/i2c_io.h
sys/dev/ic/ahcisata_core.c
sys/dev/ic/bwi.c
sys/dev/ic/bwivar.h
sys/dev/ic/com.c
sys/dev/ic/mvsata.c
sys/dev/ic/opl.c
sys/dev/ic/oplvar.h
sys/dev/ic/siisata.c
sys/dev/ieee1394/firewire.c
sys/dev/ieee1394/firewirereg.h
sys/dev/ieee1394/fwdev.c
sys/dev/ieee1394/fwmem.c
sys/dev/ieee1394/fwohcivar.h
sys/dev/ieee1394/if_fwip.c
sys/dev/isa/cms.c
sys/dev/isa/midi_pcppi.c
sys/dev/isa/opl_ess.c
sys/dev/isa/opl_isa.c
sys/dev/isa/opl_sb.c
sys/dev/isa/opl_wss.c
sys/dev/isa/opl_ym.c
sys/dev/isa/pcppi.c
sys/dev/isa/spkr.c
sys/dev/midi.c
sys/dev/midi_if.h
sys/dev/midisyn.c
sys/dev/midisynvar.h
sys/dev/mii/miidevs
sys/dev/mii/miidevs.h
sys/dev/mii/miidevs_data.h
sys/dev/pci/agp.c
sys/dev/pci/files.pci
sys/dev/pci/if_bnxvar.h
sys/dev/pci/mpii.c
sys/dev/pci/opl_cmpci.c
sys/dev/pci/opl_eso.c
sys/dev/pci/opl_fms.c
sys/dev/pci/opl_sv.c
sys/dev/pci/opl_yds.c
sys/dev/pci/pci_subr.c
sys/dev/pci/pcidevs
sys/dev/pci/pcidevs.h
sys/dev/pci/pcidevs_data.h
sys/dev/pci/r128fb.c
sys/dev/pci/radeonfb.c
sys/dev/pci/slide.c
sys/dev/pci/voodoofb.c
sys/dev/pci/voyager/voyagerfb.c
sys/dev/raidframe/rf_netbsdkintf.c
sys/dev/rasops/rasops.c
sys/dev/rasops/rasops.h
sys/dev/rasops/rasops15.c
sys/dev/rndpseudo.c
sys/dev/scsipi/atapi_wdc.c
sys/dev/scsipi/atapiconf.c
sys/dev/scsipi/cd.c
sys/dev/scsipi/scsi_base.c
sys/dev/scsipi/scsiconf.c
sys/dev/scsipi/scsiconf.h
sys/dev/scsipi/scsipi_base.c
sys/dev/scsipi/scsipi_ioctl.c
sys/dev/scsipi/scsipiconf.h
sys/dev/scsipi/sd.c
sys/dev/scsipi/st.c
sys/dev/scsipi/st_atapi.c
sys/dev/scsipi/st_scsi.c
sys/dev/sequencer.c
sys/dev/sun/files.sun
sys/dev/sun/kbd.c
sys/dev/sun/kbdvar.h
sys/dev/usb/uaudio.c
sys/dev/usb/ubt.c
sys/dev/usb/ugen.c
sys/dev/usb/ukbd.c
sys/dev/usb/umass_scsipi.c
sys/dev/usb/usbdevs
sys/dev/usb/usbdevs.h
sys/dev/usb/usbdevs_data.h
sys/dev/usb/usbdi.h
sys/dev/wscons/wsconsio.h
sys/dev/wscons/wsdisplay_glyphcache.c
sys/dev/wscons/wsdisplay_glyphcachevar.h
sys/dev/wscons/wsksymdef.h
sys/dev/wsfb/genfb.c
sys/dev/wsfont/Droid_Sans_Mono_12x22.h
sys/dev/wsfont/Droid_Sans_Mono_9x18.h
sys/external/isc/atheros_hal/ic/ah_osdep.c
sys/fs/msdosfs/msdosfs_fat.c
sys/fs/puffs/puffs_msgif.h
sys/fs/puffs/puffs_node.c
sys/fs/puffs/puffs_sys.h
sys/fs/puffs/puffs_vfsops.c
sys/fs/puffs/puffs_vnops.c
sys/kern/exec_elf.c
sys/kern/init_sysctl.c
sys/kern/kern_exec.c
sys/kern/kern_exit.c
sys/kern/kern_lwp.c
sys/kern/kern_malloc.c
sys/kern/kern_malloc_debug.c
sys/kern/kern_malloc_stdtype.c
sys/kern/kern_proc.c
sys/kern/kern_rndpool.c
sys/kern/kern_rndq.c
sys/kern/kern_synch.c
sys/kern/subr_cprng.c
sys/kern/subr_disk_open.c
sys/kern/subr_kcpuset.c
sys/kern/subr_kmem.c
sys/kern/subr_pcu.c
sys/kern/sys_sched.c
sys/kern/uipc_mbuf.c
sys/kern/vfs_syscalls.c
sys/lib/libkern/arc4random.c
sys/modules/Makefile
sys/modules/amdtemp/amdtemp.ioconf
sys/modules/chfs/Makefile
sys/modules/coda/Makefile
sys/net/npf/npf.h
sys/net/npf/npf_impl.h
sys/net/npf/npf_mbuf.c
sys/net/npf/npf_ncode.h
sys/netinet/rfc6056.c
sys/netinet/tcp_input.c
sys/netinet/tcp_vtw.c
sys/nfs/nfs_vnops.c
sys/rump/dev/lib/libdrvctl/component.c
sys/rump/dev/lib/libmd/component.c
sys/rump/dev/lib/libnpf/Makefile
sys/rump/librump/rumpkern/Makefile.rumpkern
sys/rump/librump/rumpkern/locks_up.c
sys/rump/librump/rumpkern/memalloc.c
sys/rump/net/lib/libnet/Makefile
sys/sys/cprng.h
sys/sys/debug.h
sys/sys/exec.h
sys/sys/kcpuset.h
sys/sys/malloc.h
sys/sys/mallocvar.h
sys/sys/mbuf.h
sys/sys/param.h
sys/sys/pcu.h
sys/sys/rnd.h
sys/sys/spawn.h
sys/ufs/chfs/chfs.h
sys/ufs/chfs/chfs_build.c
sys/ufs/chfs/chfs_inode.h
sys/ufs/chfs/chfs_subr.c
sys/ufs/chfs/chfs_vfsops.c
sys/ufs/chfs/chfs_vnode.c
sys/ufs/chfs/chfs_vnops.c
sys/ufs/chfs/chfs_write.c
sys/ufs/chfs/debug.c
sys/ufs/chfs/debug.h
sys/ufs/chfs/ebh.h
sys/ufs/ext2fs/ext2fs_readwrite.c
sys/ufs/ffs/fs.h
sys/ufs/files.ufs
sys/ufs/ufs/ufs_readwrite.c
sys/uvm/uvm_amap.c
sys/uvm/uvm_emap.c
sys/uvm/uvm_extern.h
sys/uvm/uvm_glue.c
sys/uvm/uvm_km.c
sys/uvm/uvm_map.c
--- a/sys/arch/amd64/acpi/acpi_wakecode.S	Tue Apr 17 19:25:17 2012 +0000
+++ b/sys/arch/amd64/acpi/acpi_wakecode.S	Sun Apr 29 23:04:36 2012 +0000
@@ -1,4 +1,4 @@
-/*	$NetBSD: acpi_wakecode.S,v 1.10 2009/08/24 22:06:50 jmcneill Exp $	*/
+/*	$NetBSD: acpi_wakecode.S,v 1.10.16.1 2012/04/29 23:04:36 mrg Exp $	*/
 
 /*-
  * Copyright (c) 2007 Joerg Sonnenberger <joerg@netbsd.org>
@@ -198,7 +198,7 @@
 
 	/* Enable paging */
 	movl	%cr0,%eax
-	orl	$(CR0_PE|CR0_PG|CR0_NE|CR0_TS|CR0_MP|CR0_WP),%eax
+	orl	$(CR0_PE|CR0_PG|CR0_NE|CR0_TS|CR0_MP|CR0_WP|CR0_AM),%eax
 	movl	%eax,%cr0
 	/* Flush prefetch queue */
 	jmp	1f
--- a/sys/arch/amd64/amd64/genassym.cf	Tue Apr 17 19:25:17 2012 +0000
+++ b/sys/arch/amd64/amd64/genassym.cf	Sun Apr 29 23:04:36 2012 +0000
@@ -1,4 +1,4 @@
-#	$NetBSD: genassym.cf,v 1.48.6.1 2012/02/18 07:31:09 mrg Exp $
+#	$NetBSD: genassym.cf,v 1.48.6.2 2012/04/29 23:04:36 mrg Exp $
 
 #
 # Copyright (c) 1998, 2006, 2007, 2008 The NetBSD Foundation, Inc.
@@ -228,12 +228,10 @@
 define	CPU_INFO_WANT_PMAPLOAD	offsetof(struct cpu_info, ci_want_pmapload)
 define	CPU_INFO_TLBSTATE	offsetof(struct cpu_info, ci_tlbstate)
 define	TLBSTATE_VALID		TLBSTATE_VALID
-define	CPU_INFO_TLB_EVCNT	offsetof(struct cpu_info, ci_tlb_evcnt)
 define	CPU_INFO_CURLWP		offsetof(struct cpu_info, ci_curlwp)
 define	CPU_INFO_CURLDT		offsetof(struct cpu_info, ci_curldt)
 define	CPU_INFO_IDLELWP	offsetof(struct cpu_info, ci_data.cpu_idlelwp)
 define	CPU_INFO_PMAP		offsetof(struct cpu_info, ci_pmap)
-define	CPU_INFO_CPUMASK	offsetof(struct cpu_info, ci_cpumask)
 define	CPU_INFO_RSP0		offsetof(struct cpu_info, ci_tss.tss_rsp0)
 define	CPU_INFO_NSYSCALL	offsetof(struct cpu_info, ci_data.cpu_nsyscall)
 define	CPU_INFO_NTRAP		offsetof(struct cpu_info, ci_data.cpu_ntrap)
--- a/sys/arch/amd64/amd64/locore.S	Tue Apr 17 19:25:17 2012 +0000
+++ b/sys/arch/amd64/amd64/locore.S	Sun Apr 29 23:04:36 2012 +0000
@@ -1,4 +1,4 @@
-/*	$NetBSD: locore.S,v 1.65.8.2 2012/03/04 00:46:02 mrg Exp $	*/
+/*	$NetBSD: locore.S,v 1.65.8.3 2012/04/29 23:04:36 mrg Exp $	*/
 
 /*
  * Copyright-o-rama!
@@ -626,7 +626,7 @@
 	 * 4. Enable paging and the rest of it.
 	 */
 	movl	%cr0,%eax
-	orl	$(CR0_PE|CR0_PG|CR0_NE|CR0_TS|CR0_MP|CR0_WP),%eax
+	orl	$(CR0_PE|CR0_PG|CR0_NE|CR0_TS|CR0_MP|CR0_WP|CR0_AM),%eax
 	movl	%eax,%cr0
 	jmp	compat
 compat:
--- a/sys/arch/amd64/amd64/machdep.c	Tue Apr 17 19:25:17 2012 +0000
+++ b/sys/arch/amd64/amd64/machdep.c	Sun Apr 29 23:04:36 2012 +0000
@@ -1,4 +1,4 @@
-/*	$NetBSD: machdep.c,v 1.171.2.5 2012/03/06 18:26:34 mrg Exp $	*/
+/*	$NetBSD: machdep.c,v 1.171.2.6 2012/04/29 23:04:36 mrg Exp $	*/
 
 /*-
  * Copyright (c) 1996, 1997, 1998, 2000, 2006, 2007, 2008, 2011
@@ -111,7 +111,7 @@
  */
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: machdep.c,v 1.171.2.5 2012/03/06 18:26:34 mrg Exp $");
+__KERNEL_RCSID(0, "$NetBSD: machdep.c,v 1.171.2.6 2012/04/29 23:04:36 mrg Exp $");
 
 /* #define XENDEBUG_LOW  */
 
@@ -2071,6 +2071,7 @@
 	uint16_t sel;
 	int error;
 	struct pmap *pmap = l->l_proc->p_vmspace->vm_map.pmap;
+	struct proc *p = l->l_proc;
 
 	gr = mcp->__gregs;
 
@@ -2104,33 +2105,42 @@
 			return error;
 #endif
 	} else {
+#define VUD(sel) \
+    ((p->p_flag & PK_32) ? VALID_USER_DSEL32(sel) : VALID_USER_DSEL(sel))
 		sel = gr[_REG_ES] & 0xffff;
-		if (sel != 0 && !VALID_USER_DSEL(sel))
+		if (sel != 0 && !VUD(sel))
 			return EINVAL;
 
+/* XXX: Shouldn't this be FSEL32? */
+#define VUF(sel) \
+    ((p->p_flag & PK_32) ? VALID_USER_DSEL32(sel) : VALID_USER_DSEL(sel))
 		sel = gr[_REG_FS] & 0xffff;
-		if (sel != 0 && !VALID_USER_DSEL(sel))
+		if (sel != 0 && !VUF(sel))
 			return EINVAL;
 
+#define VUG(sel) \
+    ((p->p_flag & PK_32) ? VALID_USER_GSEL32(sel) : VALID_USER_DSEL(sel))
 		sel = gr[_REG_GS] & 0xffff;
-		if (sel != 0 && !VALID_USER_DSEL(sel))
+		if (sel != 0 && !VUG(sel))
 			return EINVAL;
 
 		sel = gr[_REG_DS] & 0xffff;
-		if (!VALID_USER_DSEL(sel))
+		if (!VUD(sel))
 			return EINVAL;
 
 #ifndef XEN
 		sel = gr[_REG_SS] & 0xffff;
-		if (!VALID_USER_DSEL(sel)) 
+		if (!VUD(sel))
 			return EINVAL;
 #endif
 
 	}
 
 #ifndef XEN
+#define VUC(sel) \
+    ((p->p_flag & PK_32) ? VALID_USER_CSEL32(sel) : VALID_USER_CSEL(sel))
 	sel = gr[_REG_CS] & 0xffff;
-	if (!VALID_USER_CSEL(sel))
+	if (!VUC(sel))
 		return EINVAL;
 #endif
 
--- a/sys/arch/amd64/amd64/mptramp.S	Tue Apr 17 19:25:17 2012 +0000
+++ b/sys/arch/amd64/amd64/mptramp.S	Sun Apr 29 23:04:36 2012 +0000
@@ -1,4 +1,4 @@
-/*	$NetBSD: mptramp.S,v 1.12 2010/04/20 15:42:21 jym Exp $	*/
+/*	$NetBSD: mptramp.S,v 1.12.12.1 2012/04/29 23:04:36 mrg Exp $	*/
 
 /*-
  * Copyright (c) 2000 The NetBSD Foundation, Inc.
@@ -108,7 +108,6 @@
 #define HALTT(x,y) /**/
 #endif
 
-	.globl	_C_LABEL(idle_loop)
 	.global _C_LABEL(cpu_spinup_trampoline)
 	.global _C_LABEL(cpu_spinup_trampoline_end)
 	.global _C_LABEL(cpu_hatch)
@@ -173,7 +172,7 @@
         movl    %ecx,%cr3               # load ptd addr into mmu
 
         movl    %cr0,%eax               # get control word
-        orl     $(CR0_PE|CR0_PG|CR0_NE|CR0_TS|CR0_MP|CR0_WP),%eax
+        orl     $(CR0_PE|CR0_PG|CR0_NE|CR0_TS|CR0_MP|CR0_WP|CR0_AM),%eax
         movl    %eax,%cr0
 	jmp	mptramp_compat
 mptramp_compat:
@@ -252,7 +251,6 @@
 	movl    PCB_CR0(%rsi),%eax
 	movq    %rax,%cr0
 	call	_C_LABEL(cpu_hatch)
-	jmp	_C_LABEL(idle_loop)
 	
 	.data
 _C_LABEL(mp_pdirpa):
--- a/sys/arch/amd64/amd64/vector.S	Tue Apr 17 19:25:17 2012 +0000
+++ b/sys/arch/amd64/amd64/vector.S	Sun Apr 29 23:04:36 2012 +0000
@@ -1,4 +1,4 @@
-/*	$NetBSD: vector.S,v 1.38 2011/06/12 03:35:38 rmind Exp $	*/
+/*	$NetBSD: vector.S,v 1.38.6.1 2012/04/29 23:04:36 mrg Exp $	*/
 
 /*-
  * Copyright (c) 1998, 2007, 2008 The NetBSD Foundation, Inc.
@@ -228,7 +228,7 @@
   	STI(si)
 	jmp	calltrap
 IDTVEC(trap11)
-	ZTRAP(T_ALIGNFLT)
+	TRAP(T_ALIGNFLT)
 IDTVEC(trap12)
 	ZTRAP(T_MCA)
 IDTVEC(trap13)
--- a/sys/arch/amd64/conf/GENERIC	Tue Apr 17 19:25:17 2012 +0000
+++ b/sys/arch/amd64/conf/GENERIC	Sun Apr 29 23:04:36 2012 +0000
@@ -1,4 +1,4 @@
-# $NetBSD: GENERIC,v 1.340.2.6 2012/04/05 21:33:11 mrg Exp $
+# $NetBSD: GENERIC,v 1.340.2.7 2012/04/29 23:04:37 mrg Exp $
 #
 # GENERIC machine description file
 #
@@ -22,7 +22,7 @@
 
 options 	INCLUDE_CONFIG_FILE	# embed config file in kernel binary
 
-#ident 		"GENERIC-$Revision: 1.340.2.6 $"
+#ident 		"GENERIC-$Revision: 1.340.2.7 $"
 
 maxusers	64		# estimated number of users
 
@@ -127,9 +127,11 @@
 # Wedge support
 options 	DKWEDGE_AUTODISCOVER	# Automatically add dk(4) instances
 options 	DKWEDGE_METHOD_GPT	# Supports GPT partitions as wedges
-# The following two options can break /etc/fstab, so handle with care
+# The following three options can break /etc/fstab, so handle with care
 #options 	DKWEDGE_METHOD_BSDLABEL	# Support disklabel entries as wedges
 #options 	DKWEDGE_METHOD_MBR	# Support MBR partitions as wedges
+#options	DKWEDGE_METHOD_APPLE    # Support Apple partitions as wedges
+
 
 file-system 	FFS		# UFS
 file-system	MFS		# memory file system
@@ -438,7 +440,8 @@
 
 # Hardware monitors
 
-amdtemp* at pchb?			# AMD CPU Temperature sensors
+amdnb_misc* at pci?			# AMD NB Misc Configuration
+amdtemp* at amdnb_misc?			# AMD CPU Temperature sensors
 
 # Winbond LPC Super I/O
 #wbsio*	at isa? port 0x2e
@@ -543,7 +546,8 @@
 isp*	at pci? dev ? function ?	# Qlogic ISP [12]0x0 SCSI/FibreChannel
 mfi*	at pci? dev ? function ?	# LSI MegaRAID SAS
 mly*	at pci? dev ? function ?	# Mylex AcceleRAID and eXtremeRAID
-mpt*	at pci? dev ? function ?	# LSILogic 9x9 and 53c1030
+mpt*	at pci? dev ? function ?	# LSILogic 9x9 and 53c1030 (Fusion-MPT)
+mpii*	at pci? dev ? function ?	# LSI Logic Fusion-MPT II
 pcscp*	at pci? dev ? function ?	# AMD 53c974 PCscsi-PCI SCSI
 siop*	at pci? dev ? function ?	# Symbios 53c8xx SCSI
 esiop*	at pci? dev ? function ?	# Symbios 53c875 and newer SCSI
@@ -1197,7 +1201,7 @@
 pseudo-device	stf			# 6to4 IPv6 over IPv4 encapsulation
 pseudo-device	vlan			# IEEE 802.1q encapsulation
 pseudo-device	bridge			# simple inter-network bridging
-#options 	BRIDGE_IPF		# bridge uses IP/IPv6 pfil hooks too
+options 	BRIDGE_IPF		# bridge uses IP/IPv6 pfil hooks too
 pseudo-device	agr			# IEEE 802.3ad link aggregation
 
 #
--- a/sys/arch/amd64/conf/XEN3_DOM0	Tue Apr 17 19:25:17 2012 +0000
+++ b/sys/arch/amd64/conf/XEN3_DOM0	Sun Apr 29 23:04:36 2012 +0000
@@ -1,4 +1,4 @@
-# $NetBSD: XEN3_DOM0,v 1.75.2.3 2012/03/11 01:52:18 mrg Exp $
+# $NetBSD: XEN3_DOM0,v 1.75.2.4 2012/04/29 23:04:37 mrg Exp $
 
 include 	"arch/amd64/conf/std.xen"
 
@@ -296,7 +296,8 @@
 
 # Hardware monitors
 
-amdtemp* at pchb?			# AMD CPU Temperature sensors
+amdnb_misc* at pci?			# AMD NB Misc Configuration
+amdtemp* at amdnb_misc?			# AMD CPU Temperature sensors
 
 # AMD 768 and 8111 power/ACPI controllers
 amdpm*	at pci? dev ? function ?	# RNG and SMBus 1.0 interface
@@ -486,7 +487,8 @@
 isp*	at pci? dev ? function ?	# Qlogic ISP [12]0x0 SCSI/FibreChannel
 mfi*	at pci? dev ? function ?	# LSI MegaRAID SAS
 mly*	at pci? dev ? function ?	# Mylex AcceleRAID and eXtremeRAID
-mpt*	at pci? dev ? function ?	# LSI Fusion SCSI/FC
+mpt*	at pci? dev ? function ?	# LSILogic 9x9 and 53c1030 (Fusion-MPT)
+mpii*	at pci? dev ? function ?	# LSI Logic Fusion-MPT II
 njs*	at pci? dev ? function ?	# Workbit NinjaSCSI-32
 pcscp*	at pci? dev ? function ?	# AMD 53c974 PCscsi-PCI SCSI
 siop*	at pci? dev ? function ?	# Symbios 53c8xx SCSI
--- a/sys/arch/amd64/include/param.h	Tue Apr 17 19:25:17 2012 +0000
+++ b/sys/arch/amd64/include/param.h	Sun Apr 29 23:04:36 2012 +0000
@@ -1,7 +1,12 @@
-/*	$NetBSD: param.h,v 1.14.6.1 2012/02/18 07:31:12 mrg Exp $	*/
+/*	$NetBSD: param.h,v 1.14.6.2 2012/04/29 23:04:37 mrg Exp $	*/
 
 #ifdef __x86_64__
 
+#ifndef XEN
+/* Must be defined before cpu.h */
+#define	MAXCPUS		256
+#endif
+
 #ifdef _KERNEL
 #include <machine/cpu.h>
 #endif
--- a/sys/arch/amiga/amiga/autoconf.c	Tue Apr 17 19:25:17 2012 +0000
+++ b/sys/arch/amiga/amiga/autoconf.c	Sun Apr 29 23:04:36 2012 +0000
@@ -1,4 +1,4 @@
-/*	$NetBSD: autoconf.c,v 1.108.6.1 2012/02/18 07:31:12 mrg Exp $	*/
+/*	$NetBSD: autoconf.c,v 1.108.6.2 2012/04/29 23:04:37 mrg Exp $	*/
 
 /*
  * Copyright (c) 1994 Christian E. Hopps
@@ -31,7 +31,7 @@
  */
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: autoconf.c,v 1.108.6.1 2012/02/18 07:31:12 mrg Exp $");
+__KERNEL_RCSID(0, "$NetBSD: autoconf.c,v 1.108.6.2 2012/04/29 23:04:37 mrg Exp $");
 
 #include <sys/param.h>
 #include <sys/systm.h>
@@ -295,6 +295,8 @@
 		config_found(dp, __UNCONST("ahsc"), simple_devprint);
 	if (is_a600() || is_a1200())
 		config_found(dp, __UNCONST("pccard"), simple_devprint);
+	if (is_a1200())
+		config_found(dp, __UNCONST("a1k2cp"), simple_devprint);
 #ifdef DRACO
 	if (!is_draco())
 #endif
--- a/sys/arch/amiga/conf/DRACO	Tue Apr 17 19:25:17 2012 +0000
+++ b/sys/arch/amiga/conf/DRACO	Sun Apr 29 23:04:36 2012 +0000
@@ -1,9 +1,9 @@
-# $NetBSD: DRACO,v 1.145.2.2 2012/03/11 01:52:18 mrg Exp $
+# $NetBSD: DRACO,v 1.145.2.3 2012/04/29 23:04:37 mrg Exp $
 #
 # This file was automatically created.
 # Changes will be lost when make is run in this directory.
 #
-# Created from: # NetBSD: GENERIC.in,v 1.95 2012/01/19 22:43:11 rkujawa Exp $
+# Created from: # NetBSD: GENERIC.in,v 1.98 2012/04/17 09:59:03 rkujawa Exp $
 #
 ##
 # GENERIC machine description file
@@ -29,7 +29,7 @@
 
 options 	INCLUDE_CONFIG_FILE	# embed config file in kernel binary
 
-#ident 		"GENERIC-$Revision: 1.145.2.2 $"
+#ident 		"GENERIC-$Revision: 1.145.2.3 $"
 
 
 maxusers	8
--- a/sys/arch/amiga/conf/GENERIC	Tue Apr 17 19:25:17 2012 +0000
+++ b/sys/arch/amiga/conf/GENERIC	Sun Apr 29 23:04:36 2012 +0000
@@ -1,9 +1,9 @@
-# $NetBSD: GENERIC,v 1.275.2.2 2012/03/11 01:52:18 mrg Exp $
+# $NetBSD: GENERIC,v 1.275.2.3 2012/04/29 23:04:37 mrg Exp $
 #
 # This file was automatically created.
 # Changes will be lost when make is run in this directory.
 #
-# Created from: # NetBSD: GENERIC.in,v 1.95 2012/01/19 22:43:11 rkujawa Exp $
+# Created from: # NetBSD: GENERIC.in,v 1.98 2012/04/17 09:59:03 rkujawa Exp $
 #
 ##
 # GENERIC machine description file
@@ -29,7 +29,7 @@
 
 options 	INCLUDE_CONFIG_FILE	# embed config file in kernel binary
 
-#ident 		"GENERIC-$Revision: 1.275.2.2 $"
+#ident 		"GENERIC-$Revision: 1.275.2.3 $"
 
 
 maxusers	8
@@ -347,6 +347,11 @@
 aucc*		at mainbus0		# Amiga CC audio
 audio*		at aucc?
 
+#a1k2cp0         at mainbus0             # A1200 on-board clockport
+#clockport*      at a1k2cp0
+
+#com*            at clockport?           # Individual Computers SilverSurfer
+
 #wsmouse*	at ms?
 
 #
--- a/sys/arch/amiga/conf/GENERIC.in	Tue Apr 17 19:25:17 2012 +0000
+++ b/sys/arch/amiga/conf/GENERIC.in	Sun Apr 29 23:04:36 2012 +0000
@@ -1,4 +1,4 @@
-# $NetBSD: GENERIC.in,v 1.87.2.2 2012/03/11 01:52:18 mrg Exp $
+# $NetBSD: GENERIC.in,v 1.87.2.3 2012/04/29 23:04:37 mrg Exp $
 #
 ##
 # GENERIC machine description file
@@ -52,7 +52,7 @@
 
 options 	INCLUDE_CONFIG_FILE	# embed config file in kernel binary
 
-#ident 		"GENERIC-$Revision: 1.87.2.2 $"
+#ident 		"GENERIC-$Revision: 1.87.2.3 $"
 
 m4_ifdef(`INSTALL_CONFIGURATION', `m4_dnl
 makeoptions	COPTS="-Os"
@@ -415,6 +415,11 @@
 m4_ifdef(`INSTALL_CONFIGURATION', `', `m4_dnl
 aucc*		at mainbus0		# Amiga CC audio
 audio*		at aucc?
+
+#a1k2cp0         at mainbus0             # A1200 on-board clockport
+#clockport*      at a1k2cp0
+
+#com*            at clockport?           # Individual Computers SilverSurfer
 ')m4_dnl
 ')m4_dnl
 
--- a/sys/arch/amiga/conf/INSTALL	Tue Apr 17 19:25:17 2012 +0000
+++ b/sys/arch/amiga/conf/INSTALL	Sun Apr 29 23:04:36 2012 +0000
@@ -1,9 +1,9 @@
-# $NetBSD: INSTALL,v 1.97.2.1 2012/02/18 07:31:14 mrg Exp $
+# $NetBSD: INSTALL,v 1.97.2.2 2012/04/29 23:04:37 mrg Exp $
 #
 # This file was automatically created.
 # Changes will be lost when make is run in this directory.
 #
-# Created from: # NetBSD: GENERIC.in,v 1.95 2012/01/19 22:43:11 rkujawa Exp $
+# Created from: # NetBSD: GENERIC.in,v 1.98 2012/04/17 09:59:03 rkujawa Exp $
 #
 ##
 # GENERIC machine description file
@@ -29,7 +29,7 @@
 
 options 	INCLUDE_CONFIG_FILE	# embed config file in kernel binary
 
-#ident 		"GENERIC-$Revision: 1.97.2.1 $"
+#ident 		"GENERIC-$Revision: 1.97.2.2 $"
 
 makeoptions	COPTS="-Os"
 
--- a/sys/arch/amiga/conf/files.amiga	Tue Apr 17 19:25:17 2012 +0000
+++ b/sys/arch/amiga/conf/files.amiga	Sun Apr 29 23:04:36 2012 +0000
@@ -1,4 +1,4 @@
-#	$NetBSD: files.amiga,v 1.149.6.1 2012/02/18 07:31:15 mrg Exp $
+#	$NetBSD: files.amiga,v 1.149.6.2 2012/04/29 23:04:37 mrg Exp $
 
 # maxpartitions must be first item in files.${ARCH}.newconf
 maxpartitions 16			# NOTE THAT AMIGA IS SPECIAL!
@@ -527,5 +527,7 @@
 include	"dev/i2o/files.i2o"
 include	"dev/pci/files.pci"
 
+include "arch/amiga/clockport/files.clockport"
+
 include	"arch/amiga/conf/majors.amiga"
 
--- a/sys/arch/amiga/dev/if_ne_zbus.c	Tue Apr 17 19:25:17 2012 +0000
+++ b/sys/arch/amiga/dev/if_ne_zbus.c	Sun Apr 29 23:04:36 2012 +0000
@@ -1,4 +1,4 @@
-/*	$NetBSD: if_ne_zbus.c,v 1.14 2011/07/19 15:55:27 dyoung Exp $ */
+/*	$NetBSD: if_ne_zbus.c,v 1.14.6.1 2012/04/29 23:04:37 mrg Exp $ */
 
 /*-
  * Copyright (c) 1998 The NetBSD Foundation, Inc.
@@ -30,7 +30,7 @@
  */
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: if_ne_zbus.c,v 1.14 2011/07/19 15:55:27 dyoung Exp $");
+__KERNEL_RCSID(0, "$NetBSD: if_ne_zbus.c,v 1.14.6.1 2012/04/29 23:04:37 mrg Exp $");
 
 /*
  * Thanks to Village Tronic for giving me a card.
@@ -86,6 +86,13 @@
 #define	NE_ARIADNE_II_ASICBASE	0x0310	/* 0x0620 */
 #define	NE_ARIADNE_II_ASICSIZE	0x10
 
+/*
+ * E3B Deneb firmware v11 creates fake X-Surf autoconfig entry.
+ * Do not attach ne driver to this fake card, otherwise kernel panic
+ * may occur.
+ */
+#define DENEB_XSURF_SERNO	0xC0FFEE01	/* Serial of the fake card */
+
 int
 ne_zbus_match(device_t parent, cfdata_t cf, void *aux)
 {
@@ -96,8 +103,10 @@
 		return (1);
 
 	/* X-surf ethernet card */
-	if (zap->manid == 4626 && zap->prodid == 23)
-		return (1);
+	if (zap->manid == 4626 && zap->prodid == 23) {
+		if (zap->serno != DENEB_XSURF_SERNO)
+			return (1);
+	}
 
 	return (0);
 }
--- a/sys/arch/arm/imx/files.imx51	Tue Apr 17 19:25:17 2012 +0000
+++ b/sys/arch/arm/imx/files.imx51	Sun Apr 29 23:04:36 2012 +0000
@@ -1,4 +1,4 @@
-#	$NetBSD: files.imx51,v 1.3 2011/03/11 03:16:13 bsh Exp $
+#	$NetBSD: files.imx51,v 1.3.8.1 2012/04/29 23:04:37 mrg Exp $
 #
 # Configuration info for the Freescale i.MX51
 #
@@ -56,10 +56,11 @@
 attach	imxiomux at axi
 file	arch/arm/imx/imx51_iomux.c		imxiomux
 
-# LCD controller
-# device	lcd : bus_dma_generic, wsemuldisplaydev, rasops16, rasops8, rasops4, rasops_rotation
-# file	arch/arm/imx/imx31_lcd.c		lcd		needs-flag
-# defflag	opt_imx31_lcd.h				IMXLCDCONSOLE
+# IPU v3 controller
+device	ipu : bus_dma_generic, wsemuldisplaydev, rasops16, rasops8, rasops4, rasops_rotation, vcons
+file	arch/arm/imx/imx51_ipuv3.c	ipu	 needs-flag
+defflag	opt_imx51_ipuv3.h		IMXIPUCONSOLE
+defparam opt_imx51_ipuv3.h		IPUV3_DEBUG
 
 # iMX M3IF - Multi Master Memory Interface
 # iMX ESDCTL/MDDRC - Enhanced SDRAM/LPDDR memory controller
@@ -86,8 +87,8 @@
 # file	arch/arm/imx/wdc_axi.c			wdc_axi
 
 # SD host controller for SD/MMC
-# device	imxmci: sdmmcbus
-# file	arch/arm/imx/imx51_mci.c		imxmci
+attach	sdhc at axi with sdhc_axi
+file	arch/arm/imx/imx51_esdhc.c		sdhc_axi
 
 # iic Controler
 # device	imxi2c: i2cbus
--- a/sys/arch/arm/imx/imx31_clock.c	Tue Apr 17 19:25:17 2012 +0000
+++ b/sys/arch/arm/imx/imx31_clock.c	Sun Apr 29 23:04:36 2012 +0000
@@ -1,4 +1,4 @@
-/*	$NetBSD: imx31_clock.c,v 1.3 2011/07/01 20:27:50 dyoung Exp $ */
+/*	$NetBSD: imx31_clock.c,v 1.3.6.1 2012/04/29 23:04:37 mrg Exp $ */
 /*
  * Copyright (c) 2009,2010  Genetec corp.  All rights reserved.
  * Written by Hashimoto Kenichi for Genetec corp.
@@ -106,6 +106,8 @@
 		aipsa->aipsa_size, 0, &sc->sc_ioh)) {
 		panic("%s: Cannot map registers", device_xname(self));
 	}
+
+	sc->sc_clksrc = EPITCR_CLKSRC_HIGH;
 }
 
 int
--- a/sys/arch/arm/imx/imx51_axi.c	Tue Apr 17 19:25:17 2012 +0000
+++ b/sys/arch/arm/imx/imx51_axi.c	Sun Apr 29 23:04:36 2012 +0000
@@ -1,4 +1,4 @@
-/*	$NetBSD: imx51_axi.c,v 1.2 2010/11/30 13:05:27 bsh Exp $	*/
+/*	$NetBSD: imx51_axi.c,v 1.2.14.1 2012/04/29 23:04:37 mrg Exp $	*/
 
 /*-
  * Copyright (c) 2010 SHIMIZU Ryo <ryo@nerv.org>
@@ -27,7 +27,7 @@
  */
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: imx51_axi.c,v 1.2 2010/11/30 13:05:27 bsh Exp $");
+__KERNEL_RCSID(0, "$NetBSD: imx51_axi.c,v 1.2.14.1 2012/04/29 23:04:37 mrg Exp $");
 
 #include <sys/param.h>
 #include <sys/bus.h>
@@ -38,6 +38,7 @@
 #include <arm/imx/imx51reg.h>
 #include <arm/imx/imx51var.h>
 
+#include "bus_dma_generic.h"
 #include "locators.h"
 
 struct axi_softc {
@@ -102,6 +103,7 @@
 
 	if ((strcmp(cf->cf_name, "tzic") != 0) &&
 	    (strcmp(cf->cf_name, "imxuart") != 0) &&
+	    (strcmp(cf->cf_name, "imxccm") != 0) &&
 	    (strcmp(cf->cf_name, "imxgpio") != 0))
 		return 0;
 
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/sys/arch/arm/imx/imx51_ccm.c	Sun Apr 29 23:04:36 2012 +0000
@@ -0,0 +1,425 @@
+/*	$NetBSD: imx51_ccm.c,v 1.1.2.2 2012/04/29 23:04:38 mrg Exp $	*/
+/*
+ * Copyright (c) 2010, 2011, 2012  Genetec Corporation.  All rights reserved.
+ * Written by Hashimoto Kenichi for Genetec Corporation.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY GENETEC CORPORATION ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL GENETEC CORPORATION
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ * Clock Controller Module (CCM)
+ */
+
+#include <sys/cdefs.h>
+__KERNEL_RCSID(0, "$NetBSD: imx51_ccm.c,v 1.1.2.2 2012/04/29 23:04:38 mrg Exp $");
+
+#include <sys/types.h>
+#include <sys/time.h>
+#include <sys/bus.h>
+#include <sys/device.h>
+#include <sys/param.h>
+
+#include <machine/cpu.h>
+
+#include <arm/imx/imx51_ccmvar.h>
+#include <arm/imx/imx51_ccmreg.h>
+#include <arm/imx/imx51_dpllreg.h>
+
+#include <arm/imx/imx51var.h>
+#include <arm/imx/imx51reg.h>
+
+#include "opt_imx51clk.h"
+#include "locators.h"
+
+//#define	IMXCCMDEBUG
+
+#ifndef	IMX51_OSC_FREQ
+#define	IMX51_OSC_FREQ	(24 * 1000 * 1000)	/* 24MHz */
+#endif
+
+struct imxccm_softc {
+	device_t	sc_dev;
+	bus_space_tag_t	sc_iot;
+	bus_space_handle_t	sc_ioh;
+
+	struct {
+		bus_space_handle_t pll_ioh;
+		u_int pll_freq;
+	} sc_pll[IMX51_N_DPLLS];
+};
+
+struct imxccm_softc *ccm_softc;
+
+static uint64_t imx51_get_pll_freq(u_int);
+
+static int imxccm_match(device_t, cfdata_t, void *);
+static void imxccm_attach(device_t, device_t, void *);
+
+CFATTACH_DECL_NEW(imxccm, sizeof(struct imxccm_softc),
+    imxccm_match, imxccm_attach, NULL, NULL);
+
+static int
+imxccm_match(device_t parent, cfdata_t cfdata, void *aux)
+{
+	struct axi_attach_args *aa = aux;
+
+	if (aa->aa_addr == CCMC_BASE)
+		return 1;
+
+	return 0;
+}
+
+static void
+imxccm_attach(device_t parent, device_t self, void *aux)
+{
+	struct axi_attach_args *aa = aux;
+	bus_space_tag_t iot = aa->aa_iot;
+	int i;
+
+	ccm_softc = device_private(self);
+	ccm_softc->sc_dev = self;
+	ccm_softc->sc_iot = iot;
+
+	if (bus_space_map(iot, aa->aa_addr, CCMC_SIZE, 0,
+		&ccm_softc->sc_ioh)) {
+		aprint_error(": can't map\n");
+		return;
+	}
+
+	for (i=1; i <= IMX51_N_DPLLS; ++i) {
+		if (bus_space_map(iot, DPLL_BASE(i), DPLL_SIZE, 0,
+			&ccm_softc->sc_pll[i-1].pll_ioh)) {
+			aprint_error(": can't map\n");
+			return;
+		}
+	}
+
+	aprint_normal(": Clock control module\n");
+	aprint_naive("\n");
+
+	imx51_get_pll_freq(1);
+	imx51_get_pll_freq(2);
+	imx51_get_pll_freq(3);
+
+
+	aprint_verbose_dev(self, "CPU clock=%d, UART clock=%d\n",
+	    imx51_get_clock(IMX51CLK_ARM_ROOT),
+	    imx51_get_clock(IMX51CLK_UART_CLK_ROOT));
+	aprint_verbose_dev(self, 
+	    "mainbus clock=%d, ahb clock=%d ipg clock=%d perclk=%d\n",
+	    imx51_get_clock(IMX51CLK_MAIN_BUS_CLK),
+	    imx51_get_clock(IMX51CLK_AHB_CLK_ROOT),
+	    imx51_get_clock(IMX51CLK_IPG_CLK_ROOT),
+	    imx51_get_clock(IMX51CLK_PERCLK_ROOT));
+}
+
+
+u_int
+imx51_get_clock(enum imx51_clock clk)
+{
+	bus_space_tag_t iot = ccm_softc->sc_iot;
+	bus_space_handle_t ioh = ccm_softc->sc_ioh;
+
+	u_int freq;
+	u_int sel;
+	uint32_t cacrr;	/* ARM clock root register */
+	uint32_t ccsr;
+	uint32_t cscdr1;
+	uint32_t cscmr1;
+	uint32_t cbcdr;
+	uint32_t cbcmr;
+	uint32_t cdcr;
+
+	switch (clk) {
+	case IMX51CLK_PLL1:
+	case IMX51CLK_PLL2:
+	case IMX51CLK_PLL3:
+		return ccm_softc->sc_pll[clk-IMX51CLK_PLL1].pll_freq;
+	case IMX51CLK_PLL1SW:
+		ccsr = bus_space_read_4(iot, ioh, CCMC_CCSR);
+		if ((ccsr & CCSR_PLL1_SW_CLK_SEL) == 0)
+			return ccm_softc->sc_pll[1-1].pll_freq;
+		/* step clock */
+		/* FALLTHROUGH */
+	case IMX51CLK_PLL1STEP:
+		ccsr = bus_space_read_4(iot, ioh, CCMC_CCSR);
+		switch ((ccsr & CCSR_STEP_SEL_MASK) >> CCSR_STEP_SEL_SHIFT) {
+		case 0:
+			return imx51_get_clock(IMX51CLK_LP_APM);
+		case 1:
+			return 0; /* XXX PLL bypass clock */
+		case 2:
+			return ccm_softc->sc_pll[2-1].pll_freq /
+			    (1 + ((ccsr & CCSR_PLL2_DIV_PODF_MASK) >>
+				CCSR_PLL2_DIV_PODF_SHIFT));
+		case 3:
+			return ccm_softc->sc_pll[3-1].pll_freq /
+			    (1 + ((ccsr & CCSR_PLL3_DIV_PODF_MASK) >>
+				CCSR_PLL3_DIV_PODF_SHIFT));
+		}
+		/*NOTREACHED*/
+	case IMX51CLK_PLL2SW:
+		ccsr = bus_space_read_4(iot, ioh, CCMC_CCSR);
+		if ((ccsr & CCSR_PLL2_SW_CLK_SEL) == 0)
+			return imx51_get_clock(IMX51CLK_PLL2);
+		return 0; /* XXX PLL2 bypass clk */
+	case IMX51CLK_PLL3SW:
+		ccsr = bus_space_read_4(iot, ioh, CCMC_CCSR);
+		if ((ccsr & CCSR_PLL3_SW_CLK_SEL) == 0)
+			return imx51_get_clock(IMX51CLK_PLL3);
+		return 0; /* XXX PLL3 bypass clk */
+
+	case IMX51CLK_LP_APM:
+		ccsr = bus_space_read_4(iot, ioh, CCMC_CCSR);
+		return (ccsr & CCSR_LP_APM) ?
+			    imx51_get_clock(IMX51CLK_FPM) : IMX51_OSC_FREQ;
+
+	case IMX51CLK_ARM_ROOT:
+		freq = imx51_get_clock(IMX51CLK_PLL1SW);
+		cacrr = bus_space_read_4(iot, ioh, CCMC_CACRR);
+		return freq / (cacrr + 1);
+
+		/* ... */
+	case IMX51CLK_MAIN_BUS_CLK_SRC:
+		cbcdr = bus_space_read_4(iot, ioh, CCMC_CBCDR);
+		if ((cbcdr & CBCDR_PERIPH_CLK_SEL) == 0)
+			freq = imx51_get_clock(IMX51CLK_PLL2SW);
+		else {
+			freq = 0;
+			cbcmr = bus_space_read_4(iot, ioh,  CCMC_CBCMR);
+			switch ((cbcmr & CBCMR_PERIPH_APM_SEL_MASK) >>
+				CBCMR_PERIPH_APM_SEL_SHIFT) {
+			case 0:
+				freq = imx51_get_clock(IMX51CLK_PLL1SW);
+				break;
+			case 1:
+				freq = imx51_get_clock(IMX51CLK_PLL3SW);
+				break;
+			case 2:
+				freq = imx51_get_clock(IMX51CLK_LP_APM);
+				break;
+			case 3:
+				/* XXX: error */
+				break;
+			}
+		}
+		return freq;
+	case IMX51CLK_MAIN_BUS_CLK:
+		freq = imx51_get_clock(IMX51CLK_MAIN_BUS_CLK_SRC);
+		cdcr = bus_space_read_4(iot, ioh, CCMC_CDCR);
+		return freq / (cdcr & CDCR_PERIPH_CLK_DVFS_PODF_MASK) >>
+			CDCR_PERIPH_CLK_DVFS_PODF_SHIFT;
+	case IMX51CLK_AHB_CLK_ROOT:
+		freq = imx51_get_clock(IMX51CLK_MAIN_BUS_CLK);
+		cbcdr = bus_space_read_4(iot, ioh, CCMC_CBCDR);
+		return freq / (1 + ((cbcdr & CBCDR_AHB_PODF_MASK) >>
+				    CBCDR_AHB_PODF_SHIFT));
+	case IMX51CLK_IPG_CLK_ROOT:
+		freq = imx51_get_clock(IMX51CLK_AHB_CLK_ROOT);
+		cbcdr = bus_space_read_4(iot, ioh, CCMC_CBCDR);
+		return freq / (1 + ((cbcdr & CBCDR_IPG_PODF_MASK) >>
+				    CBCDR_IPG_PODF_SHIFT));
+
+	case IMX51CLK_PERCLK_ROOT:
+		cbcmr = bus_space_read_4(iot, ioh, CCMC_CBCMR);
+		if (cbcmr & CBCMR_PERCLK_IPG_SEL)
+			return imx51_get_clock(IMX51CLK_IPG_CLK_ROOT);
+		if (cbcmr & CBCMR_PERCLK_LP_APM_SEL)
+			freq = imx51_get_clock(IMX51CLK_LP_APM);
+		else
+			freq = imx51_get_clock(IMX51CLK_MAIN_BUS_CLK_SRC);
+		cbcdr = bus_space_read_4(iot, ioh, CCMC_CBCDR);
+
+#ifdef IMXCCMDEBUG
+		printf("cbcmr=%x cbcdr=%x\n", cbcmr, cbcdr);
+#endif
+
+		freq /= 1 + ((cbcdr & CBCDR_PERCLK_PRED1_MASK) >>
+			CBCDR_PERCLK_PRED1_SHIFT);
+		freq /= 1 + ((cbcdr & CBCDR_PERCLK_PRED2_MASK) >>
+			CBCDR_PERCLK_PRED2_SHIFT);
+		freq /= 1 + ((cbcdr & CBCDR_PERCLK_PODF_MASK) >>
+			CBCDR_PERCLK_PODF_SHIFT);
+		return freq;
+	case IMX51CLK_UART_CLK_ROOT:
+		cscdr1 = bus_space_read_4(iot, ioh, CCMC_CSCDR1);
+		cscmr1 = bus_space_read_4(iot, ioh, CCMC_CSCMR1);
+
+#ifdef IMXCCMDEBUG
+		printf("cscdr1=%x cscmr1=%x\n", cscdr1, cscmr1);
+#endif
+
+		sel = (cscmr1 & CSCMR1_UART_CLK_SEL_MASK) >>
+		    CSCMR1_UART_CLK_SEL_SHIFT;
+
+		freq = 0; /* shut up GCC */
+		switch (sel) {
+		case 0:
+		case 1:
+		case 2:
+			freq = imx51_get_clock(IMX51CLK_PLL1SW + sel);
+			break;
+		case 3:
+			freq = imx51_get_clock(IMX51CLK_LP_APM);
+			break;
+		}
+
+		return freq / (1 + ((cscdr1 & CSCDR1_UART_CLK_PRED_MASK) >>
+			CSCDR1_UART_CLK_PRED_SHIFT)) /
+		    (1 + ((cscdr1 & CSCDR1_UART_CLK_PODF_MASK) >>
+			CSCDR1_UART_CLK_PODF_SHIFT));
+	case IMX51CLK_IPU_HSP_CLK_ROOT:
+		freq = 0;
+		cbcmr = bus_space_read_4(iot, ioh,  CCMC_CBCMR);
+		switch ((cbcmr & CBCMR_IPU_HSP_CLK_SEL_MASK) >>
+				CBCMR_IPU_HSP_CLK_SEL_SHIFT) {
+			case 0:
+				freq = imx51_get_clock(IMX51CLK_ARM_AXI_A_CLK);
+				break;
+			case 1:
+				freq = imx51_get_clock(IMX51CLK_ARM_AXI_B_CLK);
+				break;
+			case 2:
+				freq = imx51_get_clock(
+					IMX51CLK_EMI_SLOW_CLK_ROOT);
+				break;
+			case 3:
+				freq = imx51_get_clock(IMX51CLK_AHB_CLK_ROOT);
+				break;
+			}
+		return freq;
+	default:
+		aprint_error_dev(ccm_softc->sc_dev,
+		    "clock %d: not supported yet\n", clk);
+		return 0;
+	}
+}
+
+
+static uint64_t
+imx51_get_pll_freq(u_int pll_no)
+{
+	uint32_t dp_ctrl;
+	uint32_t dp_op;
+	uint32_t dp_mfd;
+	uint32_t dp_mfn;
+	uint32_t mfi;
+	int32_t mfn;
+	uint32_t mfd;
+	uint32_t pdf;
+	uint32_t ccr;
+	uint64_t freq = 0;
+	u_int ref = 0;
+	bus_space_tag_t iot = ccm_softc->sc_iot;
+	bus_space_handle_t ioh = ccm_softc->sc_pll[pll_no-1].pll_ioh;
+
+	KASSERT(1 <= pll_no && pll_no <= IMX51_N_DPLLS);
+
+	dp_ctrl = bus_space_read_4(iot, ioh, DPLL_DP_CTL);
+
+	if (dp_ctrl & DP_CTL_HFSM) {
+		dp_op = bus_space_read_4(iot, ioh, DPLL_DP_HFS_OP);
+		dp_mfd = bus_space_read_4(iot, ioh, DPLL_DP_HFS_MFD);
+		dp_mfn = bus_space_read_4(iot, ioh, DPLL_DP_HFS_MFN);
+	} else {
+		dp_op = bus_space_read_4(iot, ioh, DPLL_DP_OP);
+		dp_mfd = bus_space_read_4(iot, ioh, DPLL_DP_MFD);
+		dp_mfn = bus_space_read_4(iot, ioh, DPLL_DP_MFN);
+	}
+
+	pdf = dp_op & DP_OP_PDF_MASK;
+	mfi = max(5, (dp_op & DP_OP_MFI_MASK) >> DP_OP_MFI_SHIFT);
+	mfd = dp_mfd;
+	if (dp_mfn & __BIT(26))
+		/* 27bit signed value */
+		mfn = (int32_t)(__BITS(31,27) | dp_mfn);
+	else
+		mfn = dp_mfn;
+
+	switch (dp_ctrl &  DP_CTL_REF_CLK_SEL_MASK) {
+	case DP_CTL_REF_CLK_SEL_COSC:
+		/* Internal Oscillator */
+		ref = IMX51_OSC_FREQ;
+		break;
+	case DP_CTL_REF_CLK_SEL_FPM:
+		ccr = bus_space_read_4(iot, ccm_softc->sc_ioh, CCMC_CCR);
+		if (ccr & CCR_FPM_MULT)
+			ref = IMX51_CKIL_FREQ * 1024;
+		else
+			ref = IMX51_CKIL_FREQ * 512;
+		break;
+	default:
+		ref = 0;
+	}
+
+
+	if (dp_ctrl & DP_CTL_REF_CLK_DIV)
+		ref /= 2;
+
+#if 0
+	if (dp_ctrl & DP_CTL_DPDCK0_2_EN)
+		ref *= 2;
+
+	ref /= (pdf + 1);
+	freq = ref * mfn;
+	freq /= (mfd + 1);
+	freq = (ref * mfi) + freq;
+#endif
+
+	ref *= 4;
+	freq = (int64_t)ref * mfi + (int64_t)ref * mfn / (mfd + 1);
+	freq /= pdf + 1;
+
+	if (!(dp_ctrl & DP_CTL_DPDCK0_2_EN))
+		freq /= 2;
+
+
+#ifdef IMXCCMDEBUG
+	printf("dp_ctl: %08x ", dp_ctrl);
+	printf("pdf: %3d ", pdf);
+	printf("mfi: %3d ", mfi);
+	printf("mfd: %3d ", mfd);
+	printf("mfn: %3d ", mfn);
+	printf("pll: %lld\n", freq);
+#endif
+
+	ccm_softc->sc_pll[pll_no-1].pll_freq = freq;
+
+	return freq;
+}
+
+void
+imx51_clk_gating(int clk_src, int mode)
+{
+	bus_space_tag_t iot = ccm_softc->sc_iot;
+	bus_space_handle_t ioh = ccm_softc->sc_ioh;
+	uint32_t group = CCMR_CCGR_MODULE(clk_src);
+	uint32_t field = clk_src % CCMR_CCGR_NSOURCE;
+	uint32_t reg;
+	uint32_t bit;
+
+	bit = (mode << field * 2);
+	reg = bus_space_read_4(iot, ioh, CCMC_CCGR(group));
+	reg &= ~(0x03 << field * 2);
+	reg |= bit;
+	bus_space_write_4(iot, ioh, CCMC_CCGR(group), reg);
+}
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/sys/arch/arm/imx/imx51_ccmreg.h	Sun Apr 29 23:04:36 2012 +0000
@@ -0,0 +1,199 @@
+/*	$NetBSD: imx51_ccmreg.h,v 1.1.2.2 2012/04/29 23:04:38 mrg Exp $	*/
+/*
+ * Copyright (c) 2011, 2012  Genetec Corporation.  All rights reserved.
+ * Written by Hashimoto Kenichi for Genetec Corporation.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY GENETEC CORPORATION ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL GENETEC CORPORATION
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef	_IMX51_CCMREG_H
+#define	_IMX51_CCMREG_H
+
+#include <sys/cdefs.h>
+
+/* register offset address */
+
+#define	CCMC_BASE	0x73fd4000
+#define	CCMC_CCR	0x0000
+#define	 CCR_FPM_MULT	__BIT(12)
+#define	CCMC_CCDR	0x0004
+#define	CCMC_CSR	0x0008
+#define	CCMC_CCSR	0x000c
+#define	 CCSR_LP_APM	__BIT(9)
+#define	 CCSR_STEP_SEL_SHIFT	7
+#define	 CCSR_STEP_SEL_MASK	__BITS(8,CCSR_STEP_SEL_SHIFT)
+#define	 CCSR_PLL2_DIV_PODF_SHIFT	5
+#define	 CCSR_PLL2_DIV_PODF_MASK	__BITS(6, CCSR_PLL2_DIV_PODF_SHIFT)
+#define	 CCSR_PLL3_DIV_PODF_SHIFT	3
+#define	 CCSR_PLL3_DIV_PODF_MASK	__BITS(4, CCSR_PLL2_DIV_PODF_SHIFT)
+#define	 CCSR_PLL1_SW_CLK_SEL	__BIT(2)
+#define	 CCSR_PLL2_SW_CLK_SEL	__BIT(1)
+#define	 CCSR_PLL3_SW_CLK_SEL	__BIT(0)
+#define	CCMC_CACRR	0x0010
+#define	CCMC_CBCDR	0x0014
+#define	 CBCDR_DDR_HIGH_FREQ_CLK_SEL	__BIT(30)
+#define	 CBCDR_DDR_CLK_PODF_SHIFT	27
+#define	 CBCDR_DDR_CLK_PODF_MASK	__BITS(29, CBCDR_DDR_CLK_PODF_SHIFT)
+#define	 CBCDR_EMI_CLK_SEL		__BIT(26)
+#define	 CBCDR_PERIPH_CLK_SEL	__BIT(25)
+#define	 CBCDR_EMI_SLOW_PODF_SHIFT	22
+#define	 CBCDR_EMI_SLOW_PODF_MASK	__BITS(24, CBCDR_EMI_SLOW_PODF_SHIFT)
+#define	 CBCDR_AXI_B_PODF_SHIFT		19
+#define	 CBCDR_AXI_B_PODF_MASK		__BITS(21, CBCDR_AXI_B_PODF_SHIFT)
+#define	 CBCDR_AXI_A_PODF_SHIFT		16
+#define	 CBCDR_AXI_A_PODF_MASK		__BITS(28, CBCDR_AXI_A_PODF_SHIFT)
+#define	 CBCDR_NFC_PODF_SHIFT		13
+#define	 CBCDR_NFC_PODF_MASK		__BITS(15, CBCDR_AXI_A_PODF_SHIFT)
+#define	 CBCDR_AHB_PODF_SHIFT		10
+#define	 CBCDR_AHB_PODF_MASK		__BITS(12, CBCDR_AHB_PODF_SHIFT)
+#define	 CBCDR_IPG_PODF_SHIFT		8
+#define	 CBCDR_IPG_PODF_MASK		__BITS(9, CBCDR_IPG_PODF_SHIFT)
+#define	 CBCDR_PERCLK_PRED1_SHIFT	6
+#define	 CBCDR_PERCLK_PRED1_MASK	__BITS(7, CBCDR_PERCLK_PRED1_SHIFT)
+#define	 CBCDR_PERCLK_PRED2_SHIFT	3
+#define	 CBCDR_PERCLK_PRED2_MASK	__BITS(5, CBCDR_PERCLK_PRED2_SHIFT)
+#define	 CBCDR_PERCLK_PODF_SHIFT	0
+#define	 CBCDR_PERCLK_PODF_MASK 	__BITS(2, CBCDR_PERCLK_PODF_SHIFT)
+#define	CCMC_CBCMR	0x0018
+#define	 CBCMR_PERIPH_APM_SEL_SHIFT	12
+#define	 CBCMR_PERIPH_APM_SEL_MASK	__BITS(13, CBCMR_PERIPH_APM_SEL_SHIFT)
+#define	 CBCMR_IPU_HSP_CLK_SEL_SHIFT	6
+#define	 CBCMR_IPU_HSP_CLK_SEL_MASK	__BITS(7, CBCMR_IPU_HSP_CLK_SEL_SHIFT)
+#define	 CBCMR_PERCLK_LP_APM_SEL	__BIT(1)
+#define	 CBCMR_PERCLK_IPG_SEL		__BIT(0)
+#define	CCMC_CSCMR1	0x001c
+#define	 CSCMR1_UART_CLK_SEL_SHIFT	24
+#define	 CSCMR1_UART_CLK_SEL_MASK	__BITS(25, CSCMR1_UART_CLK_SEL_SHIFT)
+#define	CCMC_CSCMR2	0x0020
+#define	CCMC_CSCDR1	0x0024
+#define	 CSCDR1_UART_CLK_PRED_SHIFT	3
+#define	 CSCDR1_UART_CLK_PRED_MASK	__BITS(5, CSCDR1_UART_CLK_PRED_SHIFT)
+#define	 CSCDR1_UART_CLK_PODF_SHIFT	0
+#define	 CSCDR1_UART_CLK_PODF_MASK	__BITS(2, CSCDR1_UART_CLK_PODF_SHIFT)
+#define	CCMC_CS1CDR	0x0028
+#define	CCMC_CS2CDR	0x002c
+#define	CCMC_CDCDR	0x0030
+#define	CCMC_CSCDR2	0x0038
+#define	CCMC_CSCDR3	0x003c
+#define	CCMC_CSCDR4	0x0040
+#define	CCMC_CWDR	0x0044
+#define	CCMC_CDHIPR	0x0048
+#define	CCMC_CDCR	0x004c
+#define	 CDCR_PERIPH_CLK_DVFS_PODF_SHIFT	0
+#define	 CDCR_PERIPH_CLK_DVFS_PODF_MASK 	\
+		__BITS(1,CDCR_PERIPH_CLK_DVFS_PODF_SHIFT)
+#define	CCMC_CTOR	0x0050
+#define	CCMC_CLPCR	0x0054
+#define	CCMC_CISR	0x0058
+#define	CCMC_CIMR	0x005c
+#define	CCMC_CCOSR	0x0060
+#define	CCMC_CGPR	0x0064
+#define	CCMC_CCGR(n)	(0x0068 + (n) * 4)
+#define	CCMC_CMEOR	0x0084
+
+#define	CCMC_SIZE	0x88
+
+/* CCGR Clock Gate Register */
+
+#define	CCMR_CCGR_NSOURCE	16
+#define	CCMR_CCGR_NGROUPS	7
+#define	CCMR_CCGR_MODULE(clk)	((clk) / CCMR_CCGR_NSOURCE)
+#define	__CCGR_NUM(a, b)	((a) * 16 + (b))
+
+#define	CCGR_ARM_BUS_CLK		__CCGR_NUM(0, 0)
+#define	CCGR_ARM_AXI_CLK		__CCGR_NUM(0, 1)
+#define	CCGR_ARM_DEBUG_CLK		__CCGR_NUM(0, 2)
+#define	CCGR_TZIC_CLK			__CCGR_NUM(0, 3)
+#define	CCGR_DAP_CLK			__CCGR_NUM(0, 4)
+#define	CCGR_TPIU_CLK			__CCGR_NUM(0, 5)
+#define	CCGR_CTI2_CLK			__CCGR_NUM(0, 6)
+#define	CCGR_CTI3_CLK			__CCGR_NUM(0, 7)
+#define	CCGR_AHBMUX1_CLK		__CCGR_NUM(0, 8)
+#define	CCGR_AHBMUX2_CLK		__CCGR_NUM(0, 9)
+#define	CCGR_ROMCP_CLK			__CCGR_NUM(0, 10)
+#define	CCGR_ROM_CLK			__CCGR_NUM(0, 11)
+#define	CCGR_AIPS_TZ1_CLK		__CCGR_NUM(0, 12)
+#define	CCGR_AIPS_TZ2_CLK		__CCGR_NUM(0, 13)
+#define	CCGR_AHB_MAX_CLK		__CCGR_NUM(0, 14)
+#define	CCGR_IIM_CLK			__CCGR_NUM(0, 15)
+#define	CCGR_TMAX1_CLK			__CCGR_NUM(1, 0)
+#define	CCGR_TMAX2_CLK			__CCGR_NUM(1, 1)
+#define	CCGR_TMAX3_CLK			__CCGR_NUM(1, 2)
+#define	CCGR_UART1_CLK			__CCGR_NUM(1, 3)
+#define	CCGR_UART1_SERIAL_CLK		__CCGR_NUM(1, 4)
+#define	CCGR_UART2_CLK			__CCGR_NUM(1, 5)
+#define	CCGR_UART2_SERIAL_CLK		__CCGR_NUM(1, 6)
+#define	CCGR_UART3_CLK			__CCGR_NUM(1, 7)
+#define	CCGR_UART3_SERIAL_CLK		__CCGR_NUM(1, 8)
+#define	CCGR_I2C1_SERIAL_CLK		__CCGR_NUM(1, 9)
+#define	CCGR_I2C2_SERIAL_CLK		__CCGR_NUM(1, 10)
+#define	CCGR_HSI2C_CLK			__CCGR_NUM(1, 11)
+#define	CCGR_HSI2C_SERIAL_CLK		__CCGR_NUM(1, 12)
+#define	CCGR_FIRI_CLK			__CCGR_NUM(1, 13)
+#define	CCGR_FIRI_SERIAL_CLK		__CCGR_NUM(1, 14)
+#define	CCGR_SCC_CLK			__CCGR_NUM(1, 15)
+#define	CCGR_USB_PHY_CLK		__CCGR_NUM(2, 0)
+#define	CCGR_EPIT1_CLK			__CCGR_NUM(2, 1)
+#define	CCGR_EPIT1_SERIAL_CLK		__CCGR_NUM(2, 2)
+#define	CCGR_EPIT2_CLK			__CCGR_NUM(2, 3)
+#define	CCGR_ESDHC1_CLK			__CCGR_NUM(3, 0)
+#define	CCGR_ESDHC1_SERIAL_CLK		__CCGR_NUM(3, 1)
+#define	CCGR_ESDHC2_CLK			__CCGR_NUM(3, 2)
+#define	CCGR_ESDHC2_SERIAL_CLK		__CCGR_NUM(3, 3)
+#define	CCGR_ESDHC3_CLK			__CCGR_NUM(3, 4)
+#define	CCGR_ESDHC3_SERIAL_CLK		__CCGR_NUM(3, 5)
+#define	CCGR_ESDHC4_CLK			__CCGR_NUM(3, 6)
+#define	CCGR_ESDHC4_SERIAL_CLK		__CCGR_NUM(3, 7)
+#define	CCGR_SSI1_CLK			__CCGR_NUM(3, 8)
+#define	CCGR_SSI1_SERIAL_CLK		__CCGR_NUM(3, 9)
+#define	CCGR_SSI2_CLK			__CCGR_NUM(3, 10)
+#define	CCGR_SSI2_SERIAL_CLK		__CCGR_NUM(3, 11)
+#define	CCGR_SSI3_CLK			__CCGR_NUM(3, 12)
+#define	CCGR_SSI3_SERIAL_CLK		__CCGR_NUM(3, 13)
+#define	CCGR_SSI_EXT1_CLK		__CCGR_NUM(3, 14)
+#define	CCGR_SSI_EXT2_CLK		__CCGR_NUM(3, 15)
+#define	CCGR_PATA_CLK			__CCGR_NUM(4, 0)
+#define	CCGR_SIM_CLK			__CCGR_NUM(4, 1)
+#define	CCGR_SIM_SERIAL_CLK		__CCGR_NUM(4, 2)
+#define	CCGR_SAHARA_CLK			__CCGR_NUM(4, 3)
+#define	CCGR_RTIC_CLK			__CCGR_NUM(4, 4)
+#define	CCGR_ECSPI1_CLK			__CCGR_NUM(4, 5)
+#define	CCGR_ECSPI1_SERIAL_CLK		__CCGR_NUM(4, 6)
+#define	CCGR_ECSPI2_CLK			__CCGR_NUM(4, 7)
+#define	CCGR_ECSPI2_SERIAL_CLK		__CCGR_NUM(4, 8)
+#define	CCGR_CSPI_CLK			__CCGR_NUM(4, 9)
+#define	CCGR_SRTC_CLK			__CCGR_NUM(4, 10)
+#define	CCGR_SDMA_CLK			__CCGR_NUM(4, 11)
+#define	CCGR_SPBA_CLK			__CCGR_NUM(5, 0)
+#define	CCGR_GPU_CLK			__CCGR_NUM(5, 1)
+#define	CCGR_GARB_CLK			__CCGR_NUM(5, 2)
+#define	CCGR_VPU_CLK			__CCGR_NUM(5, 3)
+#define	CCGR_VPU_SERIAL_CLK		__CCGR_NUM(5, 4)
+#define	CCGR_IPU_CLK			__CCGR_NUM(5, 5)
+#define	CCGR_EMI_GARB_CLK		__CCGR_NUM(6, 0)
+#define	CCGR_IPU_DI0_CLK		__CCGR_NUM(6, 1)
+#define	CCGR_IPU_DI1_CLK		__CCGR_NUM(6, 2)
+#define	CCGR_GPU2D_CLK			__CCGR_NUM(6, 3)
+#define	CCGR_SLIMBUS_CLK		__CCGR_NUM(6, 4)
+#define	CCGR_SLIMBUS_SERIAL_CLK		__CCGR_NUM(6, 5)
+
+#endif /* _IMX51_CCMREG_H */
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/sys/arch/arm/imx/imx51_ccmvar.h	Sun Apr 29 23:04:36 2012 +0000
@@ -0,0 +1,78 @@
+/*	$NetBSD: imx51_ccmvar.h,v 1.1.2.2 2012/04/29 23:04:38 mrg Exp $	*/
+/*
+ * Copyright (c) 2012  Genetec Corporation.  All rights reserved.
+ * Written by Hashimoto Kenichi for Genetec Corporation.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY GENETEC CORPORATION ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL GENETEC CORPORATION
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef	_ARM_IMX_IMX51_CCMVAR_H_
+#define	_ARM_IMX_IMX51_CCMVAR_H_
+
+enum imx51_clock {
+	IMX51CLK_FPM,
+	IMX51CLK_PLL1,
+	IMX51CLK_PLL2,
+	IMX51CLK_PLL3,
+	IMX51CLK_PLL1SW,
+	IMX51CLK_PLL2SW,
+	IMX51CLK_PLL3SW,
+	IMX51CLK_PLL1STEP,
+	IMX51CLK_LP_APM,
+	IMX51CLK_ARM_ROOT,
+	IMX51CLK_MAIN_BUS_CLK_SRC,	/* XXX */
+	IMX51CLK_MAIN_BUS_CLK,
+	IMX51CLK_EMI_SLOW_CLK_ROOT,
+	IMX51CLK_ENFC_CLK_ROOT,
+	IMX51CLK_AHB_CLK_ROOT,
+	IMX51CLK_IPG_CLK_ROOT,
+	IMX51CLK_PERCLK_ROOT,
+	IMX51CLK_DDR_CLK_ROOT,
+	IMX51CLK_ARM_AXI_CLK_ROOT,
+	IMX51CLK_ARM_AXI_A_CLK,
+	IMX51CLK_ARM_AXI_B_CLK,
+	IMX51CLK_IPU_HSP_CLK_ROOT,
+	IMX51CLK_CKIL_SYNC_CLK_ROOT,
+	IMX51CLK_USBOH3_CLK_ROOT,
+	IMX51CLK_ESDHC1_CLK_ROOT,
+	IMX51CLK_ESDHC2_CLK_ROOT,
+	IMX51CLK_ESDHC3_CLK_ROOT,
+	IMX51CLK_UART_CLK_ROOT,
+	IMX51CLK_SSI1_CLK_ROOT,
+	IMX51CLK_SSI2_CLK_ROOT,
+	IMX51CLK_SSI_EXT1_CLK_ROOT,
+	IMX51CLK_SSI_EXT2_CLK_ROOT,
+	IMX51CLK_USB_PHY_CLK_ROOT,
+	IMX51CLK_TVE_216_54_CLK_ROOT,
+	IMX51CLK_DI_CLK_ROOT,
+	IMX51CLK_SPDIF0_CLK_ROOT,
+	IMX51CLK_SPDIF1_CLK_ROOT,
+	IMX51CLK_CSPI_CLK_ROOT,
+	IMX51CLK_WRCK_CLK_ROOT,
+	IMX51CLK_LPSR_CLK_ROOT,
+	IMX51CLK_PGC_CLK_ROOT
+};
+
+u_int imx51_get_clock(enum imx51_clock);
+void imx51_clk_gating(int, int);
+
+#endif	/* _ARM_IMX_IMX51_CCMVAR_H_ */
--- a/sys/arch/arm/imx/imx51_clock.c	Tue Apr 17 19:25:17 2012 +0000
+++ b/sys/arch/arm/imx/imx51_clock.c	Sun Apr 29 23:04:36 2012 +0000
@@ -1,4 +1,4 @@
-/*	$NetBSD: imx51_clock.c,v 1.2 2011/07/01 20:27:50 dyoung Exp $ */
+/*	$NetBSD: imx51_clock.c,v 1.2.6.1 2012/04/29 23:04:38 mrg Exp $ */
 /*
  * Copyright (c) 2009  Genetec corp.  All rights reserved.
  * Written by Hashimoto Kenichi for Genetec corp.
@@ -25,7 +25,7 @@
  * POSSIBILITY OF SUCH DAMAGE.
  */
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: imx51_clock.c,v 1.2 2011/07/01 20:27:50 dyoung Exp $");
+__KERNEL_RCSID(0, "$NetBSD: imx51_clock.c,v 1.2.6.1 2012/04/29 23:04:38 mrg Exp $");
 
 #include <sys/param.h>
 #include <sys/systm.h>
@@ -48,7 +48,7 @@
 #include <arm/imx/imx51reg.h>
 #include <arm/imx/imx51var.h>
 #include <arm/imx/imxepitreg.h>
-//#include <arm/imx/imx51_ccmvar.h> notyet
+#include <arm/imx/imx51_ccmvar.h>
 #include <arm/imx/imxclockvar.h>
 
 #include "imxccm.h"	/* if CCM driver is configured into the kernel */
@@ -90,8 +90,6 @@
 	sc->sc_iot = aa->aa_iot;
 	sc->sc_intr = aa->aa_irq;
 
-	KASSERT((sc->sc_intr == IRQ_EPIT1) || (sc->sc_intr == IRQ_EPIT2));
-
 	switch ( aa->aa_addr ) {
 	case EPIT1_BASE:
 		epit1_sc = sc;
@@ -106,6 +104,8 @@
 
 	if (bus_space_map(aa->aa_iot, aa->aa_addr, aa->aa_size, 0, &sc->sc_ioh))
 		panic("%s: Cannot map registers", device_xname(self));
+
+	sc->sc_clksrc = EPITCR_CLKSRC_IPG;
 }
 
 int
@@ -113,11 +113,7 @@
 {
 	unsigned int ipg_freq;
 #if NIMXCCM > 0
-	struct imx51_clocks clk;
-
-	imx51_get_clocks(&clk);
-
-	ipg_freq = clk.ipg_clk;
+	ipg_freq = imx51_get_clock(IMX51CLK_IPG_CLK_ROOT);
 #else
 #ifndef	IMX51_IPGCLK_FREQ
 #error	IMX51_IPGCLK_FREQ need to be defined.
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/sys/arch/arm/imx/imx51_dpllreg.h	Sun Apr 29 23:04:36 2012 +0000
@@ -0,0 +1,62 @@
+/*	$NetBSD: imx51_dpllreg.h,v 1.1.2.2 2012/04/29 23:04:38 mrg Exp $	*/
+/*
+ * Copyright (c) 2012  Genetec Corporation.  All rights reserved.
+ * Written by Hashimoto Kenichi for Genetec Corporation.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY GENETEC CORPORATION ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL GENETEC CORPORATION
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef	_IMX51_DPLLREG_H
+#define	_IMX51_DPLLREG_H
+
+#include <sys/cdefs.h>
+
+/* register offset address */
+
+#define	IMX51_N_DPLLS		3		/* 1..3 */
+
+#define	DPLL_BASE(n)	      	(0x83F80000 + (0x4000 * ((n)-1)))
+#define	DPLL_SIZE		0x100
+
+#define	DPLL_DP_CTL		0x0000
+#define	 DP_CTL_HFSM		__BIT(7)
+#define	 DP_CTL_REF_CLK_SEL_MASK	__BITS(8,9)
+#define	 DP_CTL_REF_CLK_SEL_COSC	(__BIT(9)|0)
+#define	 DP_CTL_REF_CLK_SEL_FPM 	(__BIT(9)|__BIT(8))
+#define	 DP_CTL_REF_CLK_DIV	__BIT(10)
+#define	 DP_CTL_DPDCK0_2_EN	__BIT(12)
+#define	DPLL_DP_CONFIG		0x0004
+#define	DPLL_DP_OP		0x0008
+#define	 DP_OP_PDF_SHIFT	0
+#define	 DP_OP_PDF_MASK		(0xf << DP_OP_PDF_SHIFT)
+#define	 DP_OP_MFI_SHIFT	4
+#define	 DP_OP_MFI_MASK		(0xf << DP_OP_MFI_SHIFT)
+#define	DPLL_DP_MFD		0x000C
+#define	DPLL_DP_MFN		0x0010
+#define	DPLL_DP_MFNMINUS	0x0014
+#define	DPLL_DP_MFNPLUS		0x0018
+#define	DPLL_DP_HFS_OP		0x001C
+#define	DPLL_DP_HFS_MFD		0x0020
+#define	DPLL_DP_HFS_MFN		0x0024
+#define	DPLL_DP_TOGC		0x0028
+#define	DPLL_DP_DESTAT		0x002C
+
+#endif /* _IMX51_DPLLREG_H */
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/sys/arch/arm/imx/imx51_esdhc.c	Sun Apr 29 23:04:36 2012 +0000
@@ -0,0 +1,128 @@
+/*	$NetBSD: imx51_esdhc.c,v 1.1.2.2 2012/04/29 23:04:38 mrg Exp $ */
+
+/*-
+ * Copyright (c) 2012  Genetec Corporation.  All rights reserved.
+ * Written by Hiroyuki Bessho for Genetec Corporation.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above
+ *    copyright notice, this list of conditions and the following
+ *    disclaimer in the documentation and/or other materials provided
+ *    with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS''
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
+ * PARTICULAR PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS
+ * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
+ * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+
+#include <sys/cdefs.h>
+__KERNEL_RCSID(0, "$NetBSD: imx51_esdhc.c,v 1.1.2.2 2012/04/29 23:04:38 mrg Exp $");
+
+#include <sys/param.h>
+#include <sys/device.h>
+#include <sys/systm.h>
+#include <sys/bus.h>
+#include <sys/pmf.h>
+
+#include <machine/intr.h>
+
+#include <dev/sdmmc/sdhcvar.h>
+#include <dev/sdmmc/sdmmcvar.h>
+
+#include <arm/imx/imx51reg.h>
+#include <arm/imx/imx51var.h>
+#include <arm/imx/imx51_ccmvar.h>
+
+struct sdhc_axi_softc {
+	struct sdhc_softc  sc_sdhc;
+	/* we have only one slot */
+	struct sdhc_host *sc_hosts[1];
+
+	void *sc_ih;
+};
+
+static int sdhc_match(device_t, cfdata_t, void *);
+static void sdhc_attach(device_t, device_t, void *);
+
+CFATTACH_DECL_NEW(sdhc_axi, sizeof(struct sdhc_axi_softc),
+    sdhc_match, sdhc_attach, NULL, NULL);
+
+static int
+sdhc_match(device_t parent, cfdata_t cf, void *aux)
+{
+
+	struct axi_attach_args *aa = aux;
+
+	switch (aa->aa_addr) {
+	case ESDHC1_BASE:
+	case ESDHC2_BASE:
+		return 1;
+	}
+
+	return 0;
+}
+
+static void
+sdhc_attach(device_t parent, device_t self, void *aux)
+{
+	struct sdhc_axi_softc *sc = device_private(self);
+	struct axi_attach_args *aa = aux;
+	bus_space_tag_t iot = aa->aa_iot;
+	bus_space_handle_t ioh;
+	u_int perclk;
+
+	sc->sc_sdhc.sc_dev = self;
+
+	sc->sc_sdhc.sc_dmat = aa->aa_dmat;
+
+	if (bus_space_map(iot, aa->aa_addr, ESDHC_SIZE, 0, &ioh)) {
+		aprint_error_dev(self, "can't map\n");
+		return;
+	}
+
+	aprint_normal(": SD/MMC host controller\n");
+	aprint_naive("\n");
+
+
+	sc->sc_sdhc.sc_host = sc->sc_hosts;
+	/* base clock frequency in kHz */
+	perclk = imx51_get_clock(IMX51CLK_PERCLK_ROOT);
+	sc->sc_sdhc.sc_clkbase = perclk / 1000;
+	sc->sc_sdhc.sc_flags |= SDHC_FLAG_HAVE_DVS |
+		SDHC_FLAG_NO_PWR0 |
+		SDHC_FLAG_32BIT_ACCESS |
+		SDHC_FLAG_ENHANCED;
+
+	sc->sc_ih = intr_establish(aa->aa_irq, IPL_SDMMC, IST_LEVEL,
+	    sdhc_intr, &sc->sc_sdhc);
+
+	if (sc->sc_ih == NULL) {
+		aprint_error_dev(self, "can't establish interrupt\n");
+		return;
+	}
+
+	if (sdhc_host_found(&sc->sc_sdhc, iot, ioh, ESDHC_SIZE)) {
+		aprint_error_dev(self, "can't initialize host\n");
+		return;
+	}
+
+	if (!pmf_device_register1(self, sdhc_suspend, sdhc_resume,
+		sdhc_shutdown)) {
+		aprint_error_dev(self,
+		    "can't establish power hook\n");
+	}
+}
--- a/sys/arch/arm/imx/imx51_iomux.c	Tue Apr 17 19:25:17 2012 +0000
+++ b/sys/arch/arm/imx/imx51_iomux.c	Sun Apr 29 23:04:36 2012 +0000
@@ -1,4 +1,4 @@
-/*	$NetBSD: imx51_iomux.c,v 1.2 2011/07/01 20:27:50 dyoung Exp $	*/
+/*	$NetBSD: imx51_iomux.c,v 1.2.6.1 2012/04/29 23:04:38 mrg Exp $	*/
 
 /*
  * Copyright (c) 2009, 2010  Genetec Corporation.  All rights reserved.
@@ -26,7 +26,7 @@
  * POSSIBILITY OF SUCH DAMAGE.
  */
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: imx51_iomux.c,v 1.2 2011/07/01 20:27:50 dyoung Exp $");
+__KERNEL_RCSID(0, "$NetBSD: imx51_iomux.c,v 1.2.6.1 2012/04/29 23:04:38 mrg Exp $");
 
 #define	_INTR_PRIVATE
 
@@ -56,8 +56,6 @@
 	bus_space_handle_t iomux_memh;
 };
 
-extern struct cfdriver imxiomux_cd;
-
 #define	IOMUX_READ(iomux, reg) \
 	bus_space_read_4((iomux)->iomux_memt, (iomux)->iomux_memh, (reg))
 #define	IOMUX_WRITE(iomux, reg, val) \
@@ -68,10 +66,8 @@
 
 static struct iomux_softc *iomuxsc = NULL;
 
-CFATTACH_DECL(imxiomux,
-	      sizeof(struct iomux_softc),
-	      iomux_match, iomux_attach,
-	      NULL, NULL);
+CFATTACH_DECL_NEW(imxiomux, sizeof(struct iomux_softc),
+    iomux_match, iomux_attach, NULL, NULL);
 
 int
 iomux_match(device_t parent, cfdata_t cfdata, void *aux)
@@ -160,7 +156,7 @@
 
 	for (i = 0; conflist[i].pin != IOMUX_CONF_EOT; i++) {
 		iomux_set_pad_sub(iomuxsc, conflist[i].pin, conflist[i].pad);
-		iomux_set_function_sub(iomuxsc, conflist[i].pin, 
+		iomux_set_function_sub(iomuxsc, conflist[i].pin,
 		    conflist[i].mux);
 	}
 }
@@ -172,7 +168,7 @@
 	int i;
 
 	for (i = 0; conflist[i].inout != -1; i++) {
-		iomux_set_inout(iomuxsc, conflist[i].inout, 
+		iomux_set_inout(iomuxsc, conflist[i].inout,
 		    conflist[i].inout_mode);
 	}
 }
--- a/sys/arch/arm/imx/imx51_iomuxreg.h	Tue Apr 17 19:25:17 2012 +0000
+++ b/sys/arch/arm/imx/imx51_iomuxreg.h	Sun Apr 29 23:04:36 2012 +0000
@@ -658,996 +658,25 @@
 
 /* MUX & PAD Control */
 
-#define MUX_PIN_AUD3_BB_CK \
-	IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_AUD3_BB_CK, \
-	    IOMUXC_SW_PAD_CTL_PAD_AUD3_BB_CK)
-#define MUX_PIN_AUD3_BB_FS \
-	IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_AUD3_BB_FS, \
-	    IOMUXC_SW_PAD_CTL_PAD_AUD3_BB_FS)
-#define MUX_PIN_AUD3_BB_RXD \
-	IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_AUD3_BB_RXD, \
-	    IOMUXC_SW_PAD_CTL_PAD_AUD3_BB_RXD)
-#define MUX_PIN_AUD3_BB_TXD \
-	IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_AUD3_BB_TXD, \
-	    IOMUXC_SW_PAD_CTL_PAD_AUD3_BB_TXD)
-#define MUX_PIN_BOOT_MODE0 \
-	IOMUX_PIN(IOMUX_MUX_NONE, IOMUXC_SW_PAD_CTL_PAD_BOOT_MODE0)
-#define MUX_PIN_BOOT_MODE1 \
-	IOMUX_PIN(IOMUX_MUX_NONE, IOMUXC_SW_PAD_CTL_PAD_BOOT_MODE1)
-#define MUX_PIN_CKIL \
-	IOMUX_PIN(IOMUX_MUX_NONE, IOMUXC_SW_PAD_CTL_PAD_CKIL)
-#define MUX_PIN_CLK_SS \
-	IOMUX_PIN(IOMUX_MUX_NONE, IOMUXC_SW_PAD_CTL_PAD_CLK_SS)
-#define MUX_PIN_CSI1_D10 \
-	IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_CSI1_D10, \
-	    IOMUXC_SW_PAD_CTL_PAD_CSI1_D10)
-#define MUX_PIN_CSI1_D11 \
-	IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_CSI1_D11, \
-	    IOMUXC_SW_PAD_CTL_PAD_CSI1_D11)
-#define MUX_PIN_CSI1_D12 \
-	IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_CSI1_D12, \
-	    IOMUXC_SW_PAD_CTL_PAD_CSI1_D12)
-#define MUX_PIN_CSI1_D13 \
-	IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_CSI1_D13, \
-	    IOMUXC_SW_PAD_CTL_PAD_CSI1_D13)
-#define MUX_PIN_CSI1_D14 \
-	IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_CSI1_D14, \
-	    IOMUXC_SW_PAD_CTL_PAD_CSI1_D14)
-#define MUX_PIN_CSI1_D15 \
-	IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_CSI1_D15, \
-	    IOMUXC_SW_PAD_CTL_PAD_CSI1_D15)
-#define MUX_PIN_CSI1_D16 \
-	IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_CSI1_D16, \
-	    IOMUXC_SW_PAD_CTL_PAD_CSI1_D16)
-#define MUX_PIN_CSI1_D17 \
-	IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_CSI1_D17, \
-	    IOMUXC_SW_PAD_CTL_PAD_CSI1_D17)
-#define MUX_PIN_CSI1_D18 \
-	IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_CSI1_D18, \
-	    IOMUXC_SW_PAD_CTL_PAD_CSI1_D18)
-#define MUX_PIN_CSI1_D19 \
-	IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_CSI1_D19, \
-	    IOMUXC_SW_PAD_CTL_PAD_CSI1_D19)
-#define MUX_PIN_CSI1_D8 \
-	IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_CSI1_D8, \
-	    IOMUXC_SW_PAD_CTL_PAD_CSI1_D8)
-#define MUX_PIN_CSI1_D9 \
-	IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_CSI1_D9, \
-	    IOMUXC_SW_PAD_CTL_PAD_CSI1_D9)
-#define MUX_PIN_CSI1_HSYNC \
-	IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_CSI1_HSYNC, \
-	    IOMUXC_SW_PAD_CTL_PAD_CSI1_HSYNC)
-#define MUX_PIN_CSI1_MCLK \
-	IOMUX_PIN(IOMUX_MUX_NONE, IOMUXC_SW_PAD_CTL_PAD_CSI1_MCLK)
-#define MUX_PIN_CSI1_PIXCLK \
-	IOMUX_PIN(IOMUX_MUX_NONE, IOMUXC_SW_PAD_CTL_PAD_CSI1_PIXCLK)
-#define MUX_PIN_CSI1_VSYNC \
-	IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_CSI1_VSYNC, \
-	    IOMUXC_SW_PAD_CTL_PAD_CSI1_VSYNC)
-#define MUX_PIN_CSI2_D12 \
-	IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_CSI2_D12, \
-	    IOMUXC_SW_PAD_CTL_PAD_CSI2_D12)
-#define MUX_PIN_CSI2_D13 \
-	IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_CSI2_D13, \
-	    IOMUXC_SW_PAD_CTL_PAD_CSI2_D13)
-#define MUX_PIN_CSI2_D14 \
-	IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_CSI2_D14, \
-	    IOMUXC_SW_PAD_CTL_PAD_CSI2_D14)
-#define MUX_PIN_CSI2_D15 \
-	IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_CSI2_D15, \
-	    IOMUXC_SW_PAD_CTL_PAD_CSI2_D15)
-#define MUX_PIN_CSI2_D16 \
-	IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_CSI2_D16, \
-	    IOMUXC_SW_PAD_CTL_PAD_CSI2_D16)
-#define MUX_PIN_CSI2_D17 \
-	IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_CSI2_D17, \
-	    IOMUXC_SW_PAD_CTL_PAD_CSI2_D17)
-#define MUX_PIN_CSI2_D18 \
-	IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_CSI2_D18, \
-	    IOMUXC_SW_PAD_CTL_PAD_CSI2_D18)
-#define MUX_PIN_CSI2_D19 \
-	IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_CSI2_D19, \
-	    IOMUXC_SW_PAD_CTL_PAD_CSI2_D19)
-#define MUX_PIN_CSI2_HSYNC \
-	IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_CSI2_HSYNC, \
-	    IOMUXC_SW_PAD_CTL_PAD_CSI2_HSYNC)
-#define MUX_PIN_CSI2_PIXCLK \
-	IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_CSI2_PIXCLK, \
-	    IOMUXC_SW_PAD_CTL_PAD_CSI2_PIXCLK)
-#define MUX_PIN_CSI2_VSYNC \
-	IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_CSI2_VSYNC, \
-	    IOMUXC_SW_PAD_CTL_PAD_CSI2_VSYNC)
-#define MUX_PIN_CSPI1_MISO \
-	IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_CSPI1_MISO, \
-	    IOMUXC_SW_PAD_CTL_PAD_CSPI1_MISO)
-#define MUX_PIN_CSPI1_MOSI \
-	IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_CSPI1_MOSI, \
-	    IOMUXC_SW_PAD_CTL_PAD_CSPI1_MOSI)
-#define MUX_PIN_CSPI1_RDY \
-	IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_CSPI1_RDY, \
-	    IOMUXC_SW_PAD_CTL_PAD_CSPI1_RDY)
-#define MUX_PIN_CSPI1_SCLK \
-	IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_CSPI1_SCLK, \
-	    IOMUXC_SW_PAD_CTL_PAD_CSPI1_SCLK)
-#define MUX_PIN_CSPI1_SS0 \
-	IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_CSPI1_SS0, \
-	    IOMUXC_SW_PAD_CTL_PAD_CSPI1_SS0)
-#define MUX_PIN_CSPI1_SS1 \
-	IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_CSPI1_SS1, \
-	    IOMUXC_SW_PAD_CTL_PAD_CSPI1_SS1)
-#define MUX_PIN_DI1_D0_CS \
-	IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_DI1_D0_CS, \
-	    IOMUXC_SW_PAD_CTL_PAD_DI1_D0_CS)
-#define MUX_PIN_DI1_D1_CS \
-	IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_DI1_D1_CS, \
-	    IOMUXC_SW_PAD_CTL_PAD_DI1_D1_CS)
-#define MUX_PIN_DI1_DISP_CLK \
-	IOMUX_PIN(IOMUX_MUX_NONE, IOMUXC_SW_PAD_CTL_PAD_DI1_DISP_CLK)
-#define MUX_PIN_DI1_PIN11 \
-	IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_DI1_PIN11, \
-	    IOMUXC_SW_PAD_CTL_PAD_DI1_PIN11)
-#define MUX_PIN_DI1_PIN12 \
-	IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_DI1_PIN12, \
-	    IOMUXC_SW_PAD_CTL_PAD_DI1_PIN12)
-#define MUX_PIN_DI1_PIN13 \
-	IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_DI1_PIN13, \
-	    IOMUXC_SW_PAD_CTL_PAD_DI1_PIN13)
-#define MUX_PIN_DI1_PIN15 \
-	IOMUX_PIN(IOMUX_MUX_NONE, IOMUXC_SW_PAD_CTL_PAD_DI1_PIN15)
-#define MUX_PIN_DI1_PIN2 \
-	IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_DI1_PIN2, \
-	    IOMUXC_SW_PAD_CTL_PAD_DI1_PIN2)
-#define MUX_PIN_DI1_PIN3 \
-	IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_DI1_PIN3, \
-	    IOMUXC_SW_PAD_CTL_PAD_DI1_PIN3)
-#define MUX_PIN_DI2_DISP_CLK \
-	IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_DI2_DISP_CLK, \
-	    IOMUXC_SW_PAD_CTL_PAD_DI2_DISP_CLK)
-#define MUX_PIN_DI2_PIN2 \
-	IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_DI2_PIN2, \
-	    IOMUXC_SW_PAD_CTL_PAD_DI2_PIN2)
-#define MUX_PIN_DI2_PIN3 \
-	IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_DI2_PIN3, \
-	    IOMUXC_SW_PAD_CTL_PAD_DI2_PIN3)
-#define MUX_PIN_DI2_PIN4 \
-	IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_DI2_PIN4, \
-	    IOMUXC_SW_PAD_CTL_PAD_DI2_PIN4)
-#define MUX_PIN_DISP1_DAT0 \
-	IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT0, \
-	    IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT0)
-#define MUX_PIN_DISP1_DAT1 \
-	IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT1, \
-	    IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT1)
-#define MUX_PIN_DISP1_DAT10 \
-	IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT10, \
-	    IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT10)
-#define MUX_PIN_DISP1_DAT11 \
-	IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT11, \
-	    IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT11)
-#define MUX_PIN_DISP1_DAT12 \
-	IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT12, \
-	    IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT12)
-#define MUX_PIN_DISP1_DAT13 \
-	IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT13, \
-	    IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT13)
-#define MUX_PIN_DISP1_DAT14 \
-	IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT14, \
-	    IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT14)
-#define MUX_PIN_DISP1_DAT15 \
-	IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT15, \
-	    IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT15)
-#define MUX_PIN_DISP1_DAT16 \
-	IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT16, \
-	    IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT16)
-#define MUX_PIN_DISP1_DAT17 \
-	IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT17, \
-	    IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT17)
-#define MUX_PIN_DISP1_DAT18 \
-	IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT18, \
-	    IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT18)
-#define MUX_PIN_DISP1_DAT19 \
-	IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT19, \
-	    IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT19)
-#define MUX_PIN_DISP1_DAT2 \
-	IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT2, \
-	    IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT2)
-#define MUX_PIN_DISP1_DAT20 \
-	IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT20, \
-	    IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT20)
-#define MUX_PIN_DISP1_DAT21 \
-	IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT21, \
-	    IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT21)
-#define MUX_PIN_DISP1_DAT22 \
-	IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT22, \
-	    IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT22)
-#define MUX_PIN_DISP1_DAT23 \
-	IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT23, \
-	    IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT23)
-#define MUX_PIN_DISP1_DAT3 \
-	IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT3, \
-	    IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT3)
-#define MUX_PIN_DISP1_DAT4 \
-	IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT4, \
-	    IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT4)
-#define MUX_PIN_DISP1_DAT5 \
-	IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT5, \
-	    IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT5)
-#define MUX_PIN_DISP1_DAT6 \
-	IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT6, \
-	    IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT6)
-#define MUX_PIN_DISP1_DAT7 \
-	IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT7, \
-	    IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT7)
-#define MUX_PIN_DISP1_DAT8 \
-	IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT8, \
-	    IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT8)
-#define MUX_PIN_DISP1_DAT9 \
-	IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT9, \
-	    IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT9)
-#define MUX_PIN_DISP2_DAT0 \
-	IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_DISP2_DAT0, \
-	    IOMUXC_SW_PAD_CTL_PAD_DISP2_DAT0)
-#define MUX_PIN_DISP2_DAT1 \
-	IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_DISP2_DAT1, \
-	    IOMUXC_SW_PAD_CTL_PAD_DISP2_DAT1)
-#define MUX_PIN_DISP2_DAT10 \
-	IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_DISP2_DAT10, \
-	    IOMUXC_SW_PAD_CTL_PAD_DISP2_DAT10)
-#define MUX_PIN_DISP2_DAT11 \
-	IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_DISP2_DAT11, \
-	    IOMUXC_SW_PAD_CTL_PAD_DISP2_DAT11)
-#define MUX_PIN_DISP2_DAT12 \
-	IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_DISP2_DAT12, \
-	    IOMUXC_SW_PAD_CTL_PAD_DISP2_DAT12)
-#define MUX_PIN_DISP2_DAT13 \
-	IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_DISP2_DAT13, \
-	    IOMUXC_SW_PAD_CTL_PAD_DISP2_DAT13)
-#define MUX_PIN_DISP2_DAT14 \
-	IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_DISP2_DAT14, \
-	    IOMUXC_SW_PAD_CTL_PAD_DISP2_DAT14)
-#define MUX_PIN_DISP2_DAT15 \
-	IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_DISP2_DAT15, \
-	    IOMUXC_SW_PAD_CTL_PAD_DISP2_DAT15)
-#define MUX_PIN_DISP2_DAT2 \
-	IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_DISP2_DAT2, \
-	    IOMUXC_SW_PAD_CTL_PAD_DISP2_DAT2)
-#define MUX_PIN_DISP2_DAT3 \
-	IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_DISP2_DAT3, \
-	    IOMUXC_SW_PAD_CTL_PAD_DISP2_DAT3)
-#define MUX_PIN_DISP2_DAT4 \
-	IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_DISP2_DAT4, \
-	    IOMUXC_SW_PAD_CTL_PAD_DISP2_DAT4)
-#define MUX_PIN_DISP2_DAT5 \
-	IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_DISP2_DAT5, \
-	    IOMUXC_SW_PAD_CTL_PAD_DISP2_DAT5)
-#define MUX_PIN_DISP2_DAT6 \
-	IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_DISP2_DAT6, \
-	    IOMUXC_SW_PAD_CTL_PAD_DISP2_DAT6)
-#define MUX_PIN_DISP2_DAT7 \
-	IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_DISP2_DAT7, \
-	    IOMUXC_SW_PAD_CTL_PAD_DISP2_DAT7)
-#define MUX_PIN_DISP2_DAT8 \
-	IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_DISP2_DAT8, \
-	    IOMUXC_SW_PAD_CTL_PAD_DISP2_DAT8)
-#define MUX_PIN_DISP2_DAT9 \
-	IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_DISP2_DAT9, \
-	    IOMUXC_SW_PAD_CTL_PAD_DISP2_DAT9)
-#define MUX_PIN_DISPB2_SER_CLK \
-	IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_DISPB2_SER_CLK, \
-	    IOMUXC_SW_PAD_CTL_PAD_DISPB2_SER_CLK)
-#define MUX_PIN_DISPB2_SER_DIN \
-	IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_DISPB2_SER_DIN, \
-	    IOMUXC_SW_PAD_CTL_PAD_DISPB2_SER_DIN)
-#define MUX_PIN_DISPB2_SER_DIO \
-	IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_DISPB2_SER_DIO, \
-	    IOMUXC_SW_PAD_CTL_PAD_DISPB2_SER_DIO)
-#define MUX_PIN_DISPB2_SER_RS \
-	IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_DISPB2_SER_RS, \
-	    IOMUXC_SW_PAD_CTL_PAD_DISPB2_SER_RS)
-#define MUX_PIN_DI_GP1 \
-	IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_DI_GP1, \
-	    IOMUXC_SW_PAD_CTL_PAD_DI_GP1)
-#define MUX_PIN_DI_GP2 \
-	IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_DI_GP2, \
-	    IOMUXC_SW_PAD_CTL_PAD_DI_GP2)
-#define MUX_PIN_DI_GP3 \
-	IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_DI_GP3, \
-	    IOMUXC_SW_PAD_CTL_PAD_DI_GP3)
-#define MUX_PIN_DI_GP4 \
-	IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_DI_GP4, \
-	    IOMUXC_SW_PAD_CTL_PAD_DI_GP4)
-#define MUX_PIN_DRAM_CAS \
-	IOMUX_PIN(IOMUX_MUX_NONE, IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS)
-#define MUX_PIN_DRAM_CS0 \
-	IOMUX_PIN(IOMUX_MUX_NONE, IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0)
-#define MUX_PIN_DRAM_CS1 \
-	IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_DRAM_CS1, \
-	    IOMUXC_SW_PAD_CTL_PAD_DRAM_CS1)
-#define MUX_PIN_DRAM_DQM0 \
-	IOMUX_PIN(IOMUX_MUX_NONE, IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0)
-#define MUX_PIN_DRAM_DQM1 \
-	IOMUX_PIN(IOMUX_MUX_NONE, IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1)
-#define MUX_PIN_DRAM_DQM2 \
-	IOMUX_PIN(IOMUX_MUX_NONE, IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2)
-#define MUX_PIN_DRAM_DQM3 \
-	IOMUX_PIN(IOMUX_MUX_NONE, IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3)
-#define MUX_PIN_DRAM_RAS \
-	IOMUX_PIN(IOMUX_MUX_NONE, IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS)
-#define MUX_PIN_DRAM_SDCKE0 \
-	IOMUX_PIN(IOMUX_MUX_NONE, IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0)
-#define MUX_PIN_DRAM_SDCKE1 \
-	IOMUX_PIN(IOMUX_MUX_NONE, IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1)
-#define MUX_PIN_DRAM_SDCLK \
-	IOMUX_PIN(IOMUX_MUX_NONE, IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK)
-#define MUX_PIN_DRAM_SDQS0 \
-	IOMUX_PIN(IOMUX_MUX_NONE, IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0)
-#define MUX_PIN_DRAM_SDQS1 \
-	IOMUX_PIN(IOMUX_MUX_NONE, IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1)
-#define MUX_PIN_DRAM_SDQS2 \
-	IOMUX_PIN(IOMUX_MUX_NONE, IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2)
-#define MUX_PIN_DRAM_SDQS3 \
-	IOMUX_PIN(IOMUX_MUX_NONE, IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3)
-#define MUX_PIN_DRAM_SDWE \
-	IOMUX_PIN(IOMUX_MUX_NONE, IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE)
-#define MUX_PIN_EIM_A16 \
-	IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_EIM_A16, \
-	    IOMUXC_SW_PAD_CTL_PAD_EIM_A16)
-#define MUX_PIN_EIM_A17 \
-	IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_EIM_A17, \
-	    IOMUXC_SW_PAD_CTL_PAD_EIM_A17)
-#define MUX_PIN_EIM_A18 \
-	IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_EIM_A18, \
-	    IOMUXC_SW_PAD_CTL_PAD_EIM_A18)
-#define MUX_PIN_EIM_A19 \
-	IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_EIM_A19, \
-	    IOMUXC_SW_PAD_CTL_PAD_EIM_A19)
-#define MUX_PIN_EIM_A20 \
-	IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_EIM_A20, \
-	    IOMUXC_SW_PAD_CTL_PAD_EIM_A20)
-#define MUX_PIN_EIM_A21 \
-	IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_EIM_A21, \
-	    IOMUXC_SW_PAD_CTL_PAD_EIM_A21)
-#define MUX_PIN_EIM_A22 \
-	IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_EIM_A22, \
-	    IOMUXC_SW_PAD_CTL_PAD_EIM_A22)
-#define MUX_PIN_EIM_A23 \
-	IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_EIM_A23, \
-	    IOMUXC_SW_PAD_CTL_PAD_EIM_A23)
-#define MUX_PIN_EIM_A24 \
-	IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_EIM_A24, \
-	    IOMUXC_SW_PAD_CTL_PAD_EIM_A24)
-#define MUX_PIN_EIM_A25 \
-	IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_EIM_A25, \
-	    IOMUXC_SW_PAD_CTL_PAD_EIM_A25)
-#define MUX_PIN_EIM_A26 \
-	IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_EIM_A26, \
-	    IOMUXC_SW_PAD_CTL_PAD_EIM_A26)
-#define MUX_PIN_EIM_A27 \
-	IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_EIM_A27, \
-	    IOMUXC_SW_PAD_CTL_PAD_EIM_A27)
-#define MUX_PIN_EIM_BCLK \
-	IOMUX_PIN(IOMUX_MUX_NONE, IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK)
-#define MUX_PIN_EIM_CRE \
-	IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_EIM_CRE, \
-	    IOMUXC_SW_PAD_CTL_PAD_EIM_CRE)
-#define MUX_PIN_EIM_CS0 \
-	IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_EIM_CS0, \
-	    IOMUXC_SW_PAD_CTL_PAD_EIM_CS0)
-#define MUX_PIN_EIM_CS1 \
-	IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_EIM_CS1, \
-	    IOMUXC_SW_PAD_CTL_PAD_EIM_CS1)
-#define MUX_PIN_EIM_CS2 \
-	IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_EIM_CS2, \
-	    IOMUXC_SW_PAD_CTL_PAD_EIM_CS2)
-#define MUX_PIN_EIM_CS3 \
-	IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_EIM_CS3, \
-	    IOMUXC_SW_PAD_CTL_PAD_EIM_CS3)
-#define MUX_PIN_EIM_CS4 \
-	IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_EIM_CS4, \
-	    IOMUXC_SW_PAD_CTL_PAD_EIM_CS4)
-#define MUX_PIN_EIM_CS5 \
-	IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_EIM_CS5, \
-	    IOMUXC_SW_PAD_CTL_PAD_EIM_CS5)
-#define MUX_PIN_EIM_D16 \
-	IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_EIM_D16, \
-	    IOMUXC_SW_PAD_CTL_PAD_EIM_D16)
-#define MUX_PIN_EIM_D17 \
-	IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_EIM_D17, \
-	    IOMUXC_SW_PAD_CTL_PAD_EIM_D17)
-#define MUX_PIN_EIM_D18 \
-	IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_EIM_D18, \
-	    IOMUXC_SW_PAD_CTL_PAD_EIM_D18)
-#define MUX_PIN_EIM_D19 \
-	IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_EIM_D19, \
-	    IOMUXC_SW_PAD_CTL_PAD_EIM_D19)
-#define MUX_PIN_EIM_D20 \
-	IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_EIM_D20, \
-	    IOMUXC_SW_PAD_CTL_PAD_EIM_D20)
-#define MUX_PIN_EIM_D21 \
-	IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_EIM_D21, \
-	    IOMUXC_SW_PAD_CTL_PAD_EIM_D21)
-#define MUX_PIN_EIM_D22 \
-	IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_EIM_D22, \
-	    IOMUXC_SW_PAD_CTL_PAD_EIM_D22)
-#define MUX_PIN_EIM_D23 \
-	IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_EIM_D23, \
-	    IOMUXC_SW_PAD_CTL_PAD_EIM_D23)
-#define MUX_PIN_EIM_D24 \
-	IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_EIM_D24, \
-	    IOMUXC_SW_PAD_CTL_PAD_EIM_D24)
-#define MUX_PIN_EIM_D25 \
-	IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_EIM_D25, \
-	    IOMUXC_SW_PAD_CTL_PAD_EIM_D25)
-#define MUX_PIN_EIM_D26 \
-	IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_EIM_D26, \
-	    IOMUXC_SW_PAD_CTL_PAD_EIM_D26)
-#define MUX_PIN_EIM_D27 \
-	IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_EIM_D27, \
-	    IOMUXC_SW_PAD_CTL_PAD_EIM_D27)
-#define MUX_PIN_EIM_D28 \
-	IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_EIM_D28, \
-	    IOMUXC_SW_PAD_CTL_PAD_EIM_D28)
-#define MUX_PIN_EIM_D29 \
-	IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_EIM_D29, \
-	    IOMUXC_SW_PAD_CTL_PAD_EIM_D29)
-#define MUX_PIN_EIM_D30 \
-	IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_EIM_D30, \
-	    IOMUXC_SW_PAD_CTL_PAD_EIM_D30)
-#define MUX_PIN_EIM_D31 \
-	IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_EIM_D31, \
-	    IOMUXC_SW_PAD_CTL_PAD_EIM_D31)
-#define MUX_PIN_EIM_DA0 \
-	IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_EIM_DA0, \
-	    IOMUX_PAD_NONE)
-#define MUX_PIN_EIM_DA1 \
-	IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_EIM_DA1, \
-	    IOMUX_PAD_NONE)
-#define MUX_PIN_EIM_DA10 \
-	IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_EIM_DA10, \
-	    IOMUX_PAD_NONE)
-#define MUX_PIN_EIM_DA11 \
-	IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_EIM_DA11, \
-	    IOMUX_PAD_NONE)
-#define MUX_PIN_EIM_DA12 \
-	IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_EIM_DA12, \
-	    IOMUX_PAD_NONE)
-#define MUX_PIN_EIM_DA13 \
-	IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_EIM_DA13, \
-	    IOMUX_PAD_NONE)
-#define MUX_PIN_EIM_DA14 \
-	IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_EIM_DA14, \
-	    IOMUX_PAD_NONE)
-#define MUX_PIN_EIM_DA15 \
-	IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_EIM_DA15, \
-	    IOMUX_PAD_NONE)
-#define MUX_PIN_EIM_DA2 \
-	IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_EIM_DA2, \
-	    IOMUX_PAD_NONE)
-#define MUX_PIN_EIM_DA3 \
-	IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_EIM_DA3, \
-	    IOMUX_PAD_NONE)
-#define MUX_PIN_EIM_DA4 \
-	IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_EIM_DA4, \
-	    IOMUX_PAD_NONE)
-#define MUX_PIN_EIM_DA5 \
-	IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_EIM_DA5, \
-	    IOMUX_PAD_NONE)
-#define MUX_PIN_EIM_DA6 \
-	IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_EIM_DA6, \
-	    IOMUX_PAD_NONE)
-#define MUX_PIN_EIM_DA7 \
-	IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_EIM_DA7, \
-	    IOMUX_PAD_NONE)
-#define MUX_PIN_EIM_DA8 \
-	IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_EIM_DA8, \
-	    IOMUX_PAD_NONE)
-#define MUX_PIN_EIM_DA9 \
-	IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_EIM_DA9, \
-	    IOMUX_PAD_NONE)
-#define MUX_PIN_EIM_DTACK \
-	IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_EIM_DTACK, \
-	    IOMUXC_SW_PAD_CTL_PAD_EIM_DTACK)
-#define MUX_PIN_EIM_EB0 \
-	IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_EIM_EB0, \
-	    IOMUXC_SW_PAD_CTL_PAD_EIM_EB0)
-#define MUX_PIN_EIM_EB1 \
-	IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_EIM_EB1, \
-	    IOMUXC_SW_PAD_CTL_PAD_EIM_EB1)
-#define MUX_PIN_EIM_EB2 \
-	IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_EIM_EB2, \
-	    IOMUXC_SW_PAD_CTL_PAD_EIM_EB2)
-#define MUX_PIN_EIM_EB3 \
-	IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_EIM_EB3, \
-	    IOMUXC_SW_PAD_CTL_PAD_EIM_EB3)
-#define MUX_PIN_EIM_LBA \
-	IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_EIM_LBA, \
-	    IOMUXC_SW_PAD_CTL_PAD_EIM_LBA)
-#define MUX_PIN_EIM_OE \
-	IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_EIM_OE, \
-	    IOMUXC_SW_PAD_CTL_PAD_EIM_OE)
-#define MUX_PIN_EIM_RW \
-	IOMUX_PIN(IOMUX_MUX_NONE, IOMUXC_SW_PAD_CTL_PAD_EIM_RW)
-#define MUX_PIN_EIM_SDBA2 \
-	IOMUX_PIN(IOMUX_MUX_NONE, IOMUXC_SW_PAD_CTL_PAD_EIM_SDBA2)
-#define MUX_PIN_EIM_SDODT0 \
-	IOMUX_PIN(IOMUX_MUX_NONE, IOMUXC_SW_PAD_CTL_PAD_EIM_SDODT0)
-#define MUX_PIN_EIM_SDODT1 \
-	IOMUX_PIN(IOMUX_MUX_NONE, IOMUXC_SW_PAD_CTL_PAD_EIM_SDODT1)
-#define MUX_PIN_EIM_WAIT \
-	IOMUX_PIN(IOMUX_MUX_NONE, IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT)
-#define MUX_PIN_GPIO1_0 \
-	IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_GPIO1_0, \
-	    IOMUXC_SW_PAD_CTL_PAD_GPIO1_0)
-#define MUX_PIN_GPIO1_1 \
-	IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_GPIO1_1, \
-	    IOMUXC_SW_PAD_CTL_PAD_GPIO1_1)
-#define MUX_PIN_GPIO1_2 \
-	IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_GPIO1_2, \
-	    IOMUXC_SW_PAD_CTL_PAD_GPIO1_2)
-#define MUX_PIN_GPIO1_3 \
-	IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_GPIO1_3, \
-	    IOMUXC_SW_PAD_CTL_PAD_GPIO1_3)
-#define MUX_PIN_GPIO1_4 \
-	IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_GPIO1_4, \
-	    IOMUXC_SW_PAD_CTL_PAD_GPIO1_4)
-#define MUX_PIN_GPIO1_5 \
-	IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_GPIO1_5, \
-	    IOMUXC_SW_PAD_CTL_PAD_GPIO1_5)
-#define MUX_PIN_GPIO1_6 \
-	IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_GPIO1_6, \
-	    IOMUXC_SW_PAD_CTL_PAD_GPIO1_6)
-#define MUX_PIN_GPIO1_7 \
-	IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_GPIO1_7, \
-	    IOMUXC_SW_PAD_CTL_PAD_GPIO1_7)
-#define MUX_PIN_GPIO1_8 \
-	IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_GPIO1_8, \
-	    IOMUXC_SW_PAD_CTL_PAD_GPIO1_8)
-#define MUX_PIN_GPIO1_9 \
-	IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_GPIO1_9, \
-	    IOMUXC_SW_PAD_CTL_PAD_GPIO1_9)
-#define MUX_PIN_GPIO_NAND \
-	IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_GPIO_NAND, \
-	    IOMUXC_SW_PAD_CTL_PAD_GPIO_NAND)
-#define MUX_PIN_I2C1_CLK \
-	IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_I2C1_CLK, \
-	    IOMUXC_SW_PAD_CTL_PAD_I2C1_CLK)
-#define MUX_PIN_I2C1_DAT \
-	IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_I2C1_DAT, \
-	    IOMUXC_SW_PAD_CTL_PAD_I2C1_DAT)
-#define MUX_PIN_JTAG_DE_B \
-	IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_JTAG_DE_B, \
-	    IOMUX_PAD_NONE)
-#define MUX_PIN_JTAG_MOD \
-	IOMUX_PIN(IOMUX_MUX_NONE, IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD)
-#define MUX_PIN_JTAG_TCK \
-	IOMUX_PIN(IOMUX_MUX_NONE, IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK)
-#define MUX_PIN_JTAG_TDI \
-	IOMUX_PIN(IOMUX_MUX_NONE, IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI)
-#define MUX_PIN_JTAG_TMS \
-	IOMUX_PIN(IOMUX_MUX_NONE, IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS)
-#define MUX_PIN_JTAG_TRSTB \
-	IOMUX_PIN(IOMUX_MUX_NONE, IOMUXC_SW_PAD_CTL_PAD_JTAG_TRSTB)
-#define MUX_PIN_KEY_COL0 \
-	IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_KEY_COL0, \
-	    IOMUXC_SW_PAD_CTL_PAD_KEY_COL0)
-#define MUX_PIN_KEY_COL1 \
-	IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_KEY_COL1, \
-	    IOMUXC_SW_PAD_CTL_PAD_KEY_COL1)
-#define MUX_PIN_KEY_COL2 \
-	IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_KEY_COL2, \
-	    IOMUXC_SW_PAD_CTL_PAD_KEY_COL2)
-#define MUX_PIN_KEY_COL3 \
-	IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_KEY_COL3, \
-	    IOMUXC_SW_PAD_CTL_PAD_KEY_COL3)
-#define MUX_PIN_KEY_COL4 \
-	IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_KEY_COL4, \
-	    IOMUXC_SW_PAD_CTL_PAD_KEY_COL4)
-#define MUX_PIN_KEY_COL5 \
-	IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_KEY_COL5, \
-	    IOMUXC_SW_PAD_CTL_PAD_KEY_COL5)
-#define MUX_PIN_KEY_ROW0 \
-	IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_KEY_ROW0, \
-	    IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0)
-#define MUX_PIN_KEY_ROW1 \
-	IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_KEY_ROW1, \
-	    IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1)
-#define MUX_PIN_KEY_ROW2 \
-	IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_KEY_ROW2, \
-	    IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2)
-#define MUX_PIN_KEY_ROW3 \
-	IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_KEY_ROW3, \
-	    IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3)
-#define MUX_PIN_NANDF_ALE \
-	IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_NANDF_ALE, \
-	    IOMUXC_SW_PAD_CTL_PAD_NANDF_ALE)
-#define MUX_PIN_NANDF_CLE \
-	IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_NANDF_CLE, \
-	    IOMUXC_SW_PAD_CTL_PAD_NANDF_CLE)
-#define MUX_PIN_NANDF_CS0 \
-	IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_NANDF_CS0, \
-	    IOMUXC_SW_PAD_CTL_PAD_NANDF_CS0)
-#define MUX_PIN_NANDF_CS1 \
-	IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_NANDF_CS1, \
-	    IOMUXC_SW_PAD_CTL_PAD_NANDF_CS1)
-#define MUX_PIN_NANDF_CS2 \
-	IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_NANDF_CS2, \
-	    IOMUXC_SW_PAD_CTL_PAD_NANDF_CS2)
-#define MUX_PIN_NANDF_CS3 \
-	IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_NANDF_CS3, \
-	    IOMUXC_SW_PAD_CTL_PAD_NANDF_CS3)
-#define MUX_PIN_NANDF_CS4 \
-	IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_NANDF_CS4, \
-	    IOMUXC_SW_PAD_CTL_PAD_NANDF_CS4)
-#define MUX_PIN_NANDF_CS5 \
-	IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_NANDF_CS5, \
-	    IOMUXC_SW_PAD_CTL_PAD_NANDF_CS5)
-#define MUX_PIN_NANDF_CS6 \
-	IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_NANDF_CS6, \
-	    IOMUXC_SW_PAD_CTL_PAD_NANDF_CS6)
-#define MUX_PIN_NANDF_CS7 \
-	IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_NANDF_CS7, \
-	    IOMUXC_SW_PAD_CTL_PAD_NANDF_CS7)
-#define MUX_PIN_NANDF_D0 \
-	IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_NANDF_D0, \
-	    IOMUXC_SW_PAD_CTL_PAD_NANDF_D0)
-#define MUX_PIN_NANDF_D1 \
-	IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_NANDF_D1, \
-	    IOMUXC_SW_PAD_CTL_PAD_NANDF_D1)
-#define MUX_PIN_NANDF_D10 \
-	IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_NANDF_D10, \
-	    IOMUXC_SW_PAD_CTL_PAD_NANDF_D10)
-#define MUX_PIN_NANDF_D11 \
-	IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_NANDF_D11, \
-	    IOMUXC_SW_PAD_CTL_PAD_NANDF_D11)
-#define MUX_PIN_NANDF_D12 \
-	IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_NANDF_D12, \
-	    IOMUXC_SW_PAD_CTL_PAD_NANDF_D12)
-#define MUX_PIN_NANDF_D13 \
-	IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_NANDF_D13, \
-	    IOMUXC_SW_PAD_CTL_PAD_NANDF_D13)
-#define MUX_PIN_NANDF_D14 \
-	IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_NANDF_D14, \
-	    IOMUXC_SW_PAD_CTL_PAD_NANDF_D14)
-#define MUX_PIN_NANDF_D15 \
-	IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_NANDF_D15, \
-	    IOMUXC_SW_PAD_CTL_PAD_NANDF_D15)
-#define MUX_PIN_NANDF_D2 \
-	IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_NANDF_D2, \
-	    IOMUXC_SW_PAD_CTL_PAD_NANDF_D2)
-#define MUX_PIN_NANDF_D3 \
-	IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_NANDF_D3, \
-	    IOMUXC_SW_PAD_CTL_PAD_NANDF_D3)
-#define MUX_PIN_NANDF_D4 \
-	IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_NANDF_D4, \
-	    IOMUXC_SW_PAD_CTL_PAD_NANDF_D4)
-#define MUX_PIN_NANDF_D5 \
-	IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_NANDF_D5, \
-	    IOMUXC_SW_PAD_CTL_PAD_NANDF_D5)
-#define MUX_PIN_NANDF_D6 \
-	IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_NANDF_D6, \
-	    IOMUXC_SW_PAD_CTL_PAD_NANDF_D6)
-#define MUX_PIN_NANDF_D7 \
-	IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_NANDF_D7, \
-	    IOMUXC_SW_PAD_CTL_PAD_NANDF_D7)
-#define MUX_PIN_NANDF_D8 \
-	IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_NANDF_D8, \
-	    IOMUXC_SW_PAD_CTL_PAD_NANDF_D8)
-#define MUX_PIN_NANDF_D9 \
-	IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_NANDF_D9, \
-	    IOMUXC_SW_PAD_CTL_PAD_NANDF_D9)
-#define MUX_PIN_NANDF_RB0 \
-	IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_NANDF_RB0, \
-	    IOMUXC_SW_PAD_CTL_PAD_NANDF_RB0)
-#define MUX_PIN_NANDF_RB1 \
-	IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_NANDF_RB1, \
-	    IOMUXC_SW_PAD_CTL_PAD_NANDF_RB1)
-#define MUX_PIN_NANDF_RB2 \
-	IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_NANDF_RB2, \
-	    IOMUXC_SW_PAD_CTL_PAD_NANDF_RB2)
-#define MUX_PIN_NANDF_RB3 \
-	IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_NANDF_RB3, \
-	    IOMUXC_SW_PAD_CTL_PAD_NANDF_RB3)
-#define MUX_PIN_NANDF_RDY_INT \
-	IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_NANDF_RDY_INT, \
-	    IOMUXC_SW_PAD_CTL_PAD_NANDF_RDY_INT)
-#define MUX_PIN_NANDF_RE_B \
-	IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_NANDF_RE_B, \
-	    IOMUXC_SW_PAD_CTL_PAD_NANDF_RE_B)
-#define MUX_PIN_NANDF_WE_B \
-	IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_NANDF_WE_B, \
-	    IOMUXC_SW_PAD_CTL_PAD_NANDF_WE_B)
-#define MUX_PIN_NANDF_WP_B \
-	IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_NANDF_WP_B, \
-	    IOMUXC_SW_PAD_CTL_PAD_NANDF_WP_B)
-#define MUX_PIN_OWIRE_LINE \
-	IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_OWIRE_LINE, \
-	    IOMUXC_SW_PAD_CTL_PAD_OWIRE_LINE)
-#define MUX_PIN_PMIC_INT_REQ \
-	IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_PMIC_INT_REQ, \
-	    IOMUXC_SW_PAD_CTL_PAD_PMIC_INT_REQ)
-#define MUX_PIN_PMIC_ON_REQ \
-	IOMUX_PIN(IOMUX_MUX_NONE, IOMUXC_SW_PAD_CTL_PAD_PMIC_ON_REQ)
-#define MUX_PIN_PMIC_RDY \
-	IOMUX_PIN(IOMUX_MUX_NONE, IOMUXC_SW_PAD_CTL_PAD_PMIC_RDY)
-#define MUX_PIN_PMIC_STBY_REQ \
-	IOMUX_PIN(IOMUX_MUX_NONE, IOMUXC_SW_PAD_CTL_PAD_PMIC_STBY_REQ)
-#define MUX_PIN_POR_B \
-	IOMUX_PIN(IOMUX_MUX_NONE, IOMUXC_SW_PAD_CTL_PAD_POR_B)
-#define MUX_PIN_RESET_IN_B \
-	IOMUX_PIN(IOMUX_MUX_NONE, IOMUXC_SW_PAD_CTL_PAD_RESET_IN_B)
-#define MUX_PIN_SD1_CLK \
-	IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_SD1_CLK, \
-	    IOMUXC_SW_PAD_CTL_PAD_SD1_CLK)
-#define MUX_PIN_SD1_CMD \
-	IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_SD1_CMD, \
-	    IOMUXC_SW_PAD_CTL_PAD_SD1_CMD)
-#define MUX_PIN_SD1_DATA0 \
-	IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_SD1_DATA0, \
-	    IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0)
-#define MUX_PIN_SD1_DATA1 \
-	IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_SD1_DATA1, \
-	    IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1)
-#define MUX_PIN_SD1_DATA2 \
-	IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_SD1_DATA2, \
-	    IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2)
-#define MUX_PIN_SD1_DATA3 \
-	IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_SD1_DATA3, \
-	    IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3)
-#define MUX_PIN_SD2_CLK \
-	IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_SD2_CLK, \
-	    IOMUXC_SW_PAD_CTL_PAD_SD2_CLK)
-#define MUX_PIN_SD2_CMD \
-	IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_SD2_CMD, \
-	    IOMUXC_SW_PAD_CTL_PAD_SD2_CMD)
-#define MUX_PIN_SD2_DATA0 \
-	IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_SD2_DATA0, \
-	    IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0)
-#define MUX_PIN_SD2_DATA1 \
-	IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_SD2_DATA1, \
-	    IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1)
-#define MUX_PIN_SD2_DATA2 \
-	IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_SD2_DATA2, \
-	    IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2)
-#define MUX_PIN_SD2_DATA3 \
-	IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_SD2_DATA3, \
-	    IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3)
-#define MUX_PIN_UART1_CTS \
-	IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_UART1_CTS, \
-	    IOMUXC_SW_PAD_CTL_PAD_UART1_CTS)
-#define MUX_PIN_UART1_RTS \
-	IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_UART1_RTS, \
-	    IOMUXC_SW_PAD_CTL_PAD_UART1_RTS)
-#define MUX_PIN_UART1_RXD \
-	IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_UART1_RXD, \
-	    IOMUXC_SW_PAD_CTL_PAD_UART1_RXD)
-#define MUX_PIN_UART1_TXD \
-	IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_UART1_TXD, \
-	    IOMUXC_SW_PAD_CTL_PAD_UART1_TXD)
-#define MUX_PIN_UART2_RXD \
-	IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_UART2_RXD, \
-	    IOMUXC_SW_PAD_CTL_PAD_UART2_RXD)
-#define MUX_PIN_UART2_TXD \
-	IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_UART2_TXD, \
-	    IOMUXC_SW_PAD_CTL_PAD_UART2_TXD)
-#define MUX_PIN_UART3_RXD \
-	IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_UART3_RXD, \
-	    IOMUXC_SW_PAD_CTL_PAD_UART3_RXD)
-#define MUX_PIN_UART3_TXD \
-	IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_UART3_TXD, \
-	    IOMUXC_SW_PAD_CTL_PAD_UART3_TXD)
-#define MUX_PIN_USBH1_CLK \
-	IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_USBH1_CLK, \
-	    IOMUXC_SW_PAD_CTL_PAD_USBH1_CLK)
-#define MUX_PIN_USBH1_DATA0 \
-	IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_USBH1_DATA0, \
-	    IOMUXC_SW_PAD_CTL_PAD_USBH1_DATA0)
-#define MUX_PIN_USBH1_DATA1 \
-	IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_USBH1_DATA1, \
-	    IOMUXC_SW_PAD_CTL_PAD_USBH1_DATA1)
-#define MUX_PIN_USBH1_DATA2 \
-	IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_USBH1_DATA2, \
-	    IOMUXC_SW_PAD_CTL_PAD_USBH1_DATA2)
-#define MUX_PIN_USBH1_DATA3 \
-	IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_USBH1_DATA3, \
-	    IOMUXC_SW_PAD_CTL_PAD_USBH1_DATA3)
-#define MUX_PIN_USBH1_DATA4 \
-	IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_USBH1_DATA4, \
-	    IOMUXC_SW_PAD_CTL_PAD_USBH1_DATA4)
-#define MUX_PIN_USBH1_DATA5 \
-	IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_USBH1_DATA5, \
-	    IOMUXC_SW_PAD_CTL_PAD_USBH1_DATA5)
-#define MUX_PIN_USBH1_DATA6 \
-	IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_USBH1_DATA6, \
-	    IOMUXC_SW_PAD_CTL_PAD_USBH1_DATA6)
-#define MUX_PIN_USBH1_DATA7 \
-	IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_USBH1_DATA7, \
-	    IOMUXC_SW_PAD_CTL_PAD_USBH1_DATA7)
-#define MUX_PIN_USBH1_DIR \
-	IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_USBH1_DIR, \
-	    IOMUXC_SW_PAD_CTL_PAD_USBH1_DIR)
-#define MUX_PIN_USBH1_NXT \
-	IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_USBH1_NXT, \
-	    IOMUXC_SW_PAD_CTL_PAD_USBH1_NXT)
-#define MUX_PIN_USBH1_STP \
-	IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_USBH1_STP, \
-	    IOMUXC_SW_PAD_CTL_PAD_USBH1_STP)
+#define MUX_PIN(name)				\
+	IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_##name,	\
+	    IOMUXC_SW_PAD_CTL_PAD_##name)
+
+#define MUX_PIN_MUX(name)			\
+	IOMUX_PIN(IOMUXC_SW_MUX_CTL_PAD_##name, IOMUX_PAD_NONE)
+
+#define MUX_PIN_PAD(name) \
+	IOMUX_PIN(IOMUX_MUX_NONE, IOMUXC_SW_PAD_CTL_PAD_##name)
+
+#define MUX_PIN_GRP(name) \
+	IOMUX_PIN(IOMUX_MUX_NONE, IOMUXC_SW_PAD_CTL_GRP_##name)
+
+#define MUX_PIN_PATH(name) \
+	IOMUX_PIN(IOMUXC_##name##_SELECT_INPUT, IOMUX_MUX_NONE)
 
 /* INPUT Control */
 
-#define MUX_IN_AUDMUX_P4_INPUT_DA_AMX \
-	IOMUXC_AUDMUX_P4_INPUT_DA_AMX_SELECT_INPUT
-#define MUX_IN_AUDMUX_P4_INPUT_DB_AMX \
-	IOMUXC_AUDMUX_P4_INPUT_DB_AMX_SELECT_INPUT
-#define MUX_IN_AUDMUX_P4_INPUT_TXCLK_AMX \
-	IOMUXC_AUDMUX_P4_INPUT_TXCLK_AMX_SELECT_INPUT
-#define MUX_IN_AUDMUX_P4_INPUT_TXFS_AMX \
-	IOMUXC_AUDMUX_P4_INPUT_TXFS_AMX_SELECT_INPUT
-#define MUX_IN_AUDMUX_P5_INPUT_DA_AMX \
-	IOMUXC_AUDMUX_P5_INPUT_DA_AMX_SELECT_INPUT
-#define MUX_IN_AUDMUX_P5_INPUT_DB_AMX \
-	IOMUXC_AUDMUX_P5_INPUT_DB_AMX_SELECT_INPUT
-#define MUX_IN_AUDMUX_P5_INPUT_RXCLK_AMX \
-	IOMUXC_AUDMUX_P5_INPUT_RXCLK_AMX_SELECT_INPUT
-#define MUX_IN_AUDMUX_P5_INPUT_RXFS_AMX \
-	IOMUXC_AUDMUX_P5_INPUT_RXFS_AMX_SELECT_INPUT
-#define MUX_IN_AUDMUX_P5_INPUT_TXCLK_AMX \
-	IOMUXC_AUDMUX_P5_INPUT_TXCLK_AMX_SELECT_INPUT
-#define MUX_IN_AUDMUX_P5_INPUT_TXFS_AMX \
-	IOMUXC_AUDMUX_P5_INPUT_TXFS_AMX_SELECT_INPUT
-#define MUX_IN_AUDMUX_P6_INPUT_DA_AMX \
-	IOMUXC_AUDMUX_P6_INPUT_DA_AMX_SELECT_INPUT
-#define MUX_IN_AUDMUX_P6_INPUT_DB_AMX \
-	IOMUXC_AUDMUX_P6_INPUT_DB_AMX_SELECT_INPUT
-#define MUX_IN_AUDMUX_P6_INPUT_RXCLK_AMX \
-	IOMUXC_AUDMUX_P6_INPUT_RXCLK_AMX_SELECT_INPUT
-#define MUX_IN_AUDMUX_P6_INPUT_RXFS_AMX \
-	IOMUXC_AUDMUX_P6_INPUT_RXFS_AMX_SELECT_INPUT
-#define MUX_IN_AUDMUX_P6_INPUT_TXCLK_AMX \
-	IOMUXC_AUDMUX_P6_INPUT_TXCLK_AMX_SELECT_INPUT
-#define MUX_IN_AUDMUX_P6_INPUT_TXFS_AMX \
-	IOMUXC_AUDMUX_P6_INPUT_TXFS_AMX_SELECT_INPUT
-#define MUX_IN_CCM_IPP_DI0_CLK \
-	IOMUXC_CCM_IPP_DI0_CLK_SELECT_INPUT
-#define MUX_IN_CCM_IPP_DI1_CLK \
-	IOMUXC_CCM_IPP_DI1_CLK_SELECT_INPUT
-#define MUX_IN_CCM_PLL1_BYPASS_CLK \
-	IOMUXC_CCM_PLL1_BYPASS_CLK_SELECT_INPUT
-#define MUX_IN_CCM_PLL2_BYPASS_CLK \
-	IOMUXC_CCM_PLL2_BYPASS_CLK_SELECT_INPUT
-#define MUX_IN_CSPI_IPP_CSPI_CLK_IN \
-	IOMUXC_CSPI_IPP_CSPI_CLK_IN_SELECT_INPUT
-#define MUX_IN_CSPI_IPP_IND_MISO \
-	IOMUXC_CSPI_IPP_IND_MISO_SELECT_INPUT
-#define MUX_IN_CSPI_IPP_IND_MOSI \
-	IOMUXC_CSPI_IPP_IND_MOSI_SELECT_INPUT
-#define MUX_IN_CSPI_IPP_IND_SS1_B \
-	IOMUXC_CSPI_IPP_IND_SS1_B_SELECT_INPUT
-#define MUX_IN_CSPI_IPP_IND_SS2_B \
-	IOMUXC_CSPI_IPP_IND_SS2_B_SELECT_INPUT
-#define MUX_IN_CSPI_IPP_IND_SS3_B \
-	IOMUXC_CSPI_IPP_IND_SS3_B_SELECT_INPUT
-#define MUX_IN_DPLLIP1_L1T_TOG_EN \
-	IOMUXC_DPLLIP1_L1T_TOG_EN_SELECT_INPUT
-#define MUX_IN_ECSPI2_IPP_IND_SS_B_1 \
-	IOMUXC_ECSPI2_IPP_IND_SS_B_1_SELECT_INPUT
-#define MUX_IN_ECSPI2_IPP_IND_SS_B_3 \
-	IOMUXC_ECSPI2_IPP_IND_SS_B_3_SELECT_INPUT
-#define MUX_IN_EMI_IPP_IND_RDY_INT \
-	IOMUXC_EMI_IPP_IND_RDY_INT_SELECT_INPUT
-#define MUX_IN_ESDHC3_IPP_DAT0_IN \
-	IOMUXC_ESDHC3_IPP_DAT0_IN_SELECT_INPUT
-#define MUX_IN_ESDHC3_IPP_DAT1_IN \
-	IOMUXC_ESDHC3_IPP_DAT1_IN_SELECT_INPUT
-#define MUX_IN_ESDHC3_IPP_DAT2_IN \
-	IOMUXC_ESDHC3_IPP_DAT2_IN_SELECT_INPUT
-#define MUX_IN_ESDHC3_IPP_DAT3_IN \
-	IOMUXC_ESDHC3_IPP_DAT3_IN_SELECT_INPUT
-#define MUX_IN_FEC_FEC_COL \
-	IOMUXC_FEC_FEC_COL_SELECT_INPUT
-#define MUX_IN_FEC_FEC_CRS \
-	IOMUXC_FEC_FEC_CRS_SELECT_INPUT
-#define MUX_IN_FEC_FEC_MDI \
-	IOMUXC_FEC_FEC_MDI_SELECT_INPUT
-#define MUX_IN_FEC_FEC_RDATA_0 \
-	IOMUXC_FEC_FEC_RDATA_0_SELECT_INPUT
-#define MUX_IN_FEC_FEC_RDATA_1 \
-	IOMUXC_FEC_FEC_RDATA_1_SELECT_INPUT
-#define MUX_IN_FEC_FEC_RDATA_2 \
-	IOMUXC_FEC_FEC_RDATA_2_SELECT_INPUT
-#define MUX_IN_FEC_FEC_RDATA_3 \
-	IOMUXC_FEC_FEC_RDATA_3_SELECT_INPUT
-#define MUX_IN_FEC_FEC_RX_CLK \
-	IOMUXC_FEC_FEC_RX_CLK_SELECT_INPUT
-#define MUX_IN_FEC_FEC_RX_DV \
-	IOMUXC_FEC_FEC_RX_DV_SELECT_INPUT
-#define MUX_IN_FEC_FEC_RX_ER \
-	IOMUXC_FEC_FEC_RX_ER_SELECT_INPUT
-#define MUX_IN_FEC_FEC_TX_CLK \
-	IOMUXC_FEC_FEC_TX_CLK_SELECT_INPUT
-#define MUX_IN_GPIO3_IPP_IND_G_IN_1 \
-	IOMUXC_GPIO3_IPP_IND_G_IN_1_SELECT_INPUT
-#define MUX_IN_GPIO3_IPP_IND_G_IN_2 \
-	IOMUXC_GPIO3_IPP_IND_G_IN_2_SELECT_INPUT
-#define MUX_IN_GPIO3_IPP_IND_G_IN_3 \
-	IOMUXC_GPIO3_IPP_IND_G_IN_3_SELECT_INPUT
-#define MUX_IN_GPIO3_IPP_IND_G_IN_4 \
-	IOMUXC_GPIO3_IPP_IND_G_IN_4_SELECT_INPUT
-#define MUX_IN_GPIO3_IPP_IND_G_IN_5 \
-	IOMUXC_GPIO3_IPP_IND_G_IN_5_SELECT_INPUT
-#define MUX_IN_GPIO3_IPP_IND_G_IN_6 \
-	IOMUXC_GPIO3_IPP_IND_G_IN_6_SELECT_INPUT
-#define MUX_IN_GPIO3_IPP_IND_G_IN_7 \
-	IOMUXC_GPIO3_IPP_IND_G_IN_7_SELECT_INPUT
-#define MUX_IN_GPIO3_IPP_IND_G_IN_8 \
-	IOMUXC_GPIO3_IPP_IND_G_IN_8_SELECT_INPUT
-#define MUX_IN_GPIO3_IPP_IND_G_IN_12 \
-	IOMUXC_GPIO3_IPP_IND_G_IN_12_SELECT_INPUT
-#define MUX_IN_HSC_MIPI_MIX_PAR0_VSYNC \
-	IOMUXC_HSC_MIPI_MIX_PAR0_VSYNC_SELECT_INPUT
-#define MUX_IN_HSC_MIPI_MIX_PAR1_DI_WAIT \
-	IOMUXC_HSC_MIPI_MIX_PAR1_DI_WAIT_SELECT_INPUT
-#define MUX_IN_HSC_MIPI_MIX_PAR_SISG_TRIG \
-	IOMUXC_HSC_MIPI_MIX_PAR_SISG_TRIG_SELECT_INPUT
-#define MUX_IN_I2C1_IPP_SCL_IN \
-	IOMUXC_I2C1_IPP_SCL_IN_SELECT_INPUT
-#define MUX_IN_I2C1_IPP_SDA_IN \
-	IOMUXC_I2C1_IPP_SDA_IN_SELECT_INPUT
-#define MUX_IN_I2C2_IPP_SCL_IN \
-	IOMUXC_I2C2_IPP_SCL_IN_SELECT_INPUT
-#define MUX_IN_I2C2_IPP_SDA_IN \
-	IOMUXC_I2C2_IPP_SDA_IN_SELECT_INPUT
-#define MUX_IN_IPU_IPP_DI_0_IND_DISPB_SD_D \
-	IOMUXC_IPU_IPP_DI_0_IND_DISPB_SD_D_SELECT_INPUT
-#define MUX_IN_IPU_IPP_DI_1_IND_DISPB_SD_D \
-	IOMUXC_IPU_IPP_DI_1_IND_DISPB_SD_D_SELECT_INPUT
-#define MUX_IN_KPP_IPP_IND_COL_6 \
-	IOMUXC_KPP_IPP_IND_COL_6_SELECT_INPUT
-#define MUX_IN_KPP_IPP_IND_COL_7 \
-	IOMUXC_KPP_IPP_IND_COL_7_SELECT_INPUT
-#define MUX_IN_KPP_IPP_IND_ROW_4 \
-	IOMUXC_KPP_IPP_IND_ROW_4_SELECT_INPUT
-#define MUX_IN_KPP_IPP_IND_ROW_5 \
-	IOMUXC_KPP_IPP_IND_ROW_5_SELECT_INPUT
-#define MUX_IN_KPP_IPP_IND_ROW_6 \
-	IOMUXC_KPP_IPP_IND_ROW_6_SELECT_INPUT
-#define MUX_IN_KPP_IPP_IND_ROW_7 \
-	IOMUXC_KPP_IPP_IND_ROW_7_SELECT_INPUT
-#define MUX_IN_UART1_IPP_UART_RTS_B \
-	IOMUXC_UART1_IPP_UART_RTS_B_SELECT_INPUT
-#define MUX_IN_UART1_IPP_UART_RXD_MUX \
-	IOMUXC_UART1_IPP_UART_RXD_MUX_SELECT_INPUT
-#define MUX_IN_UART2_IPP_UART_RTS_B \
-	IOMUXC_UART2_IPP_UART_RTS_B_SELECT_INPUT
-#define MUX_IN_UART2_IPP_UART_RXD_MUX \
-	IOMUXC_UART2_IPP_UART_RXD_MUX_SELECT_INPUT
-#define MUX_IN_UART3_IPP_UART_RTS_B \
-	IOMUXC_UART3_IPP_UART_RTS_B_SELECT_INPUT
-#define MUX_IN_UART3_IPP_UART_RXD_MUX \
-	IOMUXC_UART3_IPP_UART_RXD_MUX_SELECT_INPUT
-#define MUX_IN_USBOH3_IPP_IND_UH3_CLK \
-	IOMUXC_USBOH3_IPP_IND_UH3_CLK_SELECT_INPUT
-#define MUX_IN_USBOH3_IPP_IND_UH3_DATA_0 \
-	IOMUXC_USBOH3_IPP_IND_UH3_DATA_0_SELECT_INPUT
-#define MUX_IN_USBOH3_IPP_IND_UH3_DATA_1 \
-	IOMUXC_USBOH3_IPP_IND_UH3_DATA_1_SELECT_INPUT
-#define MUX_IN_USBOH3_IPP_IND_UH3_DATA_2 \
-	IOMUXC_USBOH3_IPP_IND_UH3_DATA_2_SELECT_INPUT
-#define MUX_IN_USBOH3_IPP_IND_UH3_DATA_3 \
-	IOMUXC_USBOH3_IPP_IND_UH3_DATA_3_SELECT_INPUT
-#define MUX_IN_USBOH3_IPP_IND_UH3_DATA_4 \
-	IOMUXC_USBOH3_IPP_IND_UH3_DATA_4_SELECT_INPUT
-#define MUX_IN_USBOH3_IPP_IND_UH3_DATA_5 \
-	IOMUXC_USBOH3_IPP_IND_UH3_DATA_5_SELECT_INPUT
-#define MUX_IN_USBOH3_IPP_IND_UH3_DATA_6 \
-	IOMUXC_USBOH3_IPP_IND_UH3_DATA_6_SELECT_INPUT
-#define MUX_IN_USBOH3_IPP_IND_UH3_DATA_7 \
-	IOMUXC_USBOH3_IPP_IND_UH3_DATA_7_SELECT_INPUT
-#define MUX_IN_USBOH3_IPP_IND_UH3_DIR \
-	IOMUXC_USBOH3_IPP_IND_UH3_DIR_SELECT_INPUT
-#define MUX_IN_USBOH3_IPP_IND_UH3_NXT \
-	IOMUXC_USBOH3_IPP_IND_UH3_NXT_SELECT_INPUT
-#define MUX_IN_USBOH3_IPP_IND_UH3_STP \
-	IOMUXC_USBOH3_IPP_IND_UH3_STP_SELECT_INPUT
+#define MUX_SELECT(name) (name##_SELECT_INPUT)
 
 #endif /* _IMX51_IOMUXREG_H */
 
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/sys/arch/arm/imx/imx51_ipuv3.c	Sun Apr 29 23:04:36 2012 +0000
@@ -0,0 +1,1288 @@
+/*	$NetBSD: imx51_ipuv3.c,v 1.1.2.2 2012/04/29 23:04:38 mrg Exp $	*/
+
+/*
+ * Copyright (c) 2011, 2012  Genetec Corporation.  All rights reserved.
+ * Written by Hashimoto Kenichi for Genetec Corporation.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY GENETEC CORPORATION ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL GENETEC CORPORATION
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>
+__KERNEL_RCSID(0, "$NetBSD: imx51_ipuv3.c,v 1.1.2.2 2012/04/29 23:04:38 mrg Exp $");
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/conf.h>
+#include <sys/uio.h>
+#include <sys/malloc.h>
+#include <sys/kernel.h>			/* for cold */
+
+#include <uvm/uvm_extern.h>
+
+#include <dev/cons.h>
+#include <dev/wscons/wsconsio.h>
+#include <dev/wscons/wsdisplayvar.h>
+#include <dev/wscons/wscons_callbacks.h>
+#include <dev/rasops/rasops.h>
+#include <dev/wsfont/wsfont.h>
+#include <dev/wscons/wsdisplay_vconsvar.h>
+
+#include <sys/bus.h>
+#include <machine/cpu.h>
+#include <arm/cpufunc.h>
+
+#include <arm/imx/imx51var.h>
+#include <arm/imx/imx51reg.h>
+#include <arm/imx/imx51_ipuv3var.h>
+#include <arm/imx/imx51_ipuv3reg.h>
+#include <arm/imx/imx51_ccmvar.h>
+#include <arm/imx/imx51_ccmreg.h>
+
+#include "imxccm.h"	/* if CCM driver is configured into the kernel */
+#include "wsdisplay.h"
+#include "opt_imx51_ipuv3.h"
+
+/*
+ * Console variables. These are necessary since console is setup very early,
+ * before devices get attached.
+ */
+struct {
+	int				is_console;
+} imx51_ipuv3_console;
+
+#define	IPUV3_READ(ipuv3, module, reg)					      \
+	bus_space_read_4((ipuv3)->iot, (ipuv3)->module##_ioh, (reg))
+#define	IPUV3_WRITE(ipuv3, module, reg, val)				      \
+	bus_space_write_4((ipuv3)->iot, (ipuv3)->module##_ioh, (reg), (val))
+
+#ifdef IPUV3_DEBUG
+int ipuv3_debug = IPUV3_DEBUG;
+#define	DPRINTFN(n,x)   if (ipuv3_debug>(n)) printf x; else
+#else
+#define	DPRINTFN(n,x)
+#endif
+
+int ipuv3intr(void *);
+
+static void imx51_ipuv3_initialize(struct imx51_ipuv3_softc *,
+    const struct lcd_panel_geometry *);
+#if NWSDISPLAY > 0
+static void imx51_ipuv3_setup_rasops(struct imx51_ipuv3_softc *,
+    struct rasops_info *, struct imx51_wsscreen_descr *,
+    const struct lcd_panel_geometry *);
+#endif
+static void imx51_ipuv3_set_idma_param(uint32_t *, uint32_t, uint32_t);
+
+#if NWSDISPLAY > 0
+/*
+ * wsdisplay glue
+ */
+static struct imx51_wsscreen_descr imx51_ipuv3_stdscreen = {
+	.c = {
+		.name	      = "std",
+		.ncols	      = 0,
+		.nrows	      = 0,
+		.textops      = NULL,
+		.fontwidth    = 8,
+		.fontheight   = 16,
+		.capabilities = WSSCREEN_WSCOLORS | WSSCREEN_HILIT,
+		.modecookie   = NULL
+	},
+	.depth = 16,		/* bits per pixel */
+	.flags = RI_CENTER | RI_FULLCLEAR
+};
+
+static const struct wsscreen_descr *imx51_ipuv3_scr_descr[] = {
+	&imx51_ipuv3_stdscreen.c,
+};
+
+const struct wsscreen_list imx51_ipuv3_screen_list = {
+	sizeof imx51_ipuv3_scr_descr / sizeof imx51_ipuv3_scr_descr[0],
+	imx51_ipuv3_scr_descr
+};
+
+struct wsdisplay_accessops imx51_ipuv3_accessops = {
+	.ioctl	      = imx51_ipuv3_ioctl,
+	.mmap	      = imx51_ipuv3_mmap,
+	.alloc_screen = NULL,
+	.free_screen  = NULL,
+	.show_screen  = NULL,
+	.load_font    = NULL,
+	.pollc	      = NULL,
+	.scroll	      = NULL
+};
+#endif
+
+#ifdef IPUV3_DEBUG
+static void
+imx51_ipuv3_dump(struct imx51_ipuv3_softc *sc)
+{
+	int i;
+
+	DPRINTFN(5, ("%s : %d\n", __func__, __LINE__));
+
+#define	__DUMP(grp, reg)						\
+	DPRINTFN(4, ("%-16s = 0x%08X\n", #reg, IPUV3_READ(sc, grp, IPU_##reg)))
+
+	__DUMP(cm, CM_CONF);
+	__DUMP(cm, CM_DISP_GEN);
+	__DUMP(idmac, IDMAC_CONF);
+	__DUMP(idmac, IDMAC_CH_EN_1);
+	__DUMP(idmac, IDMAC_CH_EN_2);
+	__DUMP(idmac, IDMAC_CH_PRI_1);
+	__DUMP(idmac, IDMAC_CH_PRI_2);
+	__DUMP(idmac, IDMAC_BNDM_EN_1);
+	__DUMP(idmac, IDMAC_BNDM_EN_2);
+	__DUMP(cm, CM_CH_DB_MODE_SEL_0);
+	__DUMP(cm, CM_CH_DB_MODE_SEL_1);
+	__DUMP(dmfc, DMFC_WR_CHAN);
+	__DUMP(dmfc, DMFC_WR_CHAN_DEF);
+	__DUMP(dmfc, DMFC_DP_CHAN);
+	__DUMP(dmfc, DMFC_DP_CHAN_DEF);
+	__DUMP(dmfc, DMFC_IC_CTRL);
+	__DUMP(cm, CM_FS_PROC_FLOW1);
+	__DUMP(cm, CM_FS_PROC_FLOW2);
+	__DUMP(cm, CM_FS_PROC_FLOW3);
+	__DUMP(cm, CM_FS_DISP_FLOW1);
+	__DUMP(dc, DC_DISP_CONF1_0);
+	__DUMP(dc, DC_DISP_CONF2_0);
+	__DUMP(dc, DC_WR_CH_CONF_5);
+
+	printf("*** IPU ***\n");
+	for (i = 0; i <= 0x17c; i += 4)
+		DPRINTFN(6, ("0x%08X = 0x%08X\n", i, IPUV3_READ(sc, cm, i)));
+	printf("*** IDMAC ***\n");
+	for (i = 0; i <= 0x104; i += 4)
+		DPRINTFN(6, ("0x%08X = 0x%08X\n", i, IPUV3_READ(sc, idmac, i)));
+	printf("*** CPMEM ***\n");
+	for (i = 0x5c0; i <= 0x600; i += 4)
+		DPRINTFN(6, ("0x%08X = 0x%08X\n", i, IPUV3_READ(sc, cpmem, i)));
+
+#undef __DUMP
+
+}
+#endif
+
+static void
+imx51_ipuv3_enable_display(struct imx51_ipuv3_softc *sc)
+{
+	uint32_t reg = 0;
+
+	DPRINTFN(5, ("%s : %d\n", __func__, __LINE__));
+
+	/* enable sub modules */
+	reg = IPUV3_READ(sc, cm, IPU_CM_CONF);
+	reg |= CM_CONF_DP_EN |
+	    CM_CONF_DC_EN |
+	    CM_CONF_DMFC_EN |
+	    CM_CONF_DI0_EN;
+	IPUV3_WRITE(sc, cm, IPU_CM_CONF, reg);
+}
+
+static void
+imx51_ipuv3_dmfc_init(struct imx51_ipuv3_softc *sc)
+{
+	DPRINTFN(5, ("%s : %d\n", __func__, __LINE__));
+
+	/* IC channel is disabled */
+	IPUV3_WRITE(sc, dmfc, IPU_DMFC_IC_CTRL,
+	    IC_IN_PORT_DISABLE);
+
+	IPUV3_WRITE(sc, dmfc, IPU_DMFC_WR_CHAN, 0x00000000);
+	IPUV3_WRITE(sc, dmfc, IPU_DMFC_WR_CHAN_DEF, 0x20202020);
+	IPUV3_WRITE(sc, dmfc, IPU_DMFC_DP_CHAN, 0x00000094);
+	IPUV3_WRITE(sc, dmfc, IPU_DMFC_DP_CHAN_DEF, 0x202020F6);
+
+	IPUV3_WRITE(sc, dmfc, IPU_DMFC_GENERAL1,
+	    DCDP_SYNC_PR_ROUNDROBIN);
+
+#ifdef IPUV3_DEBUG
+	int i;
+	printf("*** DMFC ***\n");
+	for (i = 0; i <= 0x34; i += 4)
+		printf("0x%08X = 0x%08X\n", i, IPUV3_READ(sc, dmfc, i));
+
+	printf("%s: DMFC_IC_CTRL         0x%08X\n", __func__,
+	    IPUV3_READ(sc, dmfc, IPU_DMFC_IC_CTRL));
+	printf("%s: IPU_DMFC_WR_CHAN     0x%08X\n", __func__,
+	    IPUV3_READ(sc, dmfc, IPU_DMFC_WR_CHAN));
+	printf("%s: IPU_DMFC_WR_CHAN_DEF 0x%08X\n", __func__,
+	    IPUV3_READ(sc, dmfc, IPU_DMFC_WR_CHAN_DEF));
+	printf("%s: IPU_DMFC_GENERAL1    0x%08X\n", __func__,
+	    IPUV3_READ(sc, dmfc, IPU_DMFC_GENERAL1));
+#endif
+}
+
+static void
+imx51_ipuv3_dc_map_clear(struct imx51_ipuv3_softc *sc, int map)
+{
+	DPRINTFN(5, ("%s : %d\n", __func__, __LINE__));
+
+	uint32_t reg;
+	uint32_t addr;
+
+	addr = IPU_DC_MAP_CONF_PNTR(map / 2);
+	reg = IPUV3_READ(sc, dc, addr);
+	reg &= ~(0xFFFF << (16 * (map & 0x1)));
+	IPUV3_WRITE(sc, dc, addr, reg);
+}
+
+static void
+imx51_ipuv3_dc_map_conf(struct imx51_ipuv3_softc *sc,
+    int map, int byte, int offset, uint8_t mask)
+{
+	DPRINTFN(5, ("%s : %d\n", __func__, __LINE__));
+
+	uint32_t reg;
+	uint32_t addr;
+
+	addr = IPU_DC_MAP_CONF_MASK((map * 3 + byte) / 2);
+	reg = IPUV3_READ(sc, dc, addr);
+	reg &= ~(0xFFFF << (16 * ((map * 3 + byte) & 0x1)));
+	reg |= ((offset << 8) | mask) << (16 * ((map * 3 + byte) & 0x1));
+	IPUV3_WRITE(sc, dc, addr, reg);
+#ifdef IPUV3_DEBUG
+	printf("%s: addr 0x%08X reg 0x%08X\n", __func__, addr, reg);
+#endif
+
+	addr = IPU_DC_MAP_CONF_PNTR(map / 2);
+	reg = IPUV3_READ(sc, dc, addr);
+	reg &= ~(0x1F << ((16 * (map & 0x1)) + (5 * byte)));
+	reg |= ((map * 3) + byte) << ((16 * (map & 0x1)) + (5 * byte));
+	IPUV3_WRITE(sc, dc, addr, reg);
+#ifdef IPUV3_DEBUG
+	printf("%s: addr 0x%08X reg 0x%08X\n", __func__, addr, reg);
+#endif
+}
+
+static void
+imx51_ipuv3_dc_template_command(struct imx51_ipuv3_softc *sc,
+    int index, int sync, int gluelogic, int waveform, int mapping,
+    int operand, int opecode, int stop)
+{
+	DPRINTFN(5, ("%s : %d\n", __func__, __LINE__));
+
+	uint32_t reg;
+
+	reg = (sync << 0) |
+	    (gluelogic << 4) |
+	    (waveform << 11) |
+	    (mapping << 15) |
+	    (operand << 20);
+	IPUV3_WRITE(sc, dctmpl, index * 8, reg);
+#ifdef IPUV3_DEBUG
+	printf("%s: addr 0x%08X reg 0x%08X\n", __func__, index * 8, reg);
+#endif
+	reg = (opecode << 0) |
+	    (stop << 9);
+	IPUV3_WRITE(sc, dctmpl, index * 8 + 4, reg);
+#ifdef IPUV3_DEBUG
+	printf("%s: addr 0x%08X reg 0x%08X\n", __func__, index * 8 + 4, reg);
+#endif
+}
+
+static void
+imx51_ipuv3_set_routine_link(struct imx51_ipuv3_softc *sc,
+    int base, int evt, int addr, int pri)
+{
+	DPRINTFN(5, ("%s : %d\n", __func__, __LINE__));
+
+	uint32_t reg;
+
+	reg = IPUV3_READ(sc, dc, IPU_DC_RL(base, evt));
+	reg &= ~(0xFFFF << (16 * (evt & 0x1)));
+	reg |= ((addr << 8) | pri) << (16 * (evt & 0x1));
+	IPUV3_WRITE(sc, dc, IPU_DC_RL(base, evt), reg);
+#ifdef IPUV3_DEBUG
+	printf("%s: event %d addr %d priority %d\n", __func__,
+	    evt, addr, pri);
+	printf("%s: %p = 0x%08X\n", __func__,
+	    (void *)IPU_DC_RL(base, evt), reg);
+#endif
+}
+
+static void
+imx51_ipuv3_dc_init(struct imx51_ipuv3_softc *sc)
+{
+	uint32_t reg;
+
+	DPRINTFN(5, ("%s : %d\n", __func__, __LINE__));
+
+	imx51_ipuv3_dc_map_clear(sc, 0);
+	imx51_ipuv3_dc_map_conf(sc, 0, 0,  7, 0xff);
+	imx51_ipuv3_dc_map_conf(sc, 0, 1, 15, 0xff);
+	imx51_ipuv3_dc_map_conf(sc, 0, 2, 23, 0xff);
+	imx51_ipuv3_dc_map_clear(sc, 1);
+	imx51_ipuv3_dc_map_conf(sc, 1, 0,  5, 0xfc);
+	imx51_ipuv3_dc_map_conf(sc, 1, 1, 11, 0xfc);
+	imx51_ipuv3_dc_map_conf(sc, 1, 2, 17, 0xfc);
+	imx51_ipuv3_dc_map_clear(sc, 2);
+	imx51_ipuv3_dc_map_conf(sc, 2, 0, 15, 0xff);
+	imx51_ipuv3_dc_map_conf(sc, 2, 1, 23, 0xff);
+	imx51_ipuv3_dc_map_conf(sc, 2, 2,  7, 0xff);
+	imx51_ipuv3_dc_map_clear(sc, 3);
+	imx51_ipuv3_dc_map_conf(sc, 3, 0,  4, 0xf8);
+	imx51_ipuv3_dc_map_conf(sc, 3, 1, 10, 0xfc);
+	imx51_ipuv3_dc_map_conf(sc, 3, 2, 15, 0xf8);
+	imx51_ipuv3_dc_map_clear(sc, 4);
+	imx51_ipuv3_dc_map_conf(sc, 4, 0,  5, 0xfc);
+	imx51_ipuv3_dc_map_conf(sc, 4, 1, 13, 0xfc);
+	imx51_ipuv3_dc_map_conf(sc, 4, 2, 21, 0xfc);
+
+	/* microcode */
+	imx51_ipuv3_dc_template_command(sc,
+	    5, 5, 8, 1, 5, 0, 0x180, 1);
+	imx51_ipuv3_dc_template_command(sc,
+	    6, 5, 4, 1, 5, 0, 0x180, 1);
+	imx51_ipuv3_dc_template_command(sc,
+	    7, 5, 0, 1, 5, 0, 0x180, 1);
+
+	reg = (4 << 5) | 0x2;
+	IPUV3_WRITE(sc, dc, IPU_DC_WR_CH_CONF_5, reg);
+	IPUV3_WRITE(sc, dc, IPU_DC_WR_CH_CONF_1, 0x4);
+	IPUV3_WRITE(sc, dc, IPU_DC_WR_CH_ADDR_5, 0x0);
+	IPUV3_WRITE(sc, dc, IPU_DC_GEN, 0x44);
+
+	imx51_ipuv3_set_routine_link(sc, DC_RL_CH_5, DC_RL_EVT_NL, 5, 3);
+	imx51_ipuv3_set_routine_link(sc, DC_RL_CH_5, DC_RL_EVT_EOL, 6, 2);
+	imx51_ipuv3_set_routine_link(sc, DC_RL_CH_5, DC_RL_EVT_NEW_DATA, 7, 1);
+	imx51_ipuv3_set_routine_link(sc, DC_RL_CH_5, DC_RL_EVT_NF, 0, 0);
+	imx51_ipuv3_set_routine_link(sc, DC_RL_CH_5, DC_RL_EVT_NFIELD, 0, 0);
+	imx51_ipuv3_set_routine_link(sc, DC_RL_CH_5, DC_RL_EVT_EOF, 0, 0);
+	imx51_ipuv3_set_routine_link(sc, DC_RL_CH_5, DC_RL_EVT_EOFIELD, 0, 0);
+	imx51_ipuv3_set_routine_link(sc, DC_RL_CH_5, DC_RL_EVT_NEW_CHAN, 0, 0);
+	imx51_ipuv3_set_routine_link(sc, DC_RL_CH_5, DC_RL_EVT_NEW_ADDR, 0, 0);
+
+#ifdef IPUV3_DEBUG
+	int i;
+	printf("*** DC ***\n");
+	for (i = 0; i <= 0x1C8; i += 4)
+		printf("0x%08X = 0x%08X\n", i, IPUV3_READ(sc, dc, i));
+	printf("*** DCTEMPL ***\n");
+	for (i = 0; i <= 0x100; i += 4)
+		printf("0x%08X = 0x%08X\n", i, IPUV3_READ(sc, dctmpl, i));
+#endif
+}
+
+static void
+imx51_ipuv3_dc_display_config(struct imx51_ipuv3_softc *sc, int width)
+{
+	DPRINTFN(5, ("%s : %d\n", __func__, __LINE__));
+
+	IPUV3_WRITE(sc, dc, IPU_DC_DISP_CONF2_0, width);
+}
+
+static void
+imx51_ipuv3_di_sync_conf(struct imx51_ipuv3_softc *sc, int no,
+    uint32_t reg_gen0, uint32_t reg_gen1, uint32_t repeat)
+{
+	DPRINTFN(5, ("%s : %d\n", __func__, __LINE__));
+
+	uint32_t reg;
+
+	IPUV3_WRITE(sc, di0, IPU_DI_SW_GEN0(no), reg_gen0);
+	IPUV3_WRITE(sc, di0, IPU_DI_SW_GEN1(no), reg_gen1);
+	reg = IPUV3_READ(sc, di0, IPU_DI_STP_REP(no));
+	reg &= ~DI_STP_REP_MASK(no);
+	reg |= repeat << DI_STP_REP_SHIFT(no);
+	IPUV3_WRITE(sc, di0, IPU_DI_STP_REP(no), reg);
+
+#ifdef IPUV3_DEBUG
+	printf("%s: no %d\n", __func__, no);
+	printf("%s: addr 0x%08X reg_gen0   0x%08X\n", __func__,
+	    IPU_DI_SW_GEN0(no), reg_gen0);
+	printf("%s: addr 0x%08X reg_gen1   0x%08X\n", __func__,
+	    IPU_DI_SW_GEN1(no), reg_gen1);
+	printf("%s: addr 0x%08X DI_STP_REP 0x%08X\n", __func__,
+	    IPU_DI_STP_REP(no), reg);
+#endif
+}
+
+static void
+imx51_ipuv3_di_init(struct imx51_ipuv3_softc *sc)
+{
+	DPRINTFN(5, ("%s : %d\n", __func__, __LINE__));
+
+	uint32_t reg;
+	uint32_t div;
+	u_int ipuclk;
+	const struct lcd_panel_geometry *geom = sc->geometry;
+
+#if NIMXCCM > 0
+	ipuclk = imx51_get_clock(IMX51CLK_IPU_HSP_CLK_ROOT);
+#elif !defined(IMX51_IPU_HSP_CLOCK)
+#error	IMX51_CPU_HSP_CLOCK need to be defined.
+#else
+	ipuclk = IMX51_IPU_HSP_CLOCK;
+#endif
+	DPRINTFN(3, ("IPU HSP clock = %d\n", ipuclk));
+	div = (ipuclk * 16) / geom->pixel_clk;
+	div = div < 16 ? 16 : div & 0xff8;
+
+	/* DI counter */
+	reg = IPUV3_READ(sc, cm, IPU_CM_DISP_GEN);
+	reg &= ~(CM_DISP_GEN_DI1_COUNTER_RELEASE |
+	    CM_DISP_GEN_DI0_COUNTER_RELEASE);
+	IPUV3_WRITE(sc, cm, IPU_CM_DISP_GEN, reg);
+
+	IPUV3_WRITE(sc, di0, IPU_DI_BS_CLKGEN0, div);
+	IPUV3_WRITE(sc, di0, IPU_DI_BS_CLKGEN1,
+	    (div / 16) << DI_BS_CLKGEN1_DOWN_SHIFT);
+#ifdef IPUV3_DEBUG
+	printf("%s: IPU_DI_BS_CLKGEN0 = 0x%08X\n", __func__,
+	    IPUV3_READ(sc, di0, IPU_DI_BS_CLKGEN0));
+	printf("%s: IPU_DI_BS_CLKGEN1 = 0x%08X\n", __func__,
+	    IPUV3_READ(sc, di0, IPU_DI_BS_CLKGEN1));
+#endif
+	/* Display Time settings */
+	reg = ((div / 16 - 1) << DI_DW_GEN_ACCESS_SIZE_SHIFT) |
+	    ((div / 16 - 1) << DI_DW_GEN_COMPONNENT_SIZE_SHIFT) |
+	    (3 << DI_DW_GEN_PIN_SHIFT(15));
+	IPUV3_WRITE(sc, di0, IPU_DI_DW_GEN(0), reg);
+#ifdef IPUV3_DEBUG
+	printf("%s: div = %d\n", __func__, div);
+	printf("%s: IPU_DI_DW_GEN(0) 0x%08X = 0x%08X\n", __func__,
+	    IPU_DI_DW_GEN(0), reg);
+#endif
+
+	/* Up & Down Data Wave Set */
+	reg = (div / 16 * 2) << DI_DW_SET_DOWN_SHIFT;
+	IPUV3_WRITE(sc, di0, IPU_DI_DW_SET(0, 3), reg);
+#ifdef IPUV3_DEBUG
+	printf("%s: IPU_DI_DW_SET(0, 3) 0x%08X = 0x%08X\n", __func__,
+	    IPU_DI_DW_SET(0, 3), reg);
+#endif
+
+	/* internal HSCYNC */
+	imx51_ipuv3_di_sync_conf(sc, 1,
+	    __DI_SW_GEN0(geom->panel_width + geom->hsync_width +
+		geom->left + geom->right - 1, 1, 0, 0),
+	    __DI_SW_GEN1(0, 1, 0, 0, 0, 0, 0),
+	    0);
+
+	/* HSYNC */
+	imx51_ipuv3_di_sync_conf(sc, 2,
+	    __DI_SW_GEN0(geom->panel_width + geom->hsync_width +
+		geom->left + geom->right - 1, 1, 0, 1),
+	    __DI_SW_GEN1(1, 1, 0, geom->hsync_width * 2, 1, 0, 0),
+	    0);
+
+	/* VSYNC */
+	imx51_ipuv3_di_sync_conf(sc, 3,
+	    __DI_SW_GEN0(geom->panel_height + geom->vsync_width +
+		geom->upper + geom->lower - 1, 2, 0, 0),
+	    __DI_SW_GEN1(1, 1, 0, geom->vsync_width * 2, 2, 0, 0),
+	    0);
+
+	IPUV3_WRITE(sc, di0, IPU_DI_SCR_CONF,
+	    geom->panel_height + geom->vsync_width + geom->upper +
+	    geom->lower - 1);
+
+	/* Active Lines Start */
+	imx51_ipuv3_di_sync_conf(sc, 4,
+	    __DI_SW_GEN0(0, 3, geom->vsync_width + geom->upper, 3),
+	    __DI_SW_GEN1(0, 0, 4, 0, 0, 0, 0),
+	    geom->panel_height);
+
+	/* Active Clock Start */
+	imx51_ipuv3_di_sync_conf(sc, 5,
+	    __DI_SW_GEN0(0, 1, geom->hsync_width + geom->left, 1),
+	    __DI_SW_GEN1(0, 0, 5, 0, 0, 0, 0),
+	    geom->panel_width);
+
+	IPUV3_WRITE(sc, di0, IPU_DI_SW_GEN0(6), 0);
+	IPUV3_WRITE(sc, di0, IPU_DI_SW_GEN1(6), 0);
+	IPUV3_WRITE(sc, di0, IPU_DI_SW_GEN0(7), 0);
+	IPUV3_WRITE(sc, di0, IPU_DI_SW_GEN1(7), 0);
+	IPUV3_WRITE(sc, di0, IPU_DI_SW_GEN0(8), 0);
+	IPUV3_WRITE(sc, di0, IPU_DI_SW_GEN1(8), 0);
+	IPUV3_WRITE(sc, di0, IPU_DI_SW_GEN0(9), 0);
+	IPUV3_WRITE(sc, di0, IPU_DI_SW_GEN1(9), 0);
+
+	reg = IPUV3_READ(sc, di0, IPU_DI_STP_REP(6));
+	reg &= ~DI_STP_REP_MASK(6);
+	IPUV3_WRITE(sc, di0, IPU_DI_STP_REP(6), reg);
+	IPUV3_WRITE(sc, di0, IPU_DI_STP_REP(7), 0);
+	IPUV3_WRITE(sc, di0, IPU_DI_STP_REP(9), 0);
+
+	IPUV3_WRITE(sc, di0, IPU_DI_GENERAL, 0);
+	reg = ((3 - 1) << DI_SYNC_AS_GEN_VSYNC_SEL_SHIFT) | 0x2;
+	IPUV3_WRITE(sc, di0, IPU_DI_SYNC_AS_GEN, reg);
+	IPUV3_WRITE(sc, di0, IPU_DI_POL, DI_POL_DRDY_POLARITY_15);
+
+	/* release DI counter */
+	reg = IPUV3_READ(sc, cm, IPU_CM_DISP_GEN);
+	reg |= CM_DISP_GEN_DI0_COUNTER_RELEASE;
+	IPUV3_WRITE(sc, cm, IPU_CM_DISP_GEN, reg);
+
+#ifdef IPUV3_DEBUG
+	int i;
+	printf("*** DI0 ***\n");
+	for (i = 0; i <= 0x174; i += 4)
+		printf("0x%08X = 0x%08X\n", i, IPUV3_READ(sc, di0, i));
+
+	printf("%s: IPU_CM_DISP_GEN    : 0x%08X\n", __func__,
+	    IPUV3_READ(sc, cm, IPU_CM_DISP_GEN));
+	printf("%s: IPU_DI_SYNC_AS_GEN : 0x%08X\n", __func__,
+	    IPUV3_READ(sc, di0, IPU_DI_SYNC_AS_GEN));
+	printf("%s: IPU_DI_GENERAL     : 0x%08X\n", __func__,
+	    IPUV3_READ(sc, di0, IPU_DI_GENERAL));
+	printf("%s: IPU_DI_POL         : 0x%08X\n", __func__,
+	    IPUV3_READ(sc, di0, IPU_DI_POL));
+#endif
+}
+
+
+void
+imx51_ipuv3_geometry(struct imx51_ipuv3_softc *sc,
+    const struct lcd_panel_geometry *geom)
+{
+	DPRINTFN(5, ("%s : %d\n", __func__, __LINE__));
+
+	sc->geometry = geom;
+
+#ifdef IPUV3_DEBUG
+	printf("%s: screen height = %d\n",__func__ , geom->panel_height);
+	printf("%s:        width  = %d\n",__func__ , geom->panel_width);
+	printf("%s: IPU Clock = %d\n", __func__,
+	    imx51_get_clock(IMX51CLK_IPU_HSP_CLK_ROOT));
+	printf("%s: Pixel Clock = %d\n", __func__, geom->pixel_clk);
+#endif
+
+	imx51_ipuv3_di_init(sc);
+
+#ifdef IPUV3_DEBUG
+	printf("%s: IPU_CM_DISP_GEN    : 0x%08X\n", __func__,
+	    IPUV3_READ(sc, cm, IPU_CM_DISP_GEN));
+#endif
+
+	imx51_ipuv3_dc_display_config(sc, geom->panel_width);
+
+	return;
+}
+
+/*
+ * Initialize the IPUV3 controller.
+ */
+static void
+imx51_ipuv3_initialize(struct imx51_ipuv3_softc *sc,
+    const struct lcd_panel_geometry *geom)
+{
+	uint32_t reg;
+
+	DPRINTFN(5, ("%s : %d\n", __func__, __LINE__));
+
+	IPUV3_WRITE(sc, cm, IPU_CM_CONF, 0);
+
+	/* reset */
+	IPUV3_WRITE(sc, cm, IPU_CM_MEM_RST, CM_MEM_START | CM_MEM_EN);
+	while (IPUV3_READ(sc, cm, IPU_CM_MEM_RST) & CM_MEM_START)
+		; /* wait */
+
+	imx51_ipuv3_dmfc_init(sc);
+	imx51_ipuv3_dc_init(sc);
+
+	imx51_ipuv3_geometry(sc, geom);
+
+	/* set global alpha */
+	IPUV3_WRITE(sc, dp, IPU_DP_GRAPH_WIND_CTRL_SYNC, 0x80 << 24);
+	IPUV3_WRITE(sc, dp, IPU_DP_COM_CONF_SYNC, DP_DP_GWAM_SYNC);
+
+	reg = IPUV3_READ(sc, cm, IPU_CM_DISP_GEN);
+	reg |= CM_DISP_GEN_MCU_MAX_BURST_STOP |
+	    CM_DISP_GEN_MCU_T(0x8);
+	IPUV3_WRITE(sc, cm, IPU_CM_DISP_GEN, reg);
+}
+
+static void
+imx51_ipuv3_init_screen(void *cookie, struct vcons_screen *scr,
+		    int existing, long *defattr)
+{
+	DPRINTFN(5, ("%s : %d\n", __func__, __LINE__));
+
+	struct imx51_ipuv3_softc *sc = cookie;
+	struct rasops_info *ri = &scr->scr_ri;
+	struct imx51_wsscreen_descr *descr = &imx51_ipuv3_stdscreen;
+
+	if ((scr == &sc->console) && (sc->vd.active != NULL))
+		return;
+
+	ri->ri_bits = sc->active->buf_va;
+
+	scr->scr_flags |= VCONS_DONT_READ;
+	if (existing)
+		ri->ri_flg |= RI_CLEAR;
+
+	imx51_ipuv3_setup_rasops(sc, ri, descr, sc->geometry);
+
+	ri->ri_caps = WSSCREEN_WSCOLORS;
+
+	rasops_reconfig(ri,
+	    ri->ri_height / ri->ri_font->fontheight,
+	    ri->ri_width / ri->ri_font->fontwidth);
+
+	ri->ri_hw = scr;
+}
+
+/*
+ * Common driver attachment code.
+ */
+void
+imx51_ipuv3_attach_sub(struct imx51_ipuv3_softc *sc,
+    struct axi_attach_args *axia, const struct lcd_panel_geometry *geom)
+{
+	DPRINTFN(5, ("%s : %d\n", __func__, __LINE__));
+
+	bus_space_tag_t iot = axia->aa_iot;
+	bus_space_handle_t ioh;
+	int error;
+
+	aprint_normal(": i.MX51 IPUV3 controller\n");
+
+	sc->n_screens = 0;
+	LIST_INIT(&sc->screens);
+
+	sc->iot = iot;
+	sc->dma_tag = &imx_bus_dma_tag;
+
+	/* map controller registers */
+	error = bus_space_map(iot, IPU_CM_BASE, IPU_CM_SIZE, 0, &ioh);
+	if (error)
+		goto fail_retarn_cm;
+	sc->cm_ioh = ioh;
+
+	/* map Display Multi FIFO Controller registers */
+	error = bus_space_map(iot, IPU_DMFC_BASE, IPU_DMFC_SIZE, 0, &ioh);
+	if (error)
+		goto fail_retarn_dmfc;
+	sc->dmfc_ioh = ioh;
+
+	/* map Display Interface registers */
+	error = bus_space_map(iot, IPU_DI0_BASE, IPU_DI0_SIZE, 0, &ioh);
+	if (error)
+		goto fail_retarn_di0;
+	sc->di0_ioh = ioh;
+
+	/* map Display Processor registers */
+	error = bus_space_map(iot, IPU_DP_BASE, IPU_DP_SIZE, 0, &ioh);
+	if (error)
+		goto fail_retarn_dp;
+	sc->dp_ioh = ioh;
+
+	/* map Display Controller registers */
+	error = bus_space_map(iot, IPU_DC_BASE, IPU_DC_SIZE, 0, &ioh);
+	if (error)
+		goto fail_retarn_dc;
+	sc->dc_ioh = ioh;
+
+	/* map Image DMA Controller registers */
+	error = bus_space_map(iot, IPU_IDMAC_BASE, IPU_IDMAC_SIZE, 0, &ioh);
+	if (error)
+		goto fail_retarn_idmac;
+	sc->idmac_ioh = ioh;
+
+	/* map CPMEM registers */
+	error = bus_space_map(iot, IPU_CPMEM_BASE, IPU_CPMEM_SIZE, 0, &ioh);
+	if (error)
+		goto fail_retarn_cpmem;
+	sc->cpmem_ioh = ioh;
+
+	/* map DCTEMPL registers */
+	error = bus_space_map(iot, IPU_DCTMPL_BASE, IPU_DCTMPL_SIZE, 0, &ioh);
+	if (error)
+		goto fail_retarn_dctmpl;
+	sc->dctmpl_ioh = ioh;
+
+#ifdef notyet
+	sc->ih = imx51_ipuv3_intr_establish(IMX51_INT_IPUV3, IPL_BIO,
+	    ipuv3intr, sc);
+	if (sc->ih == NULL) {
+		aprint_error_dev(sc->dev,
+		    "unable to establish interrupt at irq %d\n",
+		    IMX51_INT_IPUV3);
+		return;
+	}
+#endif
+
+	imx51_ipuv3_initialize(sc, geom);
+
+#if NWSDISPLAY > 0
+	struct imx51_wsscreen_descr *descr = &imx51_ipuv3_stdscreen;
+	struct imx51_ipuv3_screen *scr;
+
+	sc->mode = WSDISPLAYIO_MODE_EMUL;
+	error = imx51_ipuv3_new_screen(sc, descr->depth, &scr);
+	if (error) {
+		aprint_error_dev(sc->dev,
+		    "unable to create new screen (errno=%d)", error);
+		return;
+	}
+	sc->active = scr;
+
+	vcons_init(&sc->vd, sc, &imx51_ipuv3_stdscreen.c,
+	    &imx51_ipuv3_accessops);
+	sc->vd.init_screen = imx51_ipuv3_init_screen;
+
+#ifdef IPUV3_DEBUG
+	printf("%s: IPUV3 console ? %d\n", __func__, imx51_ipuv3_console.is_console);
+#endif
+
+	struct rasops_info *ri;
+	long defattr;
+	ri = &sc->console.scr_ri;
+
+	if (imx51_ipuv3_console.is_console) {
+		vcons_init_screen(&sc->vd, &sc->console, 1,
+		    &defattr);
+		sc->console.scr_flags |= VCONS_SCREEN_IS_STATIC;
+
+		imx51_ipuv3_stdscreen.c.nrows = ri->ri_rows;
+		imx51_ipuv3_stdscreen.c.ncols = ri->ri_cols;
+		imx51_ipuv3_stdscreen.c.textops = &ri->ri_ops;
+		imx51_ipuv3_stdscreen.c.capabilities = ri->ri_caps;
+
+		wsdisplay_cnattach(&descr->c, ri, 0, 0, defattr);
+		vcons_replay_msgbuf(&sc->console);
+
+		imx51_ipuv3_start_dma(sc, scr);
+
+		aprint_normal_dev(sc->dev, "console\n");
+	} else {
+		/*
+		 * since we're not the console we can postpone the rest
+		 * until someone actually allocates a screen for us
+		 */
+		(*ri->ri_ops.allocattr)(ri, 0, 0, 0, &defattr);
+	}
+
+	struct wsemuldisplaydev_attach_args aa;
+	aa.console = imx51_ipuv3_console.is_console;
+	aa.scrdata = &imx51_ipuv3_screen_list;
+	aa.accessops = &imx51_ipuv3_accessops;
+	aa.accesscookie = &sc->vd;
+
+	config_found(sc->dev, &aa, wsemuldisplaydevprint);
+#endif
+
+	return;
+
+fail_retarn_dctmpl:
+	bus_space_unmap(sc->iot, sc->cpmem_ioh, IPU_CPMEM_SIZE);
+fail_retarn_cpmem:
+	bus_space_unmap(sc->iot, sc->idmac_ioh, IPU_IDMAC_SIZE);
+fail_retarn_idmac:
+	bus_space_unmap(sc->iot, sc->dc_ioh, IPU_DC_SIZE);
+fail_retarn_dp:
+	bus_space_unmap(sc->iot, sc->dp_ioh, IPU_DP_SIZE);
+fail_retarn_dc:
+	bus_space_unmap(sc->iot, sc->di0_ioh, IPU_DI0_SIZE);
+fail_retarn_di0:
+	bus_space_unmap(sc->iot, sc->dmfc_ioh, IPU_DMFC_SIZE);
+fail_retarn_dmfc:
+	bus_space_unmap(sc->iot, sc->dc_ioh, IPU_CM_SIZE);
+fail_retarn_cm:
+	aprint_error_dev(sc->dev,
+	    "failed to map registers (errno=%d)\n", error);
+	return;
+}
+
+int
+imx51_ipuv3_cnattach(const struct lcd_panel_geometry *geom)
+{
+	DPRINTFN(5, ("%s : %d\n", __func__, __LINE__));
+	imx51_ipuv3_console.is_console = 1;
+	return 0;
+}
+
+#ifdef notyet
+/*
+ * Interrupt handler.
+ */
+int
+ipuv3intr(void *arg)
+{
+	DPRINTFN(5, ("%s : %d\n", __func__, __LINE__));
+
+	struct imx51_ipuv3_softc *sc = (struct imx51_ipuv3_softc *)arg;
+	bus_space_tag_t iot = sc->iot;
+	bus_space_handle_t ioh = sc->dc_ioh;
+	uint32_t status;
+
+	status = IPUV3_READ(ioh, V3CR);
+	/* Clear stickey status bits */
+	IPUV3_WRITE(ioh, V3CR, status);
+
+	return 1;
+}
+#endif
+
+static void
+imx51_ipuv3_write_dmaparam(struct imx51_ipuv3_softc *sc,
+    int ch, uint32_t *value, int size)
+{
+	DPRINTFN(5, ("%s : %d\n", __func__, __LINE__));
+
+	int i;
+	uint32_t addr = ch * 0x40;
+
+	for (i = 0; i < size; i++) {
+		IPUV3_WRITE(sc, cpmem, addr + ((i % 5) * 0x4) +
+		    ((i / 5) * 0x20), value[i]);
+#ifdef IPUV3_DEBUG
+		printf("%s: addr = 0x%08X, val = 0x%08X\n", __func__,
+		    addr + ((i % 5) * 0x4) + ((i / 5) * 0x20),
+		    IPUV3_READ(sc, cpmem, addr + ((i % 5) * 0x4) +
+			((i / 5) * 0x20)));
+#endif
+	}
+}
+
+static void
+imx51_ipuv3_build_param(struct imx51_ipuv3_softc *sc,
+    struct imx51_ipuv3_screen *scr,
+    uint32_t *params)
+{
+	const struct lcd_panel_geometry *geom = sc->geometry;
+
+	DPRINTFN(5, ("%s : %d\n", __func__, __LINE__));
+
+	imx51_ipuv3_set_idma_param(params, IDMAC_Ch_PARAM_FW,
+	    (geom->panel_width - 1));
+	imx51_ipuv3_set_idma_param(params, IDMAC_Ch_PARAM_FH,
+	    (geom->panel_height - 1));
+	imx51_ipuv3_set_idma_param(params, IDMAC_Ch_PARAM_EBA0,
+	    scr->segs[0].ds_addr >> 3);
+	imx51_ipuv3_set_idma_param(params, IDMAC_Ch_PARAM_EBA1,
+	    scr->segs[0].ds_addr >> 3);
+	imx51_ipuv3_set_idma_param(params, IDMAC_Ch_PARAM_SL,
+	    (scr->stride - 1));
+
+	imx51_ipuv3_set_idma_param(params, IDMAC_Ch_PARAM_PFS, 0x7);
+	imx51_ipuv3_set_idma_param(params, IDMAC_Ch_PARAM_NPB, 32 - 1);
+
+	switch (scr->depth) {
+	case 32:
+		/* ARBG888 */
+		imx51_ipuv3_set_idma_param(params, IDMAC_Ch_PARAM_BPP, 0x0);
+
+		imx51_ipuv3_set_idma_param(params, IDMAC_Ch_PARAM_OFS0, 0);
+		imx51_ipuv3_set_idma_param(params, IDMAC_Ch_PARAM_OFS1, 8);
+		imx51_ipuv3_set_idma_param(params, IDMAC_Ch_PARAM_OFS2, 16);
+		imx51_ipuv3_set_idma_param(params, IDMAC_Ch_PARAM_OFS3, 24);
+
+		imx51_ipuv3_set_idma_param(params, IDMAC_Ch_PARAM_WID0, 8 - 1);
+		imx51_ipuv3_set_idma_param(params, IDMAC_Ch_PARAM_WID1, 8 - 1);
+		imx51_ipuv3_set_idma_param(params, IDMAC_Ch_PARAM_WID2, 8 - 1);
+		imx51_ipuv3_set_idma_param(params, IDMAC_Ch_PARAM_WID3, 8 - 1);
+		break;
+	case 24:
+		/* RBG888 */
+		imx51_ipuv3_set_idma_param(params, IDMAC_Ch_PARAM_BPP, 0x1);
+
+		imx51_ipuv3_set_idma_param(params, IDMAC_Ch_PARAM_OFS0, 0);
+		imx51_ipuv3_set_idma_param(params, IDMAC_Ch_PARAM_OFS1, 8);
+		imx51_ipuv3_set_idma_param(params, IDMAC_Ch_PARAM_OFS2, 16);
+		imx51_ipuv3_set_idma_param(params, IDMAC_Ch_PARAM_OFS3, 24);
+
+		imx51_ipuv3_set_idma_param(params, IDMAC_Ch_PARAM_WID0, 8 - 1);
+		imx51_ipuv3_set_idma_param(params, IDMAC_Ch_PARAM_WID1, 8 - 1);
+		imx51_ipuv3_set_idma_param(params, IDMAC_Ch_PARAM_WID2, 8 - 1);
+		imx51_ipuv3_set_idma_param(params, IDMAC_Ch_PARAM_WID3, 0);
+		break;
+	case 16:
+		/* RBG565 */
+		imx51_ipuv3_set_idma_param(params, IDMAC_Ch_PARAM_BPP, 0x3);
+
+		imx51_ipuv3_set_idma_param(params, IDMAC_Ch_PARAM_OFS0, 0);
+		imx51_ipuv3_set_idma_param(params, IDMAC_Ch_PARAM_OFS1, 5);
+		imx51_ipuv3_set_idma_param(params, IDMAC_Ch_PARAM_OFS2, 11);
+		imx51_ipuv3_set_idma_param(params, IDMAC_Ch_PARAM_OFS3, 16);
+
+		imx51_ipuv3_set_idma_param(params, IDMAC_Ch_PARAM_WID0, 5 - 1);
+		imx51_ipuv3_set_idma_param(params, IDMAC_Ch_PARAM_WID1, 6 - 1);
+		imx51_ipuv3_set_idma_param(params, IDMAC_Ch_PARAM_WID2, 5 - 1);
+		imx51_ipuv3_set_idma_param(params, IDMAC_Ch_PARAM_WID3, 0);
+		break;
+	default:
+		panic("%s: unsupported depth %d\n", __func__, scr->depth);
+		break;
+	}
+
+	imx51_ipuv3_set_idma_param(params, IDMAC_Ch_PARAM_ID, 1);
+}
+
+static void
+imx51_ipuv3_set_idma_param(uint32_t *params, uint32_t name, uint32_t val)
+{
+	int word = (name >> 16) & 0xff;
+	int shift = (name >> 8) & 0xff;
+	int width = name & 0xff;
+	int index;
+
+	DPRINTFN(5, ("%s : %d\n", __func__, __LINE__));
+
+	index = word * 5;
+	index += shift / 32;
+	shift = shift % 32;
+
+	params[index] |= val << shift;
+	shift = 32 - shift;
+
+	if (width > shift)
+		params[index+1] |= val >> shift;
+}
+
+/*
+ * Enable DMA to cause the display to be refreshed periodically.
+ * This brings the screen to life...
+ */
+void
+imx51_ipuv3_start_dma(struct imx51_ipuv3_softc *sc,
+    struct imx51_ipuv3_screen *scr)
+{
+	int save;
+	uint32_t params[10];
+	uint32_t reg;
+
+	DPRINTFN(3, ("%s: Pixel depth = %d\n", __func__, scr->depth));
+
+	reg = IPUV3_READ(sc, idmac, IPU_IDMAC_CH_EN_1);
+	reg &= ~__BIT(CH_PANNEL_BG);
+	IPUV3_WRITE(sc, idmac, IPU_IDMAC_CH_EN_1, reg);
+
+	memset(params, 0, sizeof(params));
+	imx51_ipuv3_build_param(sc, scr, params);
+
+	save = disable_interrupts(I32_bit);
+
+	/* IDMAC configuration */
+	imx51_ipuv3_write_dmaparam(sc, CH_PANNEL_BG, params,
+	    sizeof(params) / sizeof(params[0]));
+
+	IPUV3_WRITE(sc, idmac, IPU_IDMAC_CH_PRI_1, __BIT(CH_PANNEL_BG));
+
+	/* double buffer */
+	reg = IPUV3_READ(sc, cm, IPU_CM_CH_DB_MODE_SEL_0);
+	reg |= __BIT(CH_PANNEL_BG);
+	IPUV3_WRITE(sc, cm, IPU_CM_CH_DB_MODE_SEL_0, reg);
+
+	reg = IPUV3_READ(sc, idmac, IPU_IDMAC_CH_EN_1);
+	reg |= __BIT(CH_PANNEL_BG);
+	IPUV3_WRITE(sc, idmac, IPU_IDMAC_CH_EN_1, reg);
+
+	reg = IPUV3_READ(sc, cm, IPU_CM_GPR);
+	reg &= ~CM_GPR_IPU_CH_BUF0_RDY0_CLR;
+	IPUV3_WRITE(sc, cm, IPU_CM_GPR, reg);
+
+	IPUV3_WRITE(sc, cm, IPU_CM_CUR_BUF_0, __BIT(CH_PANNEL_BG));
+
+	restore_interrupts(save);
+
+	imx51_ipuv3_enable_display(sc);
+
+#ifdef IPUV3_DEBUG
+	imx51_ipuv3_dump(sc);
+#endif
+}
+
+/*
+ * Disable screen refresh.
+ */
+static void
+imx51_ipuv3_stop_dma(struct imx51_ipuv3_softc *sc)
+{
+	DPRINTFN(5, ("%s : %d\n", __func__, __LINE__));
+
+	return;
+}
+
+/*
+ * Create and initialize a new screen buffer.
+ */
+int
+imx51_ipuv3_new_screen(struct imx51_ipuv3_softc *sc, int depth,
+    struct imx51_ipuv3_screen **scrpp)
+{
+	const struct lcd_panel_geometry *geometry;
+	struct imx51_ipuv3_screen *scr = NULL;
+	int width, height;
+	bus_size_t size;
+	int error;
+	int busdma_flag = (cold ? BUS_DMA_NOWAIT : BUS_DMA_WAITOK);
+
+	DPRINTFN(5, ("%s : %d\n", __func__, __LINE__));
+
+	geometry = sc->geometry;
+
+	width = geometry->panel_width;
+	height = geometry->panel_height;
+
+	scr = malloc(sizeof(*scr), M_DEVBUF, M_NOWAIT);
+	if (scr == NULL)
+		return ENOMEM;
+
+	memset(scr, 0, sizeof(*scr));
+
+	scr->nsegs = 0;
+	scr->depth = depth;
+	scr->stride = width * depth / 8;
+	scr->buf_size = size = scr->stride * height;
+	scr->buf_va = NULL;
+
+	error = bus_dmamem_alloc(sc->dma_tag, size, 16, 0, scr->segs, 1,
+	    &scr->nsegs, busdma_flag);
+
+	if (error || scr->nsegs != 1) {
+		/* XXX:
+		 * Actually we can handle nsegs>1 case by means
+		 * of multiple DMA descriptors for a panel.  It
+		 * will make code here a bit hairly.
+		 */
+		if (error == 0)
+			error = E2BIG;
+		goto bad;
+	}
+
+	error = bus_dmamem_map(sc->dma_tag, scr->segs, scr->nsegs, size,
+	    (void **)&scr->buf_va, busdma_flag | BUS_DMA_COHERENT);
+	if (error)
+		goto bad;
+
+	memset(scr->buf_va, 0, scr->buf_size);
+
+	/* map memory for DMA */
+	error = bus_dmamap_create(sc->dma_tag, 1024*1024*2, 1, 1024*1024*2, 0,
+	    busdma_flag, &scr->dma);
+	if (error)
+		goto bad;
+
+	error = bus_dmamap_load(sc->dma_tag, scr->dma, scr->buf_va, size,
+	    NULL, busdma_flag);
+	if (error)
+		goto bad;
+
+	LIST_INSERT_HEAD(&sc->screens, scr, link);
+	sc->n_screens++;
+
+#ifdef IPUV3_DEBUG
+	printf("%s: screen buffer width  %d\n", __func__, width);
+	printf("%s: screen buffer height %d\n", __func__, height);
+	printf("%s: screen buffer depth  %d\n", __func__, depth);
+	printf("%s: screen buffer stride %d\n", __func__, scr->stride);
+	printf("%s: screen buffer size   0x%08X\n", __func__,
+	    (uint32_t)scr->buf_size);
+	printf("%s: screen buffer addr virtual  %p\n", __func__, scr->buf_va);
+	printf("%s: screen buffer addr physical %p\n", __func__,
+	    (void *)scr->segs[0].ds_addr);
+#endif
+
+	scr->map_size = size;		/* used when unmap this. */
+
+	*scrpp = scr;
+
+	return 0;
+
+bad:
+#ifdef IPUV3_DEBUG
+	printf("%s: error = 0x%08X\n", __func__, error);
+#endif
+	if (scr) {
+		if (scr->buf_va)
+			bus_dmamem_unmap(sc->dma_tag, scr->buf_va, size);
+		if (scr->nsegs)
+			bus_dmamem_free(sc->dma_tag, scr->segs, scr->nsegs);
+		free(scr, M_DEVBUF);
+	}
+	*scrpp = NULL;
+	return error;
+}
+
+#if NWSDISPLAY > 0
+/*
+ * Initialize rasops for a screen, as well as struct wsscreen_descr if this
+ * is the first screen creation.
+ */
+static void
+imx51_ipuv3_setup_rasops(struct imx51_ipuv3_softc *sc, struct rasops_info *rinfo,
+    struct imx51_wsscreen_descr *descr,
+    const struct lcd_panel_geometry *geom)
+{
+
+	DPRINTFN(5, ("%s : %d\n", __func__, __LINE__));
+
+	rinfo->ri_flg = descr->flags;
+	rinfo->ri_depth = descr->depth;
+	rinfo->ri_width = geom->panel_width;
+	rinfo->ri_height = geom->panel_height;
+	rinfo->ri_stride = rinfo->ri_width * rinfo->ri_depth / 8;
+
+	/* swap B and R */
+	if (descr->depth == 16) {
+		rinfo->ri_rnum = 5;
+		rinfo->ri_rpos = 11;
+		rinfo->ri_gnum = 6;
+		rinfo->ri_gpos = 5;
+		rinfo->ri_bnum = 5;
+		rinfo->ri_bpos = 0;
+	}
+
+	if (descr->c.nrows == 0) {
+		/* get rasops to compute screen size the first time */
+		rasops_init(rinfo, 100, 100);
+	} else {
+		rasops_init(rinfo, descr->c.nrows, descr->c.ncols);
+	}
+
+	descr->c.nrows = rinfo->ri_rows;
+	descr->c.ncols = rinfo->ri_cols;
+	descr->c.capabilities = rinfo->ri_caps;
+	descr->c.textops = &rinfo->ri_ops;
+}
+#endif
+/*
+ * Power management
+ */
+void
+imx51_ipuv3_suspend(struct imx51_ipuv3_softc *sc)
+{
+	DPRINTFN(5, ("%s : %d\n", __func__, __LINE__));
+
+	if (sc->active) {
+		imx51_ipuv3_stop_dma(sc);
+	}
+}
+
+void
+imx51_ipuv3_resume(struct imx51_ipuv3_softc *sc)
+{
+	DPRINTFN(5, ("%s : %d\n", __func__, __LINE__));
+
+	if (sc->active) {
+		imx51_ipuv3_initialize(sc, sc->geometry);
+		imx51_ipuv3_start_dma(sc, sc->active);
+	}
+}
+
+void
+imx51_ipuv3_power(int why, void *v)
+{
+	DPRINTFN(5, ("%s : %d\n", __func__, __LINE__));
+
+	struct imx51_ipuv3_softc *sc = v;
+
+	switch (why) {
+	case PWR_SUSPEND:
+	case PWR_STANDBY:
+		imx51_ipuv3_suspend(sc);
+		break;
+
+	case PWR_RESUME:
+		imx51_ipuv3_resume(sc);
+		break;
+	}
+}
+
+#if NWSDISPLAY > 0
+int
+imx51_ipuv3_ioctl(void *v, void *vs, u_long cmd, void *data, int flag,
+    struct lwp *l)
+{
+	DPRINTFN(5, ("%s : %d\n", __func__, __LINE__));
+
+	struct vcons_data *vd = v;
+	struct imx51_ipuv3_softc *sc = vd->cookie;
+	struct wsdisplay_fbinfo *wsdisp_info;
+	struct vcons_screen *ms = vd->active;
+
+	switch (cmd) {
+	case WSDISPLAYIO_GTYPE:
+		*(int *)data = WSDISPLAY_TYPE_IMXIPU;
+		return 0;
+
+	case WSDISPLAYIO_GINFO:
+		wsdisp_info = (struct wsdisplay_fbinfo *)data;
+		wsdisp_info->height = ms->scr_ri.ri_height;
+		wsdisp_info->width = ms->scr_ri.ri_width;
+		wsdisp_info->depth = ms->scr_ri.ri_depth;
+		wsdisp_info->cmsize = 0;
+		return 0;
+
+	case WSDISPLAYIO_LINEBYTES:
+		*(u_int *)data = ms->scr_ri.ri_stride;
+		return 0;
+
+	case WSDISPLAYIO_GETCMAP:
+	case WSDISPLAYIO_PUTCMAP:
+		return EPASSTHROUGH;	/* XXX Colormap */
+
+	case WSDISPLAYIO_SVIDEO:
+		if (*(int *)data == WSDISPLAYIO_VIDEO_ON) {
+			/* turn it on */
+		}
+		else {
+			/* start IPUV3 shutdown */
+			/* sleep until interrupt */
+		}
+		return 0;
+
+	case WSDISPLAYIO_GVIDEO:
+		*(u_int *)data =  WSDISPLAYIO_VIDEO_ON;
+		return 0;
+
+	case WSDISPLAYIO_GCURPOS:
+	case WSDISPLAYIO_SCURPOS:
+	case WSDISPLAYIO_GCURMAX:
+	case WSDISPLAYIO_GCURSOR:
+	case WSDISPLAYIO_SCURSOR:
+		return EPASSTHROUGH;	/* XXX */
+	case WSDISPLAYIO_SMODE:
+		{
+			int new_mode = *(int*)data;
+
+			/* notify the bus backend */
+			if (new_mode != sc->mode) {
+				sc->mode = new_mode;
+				if(new_mode == WSDISPLAYIO_MODE_EMUL)
+					vcons_redraw_screen(ms);
+			}
+		}
+		return 0;
+	}
+
+	return EPASSTHROUGH;
+}
+
+paddr_t
+imx51_ipuv3_mmap(void *v, void *vs, off_t offset, int prot)
+{
+	DPRINTFN(5, ("%s : %d\n", __func__, __LINE__));
+
+	struct vcons_data *vd = v;
+	struct imx51_ipuv3_softc *sc = vd->cookie;
+	struct imx51_ipuv3_screen *scr = sc->active;
+
+	return bus_dmamem_mmap(sc->dma_tag, scr->segs, scr->nsegs,
+	    offset, prot,
+	    BUS_DMA_WAITOK | BUS_DMA_COHERENT);
+}
+#endif /* NWSDISPLAY > 0 */
+
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/sys/arch/arm/imx/imx51_ipuv3reg.h	Sun Apr 29 23:04:36 2012 +0000
@@ -0,0 +1,841 @@
+/*	$NetBSD: imx51_ipuv3reg.h,v 1.1.2.2 2012/04/29 23:04:38 mrg Exp $	*/
+/*
+ * Copyright (c) 2011, 2012  Genetec Corporation.  All rights reserved.
+ * Written by Hashimoto Kenichi for Genetec Corporation.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY GENETEC CORPORATION ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL GENETEC CORPORATION
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef _ARM_IMX_IMX51_IPUV3REG_H
+#define _ARM_IMX_IMX51_IPUV3REG_H
+
+/* register offset address */
+
+/*
+ * CM
+ * Control Module
+ */
+#define IPU_CM_CONF			0x00000000
+#define  CM_CONF_CSI_SEL		__BIT(31)
+#define  CM_CONF_IC_INPUT		__BIT(30)
+#define  CM_CONF_CSI1_DATA_SOURCE	__BIT(29)
+#define  CM_CONF_CSI0_DATA_SOURCE	__BIT(28)
+#define  CM_CONF_VDI_DMFC_SYNC		__BIT(27)
+#define  CM_CONF_IC_DMFC_SYNC		__BIT(26)
+#define  CM_CONF_IC_DMFC_SEL		__BIT(25)
+#define  CM_CONF_ISP_DOUBLE_FLOW	__BIT(24)
+#define  CM_CONF_IDMAC_DISABLE		__BIT(22)
+#define  CM_CONF_IPU_DIAGBUS_ON		__BIT(21)
+#define  CM_CONF_IPU_DIAGBUS_MODE	__BITS(20, 16)
+#define  CM_CONF_VDI_EN			__BIT(12)
+#define  CM_CONF_SISG_EN		__BIT(11)
+#define  CM_CONF_DMFC_EN		__BIT(10)
+#define  CM_CONF_DC_EN			__BIT(9)
+#define  CM_CONF_SMFC_EN		__BIT(8)
+#define  CM_CONF_DI1_EN			__BIT(7)
+#define  CM_CONF_DI0_EN			__BIT(6)
+#define  CM_CONF_DP_EN			__BIT(5)
+#define  CM_CONF_ISP_EN			__BIT(4)
+#define  CM_CONF_IRT_EN			__BIT(3)
+#define  CM_CONF_IC_EN			__BIT(2)
+#define  CM_CONF_CSI1_EN		__BIT(1)
+#define  CM_CONF_CSI0_EN		__BIT(0)
+#define IPU_SISG_CTRL0			0x00000004
+#define IPU_SISG_CTRL1			0x00000008
+#define IPU_CM_INT_CTRL_1		0x0000003c
+#define IPU_CM_INT_CTRL_2		0x00000040
+#define IPU_CM_INT_CTRL_3		0x00000044
+#define IPU_CM_INT_CTRL_4		0x00000048
+#define IPU_CM_INT_CTRL_5		0x0000004c
+#define IPU_CM_INT_CTRL_6		0x00000050
+#define IPU_CM_INT_CTRL_7		0x00000054
+#define IPU_CM_INT_CTRL_8		0x00000058
+#define IPU_CM_INT_CTRL_9		0x0000005c
+#define IPU_CM_INT_CTRL_10		0x00000060
+#define IPU_CM_INT_CTRL_11		0x00000064
+#define IPU_CM_INT_CTRL_12		0x00000068
+#define IPU_CM_INT_CTRL_13		0x0000006c
+#define IPU_CM_INT_CTRL_14		0x00000070
+#define IPU_CM_INT_CTRL_15		0x00000074
+#define IPU_CM_SDMA_EVENT_1		0x00000078
+#define IPU_CM_SDMA_EVENT_2		0x0000007c
+#define IPU_CM_SDMA_EVENT_3		0x00000080
+#define IPU_CM_SDMA_EVENT_4		0x00000084
+#define IPU_CM_SDMA_EVENT_7		0x00000088
+#define IPU_CM_SDMA_EVENT_8		0x0000008c
+#define IPU_CM_SDMA_EVENT_11		0x00000090
+#define IPU_CM_SDMA_EVENT_12		0x00000094
+#define IPU_CM_SDMA_EVENT_13		0x00000098
+#define IPU_CM_SDMA_EVENT_14		0x0000009c
+#define IPU_CM_SRM_PRI1			0x000000a0
+#define IPU_CM_SRM_PRI2			0x000000a4
+#define IPU_CM_FS_PROC_FLOW1		0x000000a8
+#define IPU_CM_FS_PROC_FLOW2		0x000000ac
+#define IPU_CM_FS_PROC_FLOW3		0x000000b0
+#define IPU_CM_FS_DISP_FLOW1		0x000000b4
+#define IPU_CM_FS_DISP_FLOW2		0x000000b8
+#define IPU_CM_SKIP			0x000000bc
+#define IPU_CM_DISP_ALT_CONF		0x000000c0
+#define IPU_CM_DISP_GEN			0x000000c4
+#define  CM_DISP_GEN_DI0_COUNTER_RELEASE	__BIT(24)
+#define  CM_DISP_GEN_DI1_COUNTER_RELEASE	__BIT(23)
+#define  CM_DISP_GEN_MCU_MAX_BURST_STOP		__BIT(22)
+#define  CM_DISP_GEN_MCU_T_SHIFT		18
+#define  CM_DISP_GEN_MCU_T(n)		((n) << CM_DISP_GEN_MCU_T_SHIFT)
+#define IPU_CM_DISP_ALT1		0x000000c8
+#define IPU_CM_DISP_ALT2		0x000000cc
+#define IPU_CM_DISP_ALT3		0x000000d0
+#define IPU_CM_DISP_ALT4		0x000000d4
+#define IPU_CM_SNOOP			0x000000d8
+#define IPU_CM_MEM_RST			0x000000dc
+#define  CM_MEM_START			__BIT(31)
+#define  CM_MEM_EN			__BITS(22, 0)
+#define IPU_CM_PM			0x000000e0
+#define IPU_CM_GPR			0x000000e4
+#define  CM_GPR_IPU_CH_BUF1_RDY1_CLR		__BIT(31)
+#define  CM_GPR_IPU_CH_BUF1_RDY0_CLR		__BIT(30)
+#define  CM_GPR_IPU_CH_BUF0_RDY1_CLR		__BIT(29)
+#define  CM_GPR_IPU_CH_BUF0_RDY0_CLR		__BIT(28)
+#define  CM_GPR_IPU_ALT_CH_BUF1_RDY1_CLR	__BIT(27)
+#define  CM_GPR_IPU_ALT_CH_BUF1_RDY0_CLR	__BIT(26)
+#define  CM_GPR_IPU_ALT_CH_BUF0_RDY1_CLR	__BIT(25)
+#define  CM_GPR_IPU_ALT_CH_BUF0_RDY0_CLR	__BIT(24)
+#define  CM_GPR_IPU_DI1_CLK_CHANGE_ACK_DIS	__BIT(23)
+#define  CM_GPR_IPU_DI0_CLK_CHANGE_ACK_DIS	__BIT(22)
+#define  CM_GPR_IPU_CH_BUF2_RDY1_CLR		__BIT(21)
+#define  CM_GPR_IPU_CH_BUF2_RDY0_CLR		__BIT(20)
+#define  CM_GPR_IPU_GP(n)			__BIT((n))
+#define IPU_CM_CH_DB_MODE_SEL_0		0x00000150
+#define IPU_CM_CH_DB_MODE_SEL_1		0x00000154
+#define IPU_CM_ALT_CH_DB_MODE_SEL_0	0x00000168
+#define IPU_CM_ALT_CH_DB_MODE_SEL_1	0x0000016c
+#define IPU_CM_CH_TRB_MODE_SEL_0	0x00000178
+#define IPU_CM_CH_TRB_MODE_SEL_1	0x0000017c
+#define IPU_CM_INT_STAT_1		0x00000200
+#define IPU_CM_INT_STAT_2		0x00000204
+#define IPU_CM_INT_STAT_3		0x00000208
+#define IPU_CM_INT_STAT_4		0x0000020c
+#define IPU_CM_INT_STAT_5		0x00000210
+#define IPU_CM_INT_STAT_6		0x00000214
+#define IPU_CM_INT_STAT_7		0x00000218
+#define IPU_CM_INT_STAT_8		0x0000021c
+#define IPU_CM_INT_STAT_9		0x00000220
+#define IPU_CM_INT_STAT_10		0x00000224
+#define IPU_CM_INT_STAT_11		0x00000228
+#define IPU_CM_INT_STAT_12		0x0000022c
+#define IPU_CM_INT_STAT_13		0x00000230
+#define IPU_CM_INT_STAT_14		0x00000234
+#define IPU_CM_INT_STAT_15		0x00000238
+#define IPU_CM_CUR_BUF_0		0x0000023c
+#define IPU_CM_CUR_BUF_1		0x00000240
+#define IPU_CM_ALT_CUR_BUF_0		0x00000244
+#define IPU_CM_ALT_CUR_BUF_1		0x00000248
+#define IPU_CM_SRM_STAT			0x0000024c
+#define IPU_CM_PROC_TASKS_STAT		0x00000250
+#define IPU_CM_DISP_TASKS_STAT		0x00000254
+#define IPU_CM_TRIPLE_CUR_BUF_0		0x00000258
+#define IPU_CM_TRIPLE_CUR_BUF_1		0x0000025c
+#define IPU_CM_TRIPLE_CUR_BUF_2		0x00000260
+#define IPU_CM_TRIPLE_CUR_BUF_3		0x00000264
+#define IPU_CM_CH_BUF0_RDY0		0x00000268
+#define IPU_CM_CH_BUF0_RDY1		0x0000026c
+#define IPU_CM_CH_BUF1_RDY0		0x00000270
+#define IPU_CM_CH_BUF1_RDY1		0x00000274
+#define IPU_CM_ALT_CH_BUF0_RDY0		0x00000278
+#define IPU_CM_ALT_CH_BUF0_RDY1		0x0000027c
+#define IPU_CM_ALT_CH_BUF1_RDY0		0x00000280
+#define IPU_CM_ALT_CH_BUF1_RDY1		0x00000284
+#define IPU_CM_CH_BUF2_RDY0		0x00000288
+#define IPU_CM_CH_BUF2_RDY1		0x0000028c
+
+/*
+ * IDMAC
+ * Image DMA Controller
+ */
+#define IPU_IDMAC_CONF		0x00000000
+#define IPU_IDMAC_CH_EN_1	0x00000004
+#define IPU_IDMAC_CH_EN_2	0x00000008
+#define IPU_IDMAC_SEP_ALPHA	0x0000000c
+#define IPU_IDMAC_ALT_SEP_ALPHA	0x00000010
+#define IPU_IDMAC_CH_PRI_1	0x00000014
+#define IPU_IDMAC_CH_PRI_2	0x00000018
+#define IPU_IDMAC_WM_EN_1	0x0000001c
+#define IPU_IDMAC_WM_EN_2	0x00000020
+#define IPU_IDMAC_LOCK_EN_1	0x00000024
+#define IPU_IDMAC_LOCK_EN_2	0x00000028
+#define IPU_IDMAC_SUB_ADDR_0	0x0000002c
+#define IPU_IDMAC_SUB_ADDR_1	0x00000030
+#define IPU_IDMAC_SUB_ADDR_2	0x00000034
+#define IPU_IDMAC_SUB_ADDR_3	0x00000038
+#define IPU_IDMAC_SUB_ADDR_4	0x0000003c
+#define IPU_IDMAC_BNDM_EN_1	0x00000040
+#define IPU_IDMAC_BNDM_EN_2	0x00000044
+#define IPU_IDMAC_SC_CORD	0x00000048
+#define IPU_IDMAC_SC_CORD1	0x0000004c
+#define IPU_IDMAC_CH_BUSY_1	0x00000100
+#define IPU_IDMAC_CH_BUSY_2	0x00000104
+
+#define CH_PANNEL_BG	23
+#define CH_PANNEL_FG	27
+
+/*
+ * DP
+ * Display Port
+ */
+#define IPU_DP_DEBUG_CNT	0x000000bc
+#define IPU_DP_DEBUG_STAT	0x000000c0
+
+/*
+ * IC
+ * Image Converter
+ */
+#define IPU_IC_CONF		0x00000000
+#define IPU_IC_PRP_ENC_RSC	0x00000004
+#define IPU_IC_PRP_VF_RSC	0x00000008
+#define IPU_IC_PP_RSC		0x0000000c
+#define IPU_IC_CMBP_1		0x00000010
+#define IPU_IC_CMBP_2		0x00000014
+#define IPU_IC_IDMAC_1		0x00000018
+#define IPU_IC_IDMAC_2		0x0000001c
+#define IPU_IC_IDMAC_3		0x00000020
+#define IPU_IC_IDMAC_4		0x00000024
+
+/*
+ * CSI
+ * Camera Sensor Interface
+ */
+#define IPU_CSI0_SENS_CONF	0x00000000
+#define IPU_CSI0_SENS_FRM_SIZE	0x00000004
+#define IPU_CSI0_ACT_FRM_SIZE	0x00000008
+#define IPU_CSI0_OUT_FRM_CTRL	0x0000000c
+#define IPU_CSI0_TST_CTRL	0x00000010
+#define IPU_CSI0_CCIR_CODE_1	0x00000014
+#define IPU_CSI0_CCIR_CODE_2	0x00000018
+#define IPU_CSI0_CCIR_CODE_3	0x0000001c
+#define IPU_CSI0_DI		0x00000020
+#define IPU_CSI0_SKIP		0x00000024
+#define IPU_CSI0_CPD_CTRL	0x00000028
+#define IPU_CSI0_CPD_OFFSET1	0x000000ec
+#define IPU_CSI0_CPD_OFFSET2	0x000000f0
+
+#define IPU_CSI1_SENS_CONF	0x00000000
+#define IPU_CSI1_SENS_FRM_SIZE	0x00000004
+#define IPU_CSI1_ACT_FRM_SIZE	0x00000008
+#define IPU_CSI1_OUT_FRM_CTRL	0x0000000c
+#define IPU_CSI1_TST_CTRL	0x00000010
+#define IPU_CSI1_CCIR_CODE_1	0x00000014
+#define IPU_CSI1_CCIR_CODE_2	0x00000018
+#define IPU_CSI1_CCIR_CODE_3	0x0000001c
+#define IPU_CSI1_DI		0x00000020
+#define IPU_CSI1_SKIP		0x00000024
+#define IPU_CSI1_CPD_CTRL	0x00000028
+#define IPU_CSI1_CPD_OFFSET1	0x000000ec
+#define IPU_CSI1_CPD_OFFSET2	0x000000f0
+
+/*
+ * DI
+ * Display Interface
+ */
+#define IPU_DI_GENERAL			0x00000000
+#define  DI_GENERAL_DISP_Y_SEL		__BITS(30, 28)
+#define  DI_GENERAL_CLOCK_STOP_MODE	__BITS(27, 24)
+#define  DI_GENERAL_DISP_CLOCK_INIT	__BIT(23)
+#define  DI_GENERAL_MASK_SEL		__BIT(22)
+#define  DI_GENERAL_VSYNC_EXT		__BIT(21)
+#define  DI_GENERAL_CLK_EXT		__BIT(20)
+#define  DI_GENERAL_WATCHDOG_MODE	__BITS(19, 18)
+#define  DI_GENERAL_POLARITY_DISP_CLK	__BIT(17)
+#define  DI_GENERAL_SYNC_COUNT_SEL	__BITS(15, 12)
+#define  DI_GENERAL_ERR_TREATMENT	__BIT(11)
+#define  DI_GENERAL_ERM_VSYNC_SEL	__BIT(10)
+#define  DI_GENERAL_POLARITY_CS(n)	(1 << ((n) + 8))
+#define  DI_GENERAL_POLARITY(n)		(1 << ((n) - 1))
+
+#define IPU_DI_BS_CLKGEN0		0x00000004
+#define  DI_BS_CLKGEN0_OFFSET_SHIFT	16
+#define IPU_DI_BS_CLKGEN1		0x00000008
+#define  DI_BS_CLKGEN1_DOWN_SHIFT	16
+#define  DI_BS_CLKGEN1_UP_SHIFT		0
+#define IPU_DI_SW_GEN0(n)		(0x0000000c + ((n) - 1) * 4)
+#define  DI_SW_GEN0_RUN_VAL		__BITS(30, 19)
+#define  DI_SW_GEN0_RUN_RESOL		__BITS(18, 16)
+#define  DI_SW_GEN0_OFFSET_VAL		__BITS(14,  3)
+#define  DI_SW_GEN0_OFFSET_RESOL	__BITS( 2,  0)
+#define  __DI_SW_GEN0(run_val, run_resol, offset_val, offset_resol)	\
+	(((run_val) << 19) | ((run_resol) << 16) | 			\
+	 ((offset_val) << 3) | (offset_resol))
+#define IPU_DI_SW_GEN1(n)		(0x00000030 + ((n) - 1) * 4)
+#define  DI_SW_GEN1_CNT_POL_GEN_EN	__BITS(30, 29)
+#define  DI_SW_GEN1_CNT_AUTO_RELOAD	__BIT(28)
+#define  DI_SW_GEN1_CNT_CLR_SEL		__BITS(27, 25)
+#define  DI_SW_GEN1_CNT_DOWN		__BITS(24, 16)
+#define  DI_SW_GEN1_CNT_POL_TRIG_SEL	__BITS(14, 12)
+#define  DI_SW_GEN1_CNT_POL_CLR_SEL	__BITS(11,  9)
+#define  DI_SW_GEN1_CNT_UP		__BITS( 8,  0)
+#define  __DI_SW_GEN1(pol_gen_en, auto_reload, clr_sel, down, pol_trig_sel, pol_clr_sel, up) \
+	(((pol_gen_en) << 29) | ((auto_reload) << 28) | \
+	 ((clr_sel) << 25) |				\
+	    ((down) << 16) | ((pol_trig_sel) << 12) |	\
+	 ((pol_clr_sel) << 9) | (up))
+#define IPU_DI_SYNC_AS_GEN		0x00000054
+#define  DI_SYNC_AS_GEN_SYNC_START_EN	__BIT(28)
+#define  DI_SYNC_AS_GEN_VSYNC_SEL	__BITS(15, 13)
+#define  DI_SYNC_AS_GEN_VSYNC_SEL_SHIFT	13
+#define  DI_SYNC_AS_GEN_SYNC_STAR	__BITS(11,  0)
+#define IPU_DI_DW_GEN(n)		(0x00000058 + (n) * 4)
+#define  DI_DW_GEN_ACCESS_SIZE_SHIFT		24
+#define  DI_DW_GEN_COMPONNENT_SIZE_SHIFT	16
+#define  DI_DW_GEN_PIN_SHIFT(n)			(((n) - 11) * 2)
+#define  DI_DW_GEN_PIN(n)		__BITS(DI_DW_GEN_PIN_SHIFT(n) + 1, \
+					       DI_DW_GEN_PIN_SHIFT(n))
+#define IPU_DI_DW_SET(n, m)	(0x00000088 + (n) * 4 + (m) * 0x30)
+#define  DI_DW_SET_DOWN_SHIFT	16
+#define  DI_DW_SET_UP_SHIFT	0
+#define IPU_DI_STP_REP(n)	(0x00000148 + ((n - 1) / 2) * 4)
+#define  DI_STP_REP_SHIFT(n)	(((n - 1) % 2) * 16)
+#define  DI_STP_REP_MASK(n)	(__BITS(11, 0) << DI_STP_REP_SHIFT((n)))
+#define IPU_DI_SER_CONF			0x0000015c
+#define IPU_DI_SSC			0x00000160
+#define IPU_DI_POL			0x00000164
+#define  DI_POL_DRDY_POLARITY_17 	__BIT(6)
+#define  DI_POL_DRDY_POLARITY_16 	__BIT(5)
+#define  DI_POL_DRDY_POLARITY_15 	__BIT(4)
+#define  DI_POL_DRDY_POLARITY_14 	__BIT(3)
+#define  DI_POL_DRDY_POLARITY_13 	__BIT(2)
+#define  DI_POL_DRDY_POLARITY_12 	__BIT(1)
+#define  DI_POL_DRDY_POLARITY_11 	__BIT(0)
+#define IPU_DI_AW0			0x00000168
+#define IPU_DI_AW1			0x0000016c
+#define IPU_DI_SCR_CONF			0x00000170
+#define IPU_DI_STAT			0x00000174
+
+/*
+ * SMFC
+ * Sensor Multi FIFO Controller
+ */
+#define IPU_SMFC_MAP	0x00000000
+#define IPU_SMFC_WMC	0x00000004
+#define IPU_SMFC_BS	0x00000008
+
+/*
+ * DC
+ * Display Controller
+ */
+#define IPU_DC_READ_CH_CONF	0x00000000
+#define IPU_DC_READ_CH_ADDR	0x00000004
+
+#define IPU_DC_RL0_CH_0		0x00000008
+#define IPU_DC_RL1_CH_0		0x0000000c
+#define IPU_DC_RL2_CH_0		0x00000010
+#define IPU_DC_RL3_CH_0		0x00000014
+#define IPU_DC_RL4_CH_0		0x00000018
+#define IPU_DC_WR_CH_CONF_1	0x0000001c
+#define IPU_DC_WR_CH_ADDR_1	0x00000020
+#define IPU_DC_RL0_CH_1		0x00000024
+#define IPU_DC_RL1_CH_1		0x00000028
+#define IPU_DC_RL2_CH_1		0x0000002c
+#define IPU_DC_RL3_CH_1		0x00000030
+#define IPU_DC_RL4_CH_1		0x00000034
+#define IPU_DC_WR_CH_CONF_2	0x00000038
+#define IPU_DC_WR_CH_ADDR_2	0x0000003c
+#define IPU_DC_RL0_CH_2		0x00000040
+#define IPU_DC_RL1_CH_2		0x00000044
+#define IPU_DC_RL2_CH_2		0x00000048
+#define IPU_DC_RL3_CH_2		0x0000004c
+#define IPU_DC_RL4_CH_2		0x00000050
+#define IPU_DC_CMD_CH_CONF_3	0x00000054
+#define IPU_DC_CMD_CH_CONF_4	0x00000058
+#define IPU_DC_WR_CH_CONF_5	0x0000005c
+#define IPU_DC_WR_CH_ADDR_5	0x00000060
+#define IPU_DC_RL0_CH_5		0x00000064
+#define IPU_DC_RL1_CH_5		0x00000068
+#define IPU_DC_RL2_CH_5		0x0000006c
+#define IPU_DC_RL3_CH_5		0x00000070
+#define IPU_DC_RL4_CH_5		0x00000074
+#define IPU_DC_WR_CH_CONF_6	0x00000078
+#define IPU_DC_WR_CH_ADDR_6	0x0000007c
+#define IPU_DC_RL0_CH_6		0x00000080
+#define IPU_DC_RL1_CH_6		0x00000084
+#define IPU_DC_RL2_CH_6		0x00000088
+#define IPU_DC_RL3_CH_6		0x0000008c
+#define IPU_DC_RL4_CH_6		0x00000090
+#define IPU_DC_WR_CH_CONF1_8	0x00000094
+#define IPU_DC_WR_CH_CONF2_8	0x00000098
+#define IPU_DC_RL1_CH_8		0x0000009c
+#define IPU_DC_RL2_CH_8		0x000000a0
+#define IPU_DC_RL3_CH_8		0x000000a4
+#define IPU_DC_RL4_CH_8		0x000000a8
+#define IPU_DC_RL5_CH_8		0x000000ac
+#define IPU_DC_RL6_CH_8		0x000000b0
+#define IPU_DC_WR_CH_CONF1_9	0x000000b4
+#define IPU_DC_WR_CH_CONF2_9	0x000000b8
+#define IPU_DC_RL1_CH_9		0x000000bc
+#define IPU_DC_RL2_CH_9		0x000000c0
+#define IPU_DC_RL3_CH_9		0x000000c4
+#define IPU_DC_RL4_CH_9		0x000000c8
+#define IPU_DC_RL5_CH_9		0x000000cc
+#define IPU_DC_RL6_CH_9		0x000000d0
+
+#define IPU_DC_RL(chan_base, evt)	((chan_base) + (evt / 2) *0x4)
+#define  DC_RL_CH_0		IPU_DC_RL0_CH_0
+#define  DC_RL_CH_1		IPU_DC_RL0_CH_1
+#define  DC_RL_CH_2		IPU_DC_RL0_CH_2
+#define  DC_RL_CH_5		IPU_DC_RL0_CH_5
+#define  DC_RL_CH_6		IPU_DC_RL0_CH_6
+#define  DC_RL_CH_8		IPU_DC_RL0_CH_8
+
+#define  DC_RL_EVT_NF		0
+#define  DC_RL_EVT_NL		1
+#define  DC_RL_EVT_EOF		2
+#define  DC_RL_EVT_NFIELD	3
+#define  DC_RL_EVT_EOL		4
+#define  DC_RL_EVT_EOFIELD	5
+#define  DC_RL_EVT_NEW_ADDR	6
+#define  DC_RL_EVT_NEW_CHAN	7
+#define  DC_RL_EVT_NEW_DATA	8
+
+#define IPU_DC_GEN		0x000000d4
+#define IPU_DC_DISP_CONF1_0	0x000000d8
+#define IPU_DC_DISP_CONF1_1	0x000000dc
+#define IPU_DC_DISP_CONF1_2	0x000000e0
+#define IPU_DC_DISP_CONF1_3	0x000000e4
+#define IPU_DC_DISP_CONF2_0	0x000000e8
+#define IPU_DC_DISP_CONF2_1	0x000000ec
+#define IPU_DC_DISP_CONF2_2	0x000000f0
+#define IPU_DC_DISP_CONF2_3	0x000000f4
+#define IPU_DC_DI0_CONF_1	0x000000f8
+#define IPU_DC_DI0_CONF_2	0x000000fc
+#define IPU_DC_DI1_CONF_1	0x00000100
+#define IPU_DC_DI1_CONF_2	0x00000104
+
+#define IPU_DC_MAP_CONF_PNTR(n)	(0x00000108 + (n) * 4)
+#define IPU_DC_MAP_CONF_0	0x00000108
+#define IPU_DC_MAP_CONF_1	0x0000010c
+#define IPU_DC_MAP_CONF_2	0x00000110
+#define IPU_DC_MAP_CONF_3	0x00000114
+#define IPU_DC_MAP_CONF_4	0x00000118
+#define IPU_DC_MAP_CONF_5	0x0000011c
+#define IPU_DC_MAP_CONF_6	0x00000120
+#define IPU_DC_MAP_CONF_7	0x00000124
+#define IPU_DC_MAP_CONF_8	0x00000128
+#define IPU_DC_MAP_CONF_9	0x0000012c
+#define IPU_DC_MAP_CONF_10	0x00000130
+#define IPU_DC_MAP_CONF_11	0x00000134
+#define IPU_DC_MAP_CONF_12	0x00000138
+#define IPU_DC_MAP_CONF_13	0x0000013c
+#define IPU_DC_MAP_CONF_14	0x00000140
+
+#define IPU_DC_MAP_CONF_MASK(n)	(0x00000144 + (n) * 4)
+#define IPU_DC_MAP_CONF_15	0x00000144
+#define IPU_DC_MAP_CONF_16	0x00000148
+#define IPU_DC_MAP_CONF_17	0x0000014c
+#define IPU_DC_MAP_CONF_18	0x00000150
+#define IPU_DC_MAP_CONF_19	0x00000154
+#define IPU_DC_MAP_CONF_20	0x00000158
+#define IPU_DC_MAP_CONF_21	0x0000015c
+#define IPU_DC_MAP_CONF_22	0x00000160
+#define IPU_DC_MAP_CONF_23	0x00000164
+#define IPU_DC_MAP_CONF_24	0x00000168
+#define IPU_DC_MAP_CONF_25	0x0000016c
+#define IPU_DC_MAP_CONF_26	0x00000170
+
+#define IPU_DC_UGDE(m, n)	(0x00000174 + (m) * 0x10 + (n) +4)
+#define IPU_DC_UGDE0_0		0x00000174
+#define IPU_DC_UGDE0_1		0x00000178
+#define IPU_DC_UGDE0_2		0x0000017c
+#define IPU_DC_UGDE0_3		0x00000180
+#define IPU_DC_UGDE1_0		0x00000184
+#define IPU_DC_UGDE1_1		0x00000188
+#define IPU_DC_UGDE1_2		0x0000018c
+#define IPU_DC_UGDE1_3		0x00000190
+#define IPU_DC_UGDE2_0		0x00000194
+#define IPU_DC_UGDE2_1		0x00000198
+#define IPU_DC_UGDE2_2		0x0000019c
+#define IPU_DC_UGDE2_3		0x000001a0
+#define IPU_DC_UGDE3_0		0x000001a4
+#define IPU_DC_UGDE3_1		0x000001a8
+#define IPU_DC_UGDE3_2		0x000001ac
+#define IPU_DC_UGDE3_3		0x000001b0
+#define IPU_DC_LLA0		0x000001b4
+#define IPU_DC_LLA1		0x000001b8
+#define IPU_DC_R_LLA0		0x000001bc
+#define IPU_DC_R_LLA1		0x000001c0
+#define IPU_DC_WR_CH_ADDR_5_ALT	0x000001c4
+#define IPU_DC_STAT		0x000001c8
+
+/*
+ * DMFC
+ * Display Multi FIFO Controller
+ */
+#define IPU_DMFC_RD_CHAN		0x00000000
+#define  DMFC_RD_CHAN_PPW_C		__BITS(25,24)
+#define  DMFC_RD_CHAN_WM_DR_0		__BITS(23,21)
+#define  DMFC_RD_CHAN_WM_SET_0		__BITS(20,18)
+#define  DMFC_RD_CHAN_WM_EN_0		__BIT(17)
+#define  DMFC_RD_CHAN_BURST_SIZE_0	__BITS( 7, 6)
+#define IPU_DMFC_WR_CHAN		0x00000004
+#define  DMFC_WR_CHAN_BUSRT_SIZE_2C	__BITS(31,30)
+#define  DMFC_WR_CHAN_FIFO_SIZE_2C	__BITS(29,27)
+#define  DMFC_WR_CHAN_ST_ADDR_2C	__BITS(26,24)
+#define  DMFC_WR_CHAN_BURST_SIZE_1C	__BITS(23,22)
+#define  DMFC_WR_CHAN_FIFO_SIZE_1C	__BITS(21,19)
+#define  DMFC_WR_CHAN_ST_ADDR_1C	__BITS(18,16)
+#define  DMFC_WR_CHAN_BURST_SIZE_2	__BITS(15,14)
+#define  DMFC_WR_CHAN_FIFO_SIZE_2	__BITS(13,11)
+#define  DMFC_WR_CHAN_ST_ADDR_2		__BITS(10, 8)
+#define  DMFC_WR_CHAN_BURST_SIZE_1	__BITS( 7, 6)
+#define  DMFC_WR_CHAN_FIFO_SIZE_1	__BITS( 5, 3)
+#define  DMFC_WR_CHAN_ST_ADDR_1		__BITS( 2, 0)
+#define IPU_DMFC_WR_CHAN_DEF		0x00000008
+#define  DMFC_WR_CHAN_DEF_WM_CLR_2C	__BITS(31,29)
+#define  DMFC_WR_CHAN_DEF_WM_SET_2C	__BITS(28,26)
+#define  DMFC_WR_CHAN_DEF_WM_EN_2C	__BIT(25)
+#define  DMFC_WR_CHAN_DEF_WM_CLR_1C	__BITS(23,21)
+#define  DMFC_WR_CHAN_DEF_WM_SET_1C	__BITS(20,18)
+#define  DMFC_WR_CHAN_DEF_WM_EN_1C	__BIT(17)
+#define  DMFC_WR_CHAN_DEF_WM_CLR_2	__BITS(15,13)
+#define  DMFC_WR_CHAN_DEF_WM_SET_2	__BITS(12,10)
+#define  DMFC_WR_CHAN_DEF_WM_EN_2	__BIT(9)
+#define  DMFC_WR_CHAN_DEF_WM_CLR_1	__BITS( 7, 5)
+#define  DMFC_WR_CHAN_DEF_WM_SET_1	__BITS( 3, 2)
+#define  DMFC_WR_CHAN_DEF_WM_EN_1	__BIT(1)
+#define IPU_DMFC_DP_CHAN		0x0000000c
+#define  DMFC_DP_CHAN_BUSRT_SIZE_6F	__BITS(31,30)
+#define  DMFC_DP_CHAN_FIFO_SIZE_6F	__BITS(29,27)
+#define  DMFC_DP_CHAN_ST_ADDR_6F	__BITS(26,24)
+#define  DMFC_DP_CHAN_BURST_SIZE_6B	__BITS(23,22)
+#define  DMFC_DP_CHAN_FIFO_SIZE_6B	__BITS(21,19)
+#define  DMFC_DP_CHAN_ST_ADDR_6B	__BITS(18,16)
+#define  DMFC_DP_CHAN_BURST_SIZE_5F	__BITS(15,14)
+#define  DMFC_DP_CHAN_FIFO_SIZE_5F	__BITS(13,11)
+#define  DMFC_DP_CHAN_ST_ADDR_5F	__BITS(10, 8)
+#define  DMFC_DP_CHAN_BURST_SIZE_5B	__BITS( 7, 6)
+#define  DMFC_DP_CHAN_FIFO_SIZE_5B	__BITS( 5, 3)
+#define  DMFC_DP_CHAN_ST_ADDR_5B	__BITS( 2, 0)
+#define IPU_DMFC_DP_CHAN_DEF		0x00000010
+#define  DMFC_DP_CHAN_DEF_WM_CLR_6F	__BITS(31,29)
+#define  DMFC_DP_CHAN_DEF_WM_SET_6F	__BITS(28,26)
+#define  DMFC_DP_CHAN_DEF_WM_EN_6F	__BIT(25)
+#define  DMFC_DP_CHAN_DEF_WM_CLR_6B	__BITS(23,21)
+#define  DMFC_DP_CHAN_DEF_WM_SET_6B	__BITS(20,18)
+#define  DMFC_DP_CHAN_DEF_WM_EN_6B	__BIT(17)
+#define  DMFC_DP_CHAN_DEF_WM_CLR_5F	__BITS(15,13)
+#define  DMFC_DP_CHAN_DEF_WM_SET_5F	__BITS(12,10)
+#define  DMFC_DP_CHAN_DEF_WM_EN_5F	__BIT(9)
+#define  DMFC_DP_CHAN_DEF_WM_CLR_5B	__BITS( 7, 5)
+#define  DMFC_DP_CHAN_DEF_WM_SET_5B	__BITS( 4, 2)
+#define  DMFC_DP_CHAN_DEF_WM_EN_5B	__BIT(1)
+#define IPU_DMFC_GENERAL1		0x00000014
+#define  DMFC_GENERAL1_WAIT4EOT_9	__BIT(24)
+#define  DMFC_GENERAL1_WAIT4EOT_6F	__BIT(23)
+#define  DMFC_GENERAL1_WAIT4EOT_6B	__BIT(22)
+#define  DMFC_GENERAL1_WAIT4EOT_5F	__BIT(21)
+#define  DMFC_GENERAL1_WAIT4EOT_5B	__BIT(20)
+#define  DMFC_GENERAL1_WAIT4EOT_4	__BIT(19)
+#define  DMFC_GENERAL1_WAIT4EOT_3	__BIT(18)
+#define  DMFC_GENERAL1_WAIT4EOT_2	__BIT(17)
+#define  DMFC_GENERAL1_WAIT4EOT_1	__BIT(16)
+#define  DMFC_GENERAL1_WM_CLR_9		__BITS(15,13)
+#define  DMFC_GENERAL1_WM_SET_9		__BITS(12,10)
+#define  DMFC_GENERAL1_BURST_SIZE_9	__BITS( 6, 5)
+#define  DMFC_GENERAL1_DCDP_SYNC_PR	__BITS( 1, 0)
+#define   DCDP_SYNC_PR_FORBIDDEN	0
+#define   DCDP_SYNC_PR_DC_DP		1
+#define   DCDP_SYNC_PR_DP_DC		2
+#define   DCDP_SYNC_PR_ROUNDROBIN	3
+#define IPU_DMFC_GENERAL2		0x00000018
+#define  DMFC_GENERAL2_FRAME_HEIGHT_RD	__BITS(28,16)
+#define  DMFC_GENERAL2_FRAME_WIDTH_RD	__BITS(12, 0)
+#define IPU_DMFC_IC_CTRL		0x0000001c
+#define  DMFC_IC_CTRL_IC_FRAME_HEIGHT_RD	__BITS(31,19)
+#define  DMFC_IC_CTRL_IC_FRAME_WIDTH_RD		__BITS(18, 6)
+#define  DMFC_IC_CTRL_IC_PPW_C			__BITS( 5, 4)
+#define  DMFC_IC_CTRL_IC_IN_PORT		__BITS( 2, 0)
+#define   IC_IN_PORT_CH28		0
+#define   IC_IN_PORT_CH41		1
+#define   IC_IN_PORT_DISABLE		2
+#define   IC_IN_PORT_CH23		4
+#define   IC_IN_PORT_CH27		5
+#define   IC_IN_PORT_CH24		6
+#define   IC_IN_PORT_CH29		7
+#define IPU_DMFC_WR_CHAN_ALT		0x00000020
+#define IPU_DMFC_WR_CHAN_DEF_ALT	0x00000024
+#define IPU_DMFC_DP_CHAN_ALT		0x00000028
+#define IPU_DMFC_DP_CHAN_DEF_ALT	0x0000002c
+#define  DMFC_DP_CHAN_DEF_ALT_WM_CLR_6F_ALT	__BITS(31,29)
+#define  DMFC_DP_CHAN_DEF_ALT_WM_SET_6F_ALT	__BITS(28,26)
+#define  DMFC_DP_CHAN_DEF_ALT_WM_EN_6F_ALT	__BIT(25)
+#define  DMFC_DP_CHAN_DEF_ALT_WM_CLR_6B_ALT	__BITS(23,21)
+#define  DMFC_DP_CHAN_DEF_ALT_WM_SET_6B_ALT	__BITS(20,18)
+#define  DMFC_DP_CHAN_DEF_ALT_WM_EN_6B_ALT	__BIT(17)
+#define  DMFC_DP_CHAN_DEF_ALT_WM_CLR_5B_ALT	__BITS( 7, 5)
+#define  DMFC_DP_CHAN_DEF_ALT_WM_SET_5B_ALT	__BITS( 4, 2)
+#define  DMFC_DP_CHAN_DEF_ALT_WM_EN_5B_ALT	__BIT(1)
+#define IPU_DMFC_GENERAL1_ALT		0x00000030
+#define  DMFC_GENERAL1_ALT_WAIT4EOT_6F_ALT	__BIT(23)
+#define  DMFC_GENERAL1_ALT_WAIT4EOT_6B_ALT	__BIT(22)
+#define  DMFC_GENERAL1_ALT_WAIT4EOT_5B_ALT	__BIT(20)
+#define  DMFC_GENERAL1_ALT_WAIT4EOT_2_ALT	__BIT(17)
+#define IPU_DMFC_STAT			0x00000034
+#define  DMFC_STAT_IC_BUFFER_EMPTY	__BIT(25)
+#define  DMFC_STAT_IC_BUFFER_FULL	__BIT(24)
+#define  DMFC_STAT_FIFO_EMPTY(n)	__BIT(12 + (n))
+#define  DMFC_STAT_FIFO_FULL(n)		__BIT((n))
+
+/*
+ * VCI
+ * Video De Interkacing Module
+ */
+#define IPU_VDI_FSIZE	0x00000000
+#define IPU_VDI_C	0x00000004
+
+/*
+ * DP
+ * Display Processor
+ */
+#define IPU_DP_COM_CONF_SYNC		0x00000000
+#define  DP_FG_EN_SYNC			__BIT(0)
+#define  DP_DP_GWAM_SYNC		__BIT(2)
+#define IPU_DP_GRAPH_WIND_CTRL_SYNC	0x00000004
+#define IPU_DP_FG_POS_SYNC		0x00000008
+#define IPU_DP_CUR_POS_SYNC		0x0000000c
+#define IPU_DP_CUR_MAP_SYNC		0x00000010
+#define IPU_DP_CSC_SYNC_0		0x00000054
+#define IPU_DP_CSC_SYNC_1		0x00000058
+#define IPU_DP_CUR_POS_ALT		0x0000005c
+#define IPU_DP_COM_CONF_ASYNC0		0x00000060
+#define IPU_DP_GRAPH_WIND_CTRL_ASYNC0	0x00000064
+#define IPU_DP_FG_POS_ASYNC0		0x00000068
+#define IPU_DP_CUR_POS_ASYNC0		0x0000006c
+#define IPU_DP_CUR_MAP_ASYNC0		0x00000070
+#define IPU_DP_CSC_ASYNC0_0		0x000000b4
+#define IPU_DP_CSC_ASYNC0_1		0x000000b8
+#define IPU_DP_COM_CONF_ASYNC1		0x000000bc
+#define IPU_DP_GRAPH_WIND_CTRL_ASYNC1	0x000000c0
+#define IPU_DP_FG_POS_ASYNC1		0x000000c4
+#define IPU_DP_CUR_POS_ASYNC1		0x000000c8
+#define IPU_DP_CUR_MAP_ASYNC1		0x000000cc
+#define IPU_DP_CSC_ASYNC1_0		0x00000110
+#define IPU_DP_CSC_ASYNC1_1		0x00000114
+
+/* IDMA parameter */
+	/*
+	 * non-Interleaved parameter
+	 *
+	 * param 0: XV W0[ 9: 0]
+	 *          YV W0[18:10]
+	 *          XB W0[31:19]
+	 * param 1: YB W0[43:32]
+	 *          NSB W0[44]
+	 *          CF W0[45]
+	 *          UBO W0[61:46]
+	 * param 2: UBO W0[67:62]
+	 *          VBO W0[89:68]
+	 *          IOX W0[93:90]
+	 *          RDRW W0[94]
+	 *          Reserved W0[95]
+	 * param 3: Reserved W0[112:96]
+	 *          S0 W0[113]
+	 *          BNDM W0[116:114]
+	 *          BM W0[118:117]
+	 *          ROT W0[119]
+	 *          HF W0[120]
+	 *          VF W0[121]
+	 *          THF W0[122]
+	 *          CAP W0[123]
+	 *          CAE W0[124]
+	 *          FW W0[127:125]
+	 * param 4: FW W0[137:128]
+	 *          FH W0[149:138]
+	 * param 5: EBA0 W1[28:0]
+	 *          EBA1 W1[31:29]
+	 * param 6: EBA1 W1[57:32]
+	 *          ILO W1[63:58]
+	 * param 7: ILO W1[77:64]
+	 *          NPB W1[84:78]
+	 *          PFS W1[88:85]
+	 *          ALU W1[89]
+	 *          ALBM W1[92:90]
+	 *          ID W1[94:93]
+	 *          TH W1[95]
+	 * param 8: TH W1[101:96]
+	 *          SLY W1[115:102]
+	 *          WID3 W1[127:125]
+	 * param 9: SLUV W1[141:128]
+	 *          CRE W1[149]
+	 *
+	 * Interleaved parameter
+	 *
+	 * param 0: XV W0[ 9: 0]
+	 *          YV W0[18:10]
+	 *          XB W0[31:19]
+	 * param 1: YB W0[43:32]
+	 *          NSB W0[44]
+	 *          CF W0[45]
+	 *          SX W0[57:46]
+	 *          SY W0[61:58]
+	 * param 2: SY W0[68:62]
+	 *          NS W0[78:69]
+	 *          SDX W0[85:79]
+	 *          SM W0[95:86]
+	 * param 3: SCC W0[96]
+	 *          SCE W0[97]
+	 *          SDY W0[104:98]
+	 *          SDRX W0[105]
+	 *          SDRY W0[106]
+	 *          BPP W0[109:107]
+	 *	    DEC_SEL W0[111:110]
+	 *          DIM W0[112]
+	 *          SO W0[113]
+	 *          BNDM W0[116:114]
+	 *          BM W0[118:117]
+	 *          ROT W0[119]
+	 *          HF W0[120]
+	 *          VF W0[121]
+	 *          THF W0[122]
+	 *          CAP W0[123]
+	 *          CAE W0[124]
+	 *          FW W0[127:125]
+	 * param 4: FW W0[137:128]
+	 *          FH W0[149:138]
+	 * param 5: EBA0 W1[28:0]
+	 *          EBA1 W1[31:29]
+	 * param 6: EBA1 W1[57:32]
+	 *          ILO W1[63:58]
+	 * param 7: ILO W1[77:64]
+	 *          NPB W1[84:78]
+	 *          PFS W1[88:85]
+	 *          ALU W1[89]
+	 *          ALBM W1[92:90]
+	 *          ID W1[94:93]
+	 *          TH W1[95]
+	 * param 8: TH W1[101:96]
+	 *          SL W1[115:102]
+	 *          WID0 W1[118:116]
+	 *          WID1 W1[121:119]
+	 *          WID2 W1[124:122]
+	 *          WID3 W1[127:125]
+	 * param 9: OFS0 W1[132:128]
+	 *          OFS1 W1[137:133]
+	 *          OFS2 W1[142:138]
+	 *          OFS3 W1[147:143]
+	 *          SXYS W1[148]
+	 *          CRE W1[149]
+	 *          DEC_SEL2 W1[150]
+	 */
+
+#define __IDMA_PARAM(word, shift, size) \
+	((((word) & 0xff) << 16) | (((shift) & 0xff) << 8) | ((size) & 0xff))
+
+/* non-Interleaved parameter */
+/* W0 */
+#define IDMAC_Ch_PARAM_XV	__IDMA_PARAM(0,  0, 10)
+#define IDMAC_Ch_PARAM_YV	__IDMA_PARAM(0, 10,  9)
+#define IDMAC_Ch_PARAM_XB	__IDMA_PARAM(0, 19, 13)
+#define IDMAC_Ch_PARAM_YB	__IDMA_PARAM(0, 32, 12)
+#define IDMAC_Ch_PARAM_NSB	__IDMA_PARAM(0, 44,  1)
+#define IDMAC_Ch_PARAM_CF	__IDMA_PARAM(0, 45,  1)
+#define IDMAC_Ch_PARAM_UBO	__IDMA_PARAM(0, 46, 22)
+#define IDMAC_Ch_PARAM_VBO	__IDMA_PARAM(0, 68, 22)
+#define IDMAC_Ch_PARAM_IOX	__IDMA_PARAM(0, 90,  4)
+#define IDMAC_Ch_PARAM_RDRW	__IDMA_PARAM(0, 94,  1)
+#define IDMAC_Ch_PARAM_S0	__IDMA_PARAM(0,113,  1)
+#define IDMAC_Ch_PARAM_BNDM	__IDMA_PARAM(0,114,  3)
+#define IDMAC_Ch_PARAM_BM	__IDMA_PARAM(0,117,  2)
+#define IDMAC_Ch_PARAM_ROT	__IDMA_PARAM(0,119,  1)
+#define IDMAC_Ch_PARAM_HF	__IDMA_PARAM(0,120,  1)
+#define IDMAC_Ch_PARAM_VF	__IDMA_PARAM(0,121,  1)
+#define IDMAC_Ch_PARAM_THF	__IDMA_PARAM(0,122,  1)
+#define IDMAC_Ch_PARAM_CAP	__IDMA_PARAM(0,123,  1)
+#define IDMAC_Ch_PARAM_CAE	__IDMA_PARAM(0,124,  1)
+#define IDMAC_Ch_PARAM_FW	__IDMA_PARAM(0,125, 13)
+#define IDMAC_Ch_PARAM_FH	__IDMA_PARAM(0,138, 12)
+/* W1 */
+#define IDMAC_Ch_PARAM_EBA0	__IDMA_PARAM(1,  0, 29)
+#define IDMAC_Ch_PARAM_EBA1	__IDMA_PARAM(1, 29, 29)
+#define IDMAC_Ch_PARAM_ILO	__IDMA_PARAM(1, 58, 20)
+#define IDMAC_Ch_PARAM_NPB	__IDMA_PARAM(1, 78,  7)
+#define IDMAC_Ch_PARAM_PFS	__IDMA_PARAM(1, 85,  4)
+#define IDMAC_Ch_PARAM_ALU	__IDMA_PARAM(1, 89,  1)
+#define IDMAC_Ch_PARAM_ALBM	__IDMA_PARAM(1, 90,  3)
+#define IDMAC_Ch_PARAM_ID	__IDMA_PARAM(1, 93,  2)
+#define IDMAC_Ch_PARAM_TH	__IDMA_PARAM(1, 95,  7)
+#define IDMAC_Ch_PARAM_SL	__IDMA_PARAM(1,102, 14)
+#define IDMAC_Ch_PARAM_WID3	__IDMA_PARAM(1,125,  3)
+#define IDMAC_Ch_PARAM_SLUV	__IDMA_PARAM(1,128, 14)
+#define IDMAC_Ch_PARAM_CRE	__IDMA_PARAM(1,149,  1)
+
+/* Interleaved parameter */
+/* W0 */
+#define IDMAC_Ch_PARAM_XV	__IDMA_PARAM(0,  0, 10)
+#define IDMAC_Ch_PARAM_YV	__IDMA_PARAM(0, 10,  9)
+#define IDMAC_Ch_PARAM_XB	__IDMA_PARAM(0, 19, 13)
+#define IDMAC_Ch_PARAM_YB	__IDMA_PARAM(0, 32, 12)
+#define IDMAC_Ch_PARAM_NSB	__IDMA_PARAM(0, 44,  1)
+#define IDMAC_Ch_PARAM_CF	__IDMA_PARAM(0, 45,  1)
+#define IDMAC_Ch_PARAM_SX	__IDMA_PARAM(0, 46, 12)
+#define IDMAC_Ch_PARAM_SY	__IDMA_PARAM(0, 58, 11)
+#define IDMAC_Ch_PARAM_NS	__IDMA_PARAM(0, 69, 10)
+#define IDMAC_Ch_PARAM_SDX	__IDMA_PARAM(0, 79,  7)
+#define IDMAC_Ch_PARAM_SM	__IDMA_PARAM(0, 86, 10)
+#define IDMAC_Ch_PARAM_SCC	__IDMA_PARAM(0, 96,  1)
+#define IDMAC_Ch_PARAM_SCE	__IDMA_PARAM(0, 97,  1)
+#define IDMAC_Ch_PARAM_SDY	__IDMA_PARAM(0, 98,  7)
+#define IDMAC_Ch_PARAM_SDRX	__IDMA_PARAM(0,105,  1)
+#define IDMAC_Ch_PARAM_SDRY	__IDMA_PARAM(0,106,  1)
+#define IDMAC_Ch_PARAM_BPP	__IDMA_PARAM(0,107,  3)
+#define IDMAC_Ch_PARAM_DEC_SEL	__IDMA_PARAM(0,110,  2)
+#define IDMAC_Ch_PARAM_DIM	__IDMA_PARAM(0,112,  1)
+#define IDMAC_Ch_PARAM_SO	__IDMA_PARAM(0,113,  1)
+#define IDMAC_Ch_PARAM_BNDM	__IDMA_PARAM(0,114,  3)
+#define IDMAC_Ch_PARAM_BM	__IDMA_PARAM(0,117,  2)
+#define IDMAC_Ch_PARAM_ROT	__IDMA_PARAM(0,119,  1)
+#define IDMAC_Ch_PARAM_HF	__IDMA_PARAM(0,120,  1)
+#define IDMAC_Ch_PARAM_VF	__IDMA_PARAM(0,121,  1)
+#define IDMAC_Ch_PARAM_THF	__IDMA_PARAM(0,122,  1)
+#define IDMAC_Ch_PARAM_CAP	__IDMA_PARAM(0,123,  1)
+#define IDMAC_Ch_PARAM_CAE	__IDMA_PARAM(0,124,  1)
+#define IDMAC_Ch_PARAM_FW	__IDMA_PARAM(0,125, 13)
+#define IDMAC_Ch_PARAM_FH	__IDMA_PARAM(0,138, 12)
+/* W1 */
+#define IDMAC_Ch_PARAM_EBA0	__IDMA_PARAM(1,  0, 29)
+#define IDMAC_Ch_PARAM_EBA1	__IDMA_PARAM(1, 29, 29)
+#define IDMAC_Ch_PARAM_ILO	__IDMA_PARAM(1, 58, 20)
+#define IDMAC_Ch_PARAM_NPB	__IDMA_PARAM(1, 78,  7)
+#define IDMAC_Ch_PARAM_PFS	__IDMA_PARAM(1, 85,  4)
+#define IDMAC_Ch_PARAM_ALU	__IDMA_PARAM(1, 89,  1)
+#define IDMAC_Ch_PARAM_ALBM	__IDMA_PARAM(1, 90,  3)
+#define IDMAC_Ch_PARAM_ID	__IDMA_PARAM(1, 93,  2)
+#define IDMAC_Ch_PARAM_TH	__IDMA_PARAM(1, 95,  7)
+#define IDMAC_Ch_PARAM_SL	__IDMA_PARAM(1,102, 14)
+#define IDMAC_Ch_PARAM_WID0	__IDMA_PARAM(1,116,  3)
+#define IDMAC_Ch_PARAM_WID1	__IDMA_PARAM(1,119,  3)
+#define IDMAC_Ch_PARAM_WID2	__IDMA_PARAM(1,122,  3)
+#define IDMAC_Ch_PARAM_WID3	__IDMA_PARAM(1,125,  3)
+#define IDMAC_Ch_PARAM_OFS0	__IDMA_PARAM(1,128,  5)
+#define IDMAC_Ch_PARAM_OFS1	__IDMA_PARAM(1,133,  5)
+#define IDMAC_Ch_PARAM_OFS2	__IDMA_PARAM(1,138,  5)
+#define IDMAC_Ch_PARAM_OFS3	__IDMA_PARAM(1,143,  5)
+#define IDMAC_Ch_PARAM_SXYS	__IDMA_PARAM(1,148,  1)
+#define IDMAC_Ch_PARAM_CRE	__IDMA_PARAM(1,149,  1)
+#define IDMAC_Ch_PARAM_DEC_SEL2 __IDMA_PARAM(1,150,  1)
+
+#endif /* _ARM_IMX_IMX51_IPUV3REG_H */
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/sys/arch/arm/imx/imx51_ipuv3var.h	Sun Apr 29 23:04:36 2012 +0000
@@ -0,0 +1,137 @@
+/*	$NetBSD: imx51_ipuv3var.h,v 1.1.2.2 2012/04/29 23:04:38 mrg Exp $	*/
+
+/*
+ * Copyright (c) 2009, 2011, 2012  Genetec Corporation.  All rights reserved.
+ * Written by Hashimoto Kenichi for Genetec Corporation.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY GENETEC CORPORATION ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL GENETEC CORPORATION
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+
+#ifndef _ARM_IMX_IMX51_IPUV3_H
+#define _ARM_IMX_IMX51_IPUV3_H
+
+#include <sys/bus.h>
+#include <dev/rasops/rasops.h>
+#include <dev/wscons/wsdisplay_vconsvar.h>
+
+/* IPUV3 Contoroller */
+struct imx51_ipuv3_screen {
+	LIST_ENTRY(imx51_ipuv3_screen) link;
+
+	/* Frame buffer */
+	bus_dmamap_t dma;
+	bus_dma_segment_t segs[1];
+	int 	nsegs;
+	size_t  buf_size;
+	size_t  map_size;
+	void 	*buf_va;
+	int	depth;
+	int	stride;
+
+	/* DMA frame descriptor */
+	struct	ipuv3_dma_descriptor *dma_desc;
+	paddr_t	dma_desc_pa;
+};
+
+struct lcd_panel_geometry {
+	short panel_width;
+	short panel_height;
+
+	uint32_t pixel_clk;
+
+	short hsync_width;
+	short left;
+	short right;
+
+	short vsync_width;
+	short upper;
+	short lower;
+
+	short panel_info;
+#define IPUV3PANEL_SHARP	(1<<0)		/* sharp panel */
+	uint32_t panel_sig_pol;
+};
+
+struct imx51_ipuv3_softc {
+	device_t		dev;
+
+	/* control register */
+	bus_space_tag_t  	iot;
+	bus_space_handle_t	cm_ioh;		/* CM */
+	bus_space_handle_t	dmfc_ioh;	/* DMFC */
+	bus_space_handle_t	di0_ioh;	/* DI 0 */
+	bus_space_handle_t	dp_ioh;		/* DP */
+	bus_space_handle_t	dc_ioh;		/* DC */
+	bus_space_handle_t	idmac_ioh;	/* IDMAC */
+	bus_space_handle_t	cpmem_ioh;	/* CPMEM */
+	bus_space_handle_t	dctmpl_ioh;	/* DCTMPL */
+	bus_dma_tag_t    	dma_tag;
+
+	uint32_t		flags;
+#define FLAG_NOUSE_ACBIAS	(1U<<0)
+
+	const struct lcd_panel_geometry *geometry;
+
+	int n_screens;
+	LIST_HEAD(, imx51_ipuv3_screen) screens;
+	struct imx51_ipuv3_screen *active;
+	void *ih;			/* interrupt handler */
+
+	/* virtual console support */
+	struct vcons_data vd;
+	struct vcons_screen console;
+	int mode;
+};
+
+/*
+ * we need bits-per-pixel value to configure wsdisplay screen
+ */
+struct imx51_wsscreen_descr {
+	struct wsscreen_descr  c;	/* standard descriptor */
+	int depth;			/* bits per pixel */
+	int flags;			/* rasops flags */
+};
+
+struct imx51_ipuv3_softc;
+
+void	imx51_ipuv3_attach_sub(struct imx51_ipuv3_softc *,
+	    struct axi_attach_args *, const struct lcd_panel_geometry *);
+int	imx51_ipuv3_cnattach(const struct lcd_panel_geometry *);
+void	imx51_ipuv3_start_dma(struct imx51_ipuv3_softc *,
+	    struct imx51_ipuv3_screen *);
+
+void	imx51_ipuv3_geometry(struct imx51_ipuv3_softc *,
+	    const struct lcd_panel_geometry *);
+int	imx51_ipuv3_new_screen(struct imx51_ipuv3_softc *, int,
+	    struct imx51_ipuv3_screen **);
+
+int	imx51_ipuv3_ioctl(void *, void *, u_long, void *, int, struct lwp *);
+paddr_t	imx51_ipuv3_mmap(void *, void *, off_t, int);
+
+void	imx51_ipuv3_power(int, void *);
+void	imx51_ipuv3_suspend(struct imx51_ipuv3_softc *);
+void	imx51_ipuv3_resume(struct imx51_ipuv3_softc *);
+
+extern const struct wsdisplay_emulops imx51_ipuv3_emulops;
+
+#endif /* _ARM_IMX_IMX51_IPUV3_H */
--- a/sys/arch/arm/imx/imx51reg.h	Tue Apr 17 19:25:17 2012 +0000
+++ b/sys/arch/arm/imx/imx51reg.h	Sun Apr 29 23:04:36 2012 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: imx51reg.h,v 1.2 2010/11/30 13:05:27 bsh Exp $ */
+/* $NetBSD: imx51reg.h,v 1.2.14.1 2012/04/29 23:04:38 mrg Exp $ */
 /*-
  * Copyright (c) 2007 The NetBSD Foundation, Inc.
  * All rights reserved.
@@ -43,9 +43,44 @@
 #define	GPU_BASE	0x30000000
 #define	GPU_SIZE	0x10000000
 
-/* LCD controller */
-#define	IPUEX_BASE	0x40000000
-#define	IPUEX_SIZE	0x20000000
+/* Image Prossasing Unit */
+#define	IPU_BASE	0x40000000
+#define	IPU_CM_BASE	(IPU_BASE + 0x1e000000)
+#define	IPU_CM_SIZE	0x8000
+#define	IPU_IDMAC_BASE	(IPU_BASE + 0x1e008000)
+#define	IPU_IDMAC_SIZE	0x8000
+#define	IPU_DP_BASE	(IPU_BASE + 0x1e018000)
+#define	IPU_DP_SIZE	0x8000
+#define	IPU_IC_BASE	(IPU_BASE + 0x1e020000)
+#define	IPU_IC_SIZE	0x8000
+#define	IPU_IRT_BASE	(IPU_BASE + 0x1e028000)
+#define	IPU_IRT_SIZE	0x8000
+#define	IPU_CSI0_BASE	(IPU_BASE + 0x1e030000)
+#define	IPU_CSI0_SIZE	0x8000
+#define	IPU_CSI1_BASE	(IPU_BASE + 0x1e038000)
+#define	IPU_CSI1_SIZE	0x8000
+#define	IPU_DI0_BASE	(IPU_BASE + 0x1e040000)
+#define	IPU_DI0_SIZE	0x8000
+#define	IPU_DI1_BASE	(IPU_BASE + 0x1e048000)
+#define	IPU_DI1_SIZE	0x8000
+#define	IPU_SMFC_BASE	(IPU_BASE + 0x1e050000)
+#define	IPU_SMFC_SIZE	0x8000
+#define	IPU_DC_BASE	(IPU_BASE + 0x1e058000)
+#define	IPU_DC_SIZE	0x8000
+#define	IPU_DMFC_BASE	(IPU_BASE + 0x1e060000)
+#define	IPU_DMFC_SIZE	0x8000
+#define	IPU_VDI_BASE	(IPU_BASE + 0x1e068000)
+#define	IPU_VDI_SIZE	0x8000
+#define	IPU_CPMEM_BASE	(IPU_BASE + 0x1f000000)
+#define	IPU_CPMEM_SIZE	0x20000
+#define	IPU_LUT_BASE	(IPU_BASE + 0x1f020000)
+#define	IPU_LUT_SIZE	0x20000
+#define	IPU_SRM_BASE	(IPU_BASE + 0x1f040000)
+#define	IPU_SRM_SIZE	0x20000
+#define	IPU_TPM_BASE	(IPU_BASE + 0x1f060000)
+#define	IPU_TPM_SIZE	0x20000
+#define	IPU_DCTMPL_BASE	(IPU_BASE + 0x1f080000)
+#define	IPU_DCTMPL_SIZE	0x20000
 
 #define	DEBUGROM_BASE	0x60000000
 #define	DEBUGROM_SIZE	0x1000
@@ -185,6 +220,7 @@
 #define	IOMUXC_SIZE	0x4000
 
 #define	IOMUXC_MUX_CTL		0x001c		/* multiprex control */
+#define	 IOMUX_CONFIG_SION	__BIT(4)
 #define	 IOMUX_CONFIG_ALT0	(0)
 #define	 IOMUX_CONFIG_ALT1	(1)
 #define	 IOMUX_CONFIG_ALT2	(2)
@@ -193,8 +229,8 @@
 #define	 IOMUX_CONFIG_ALT5	(5)
 #define	 IOMUX_CONFIG_ALT6	(6)
 #define	 IOMUX_CONFIG_ALT7	(7)
-#define	 IOMUX_CONFIG_SION	__BIT(4)
 #define	IOMUXC_PAD_CTL		0x03f0		/* pad control */
+#define	 PAD_CTL_HVE		__BIT(13)
 #define	 PAD_CTL_DDR_INPUT	__BIT(9)
 #define	 PAD_CTL_HYS		__BIT(8)
 #define	 PAD_CTL_PKE		__BIT(7)
--- a/sys/arch/arm/imx/imxclock.c	Tue Apr 17 19:25:17 2012 +0000
+++ b/sys/arch/arm/imx/imxclock.c	Sun Apr 29 23:04:36 2012 +0000
@@ -1,4 +1,4 @@
-/*	$NetBSD: imxclock.c,v 1.4 2011/07/01 20:27:50 dyoung Exp $ */
+/*	$NetBSD: imxclock.c,v 1.4.6.1 2012/04/29 23:04:38 mrg Exp $ */
 /*
  * Copyright (c) 2009, 2010  Genetec corp.  All rights reserved.
  * Written by Hashimoto Kenichi for Genetec corp.
@@ -70,7 +70,7 @@
 cpu_initclocks(void)
 {
 	uint32_t reg;
-	int freq;
+	u_int freq;
 
 	if (!epit1_sc) {
 		panic("%s: driver has not been initialized!", __FUNCTION__);
@@ -80,6 +80,9 @@
 	imx_epit_timecounter.tc_frequency = freq;
 	tc_init(&imx_epit_timecounter);
 
+	aprint_verbose_dev(epit1_sc->sc_dev,
+			   "timer clock frequency %d\n", freq);
+
 	epit1_sc->sc_reload_value = freq / hz - 1;
 
 	/* stop all timers */
@@ -92,11 +95,13 @@
 			  epit1_sc->sc_reload_value);
 	bus_space_write_4(epit1_sc->sc_iot, epit1_sc->sc_ioh, EPIT_EPITCMPR, 0);
 
-	reg = EPITCR_ENMOD | EPITCR_IOVW | EPITCR_RLD;
-	bus_space_write_4(epit1_sc->sc_iot, epit1_sc->sc_ioh, EPIT_EPITCR, reg);
-	reg |= EPITCR_EN | EPITCR_OCIEN | EPITCR_CLKSRC_HIGH |
-		EPITCR_WAITEN | EPITCR_DOZEN | EPITCR_STOPEN;
-	bus_space_write_4(epit1_sc->sc_iot, epit1_sc->sc_ioh, EPIT_EPITCR, reg);
+	reg = EPITCR_ENMOD | EPITCR_IOVW | EPITCR_RLD | epit1_sc->sc_clksrc;
+	bus_space_write_4(epit1_sc->sc_iot, epit1_sc->sc_ioh,
+	    EPIT_EPITCR, reg);
+	reg |= EPITCR_EN | EPITCR_OCIEN | EPITCR_WAITEN | EPITCR_DOZEN |
+		EPITCR_STOPEN;
+	bus_space_write_4(epit1_sc->sc_iot, epit1_sc->sc_ioh,
+	    EPIT_EPITCR, reg);
 
 	epit1_sc->sc_ih = intr_establish(epit1_sc->sc_intr, IPL_CLOCK,
 	    IST_LEVEL, imxclock_intr, epit1_sc);
--- a/sys/arch/arm/imx/imxclockvar.h	Tue Apr 17 19:25:17 2012 +0000
+++ b/sys/arch/arm/imx/imxclockvar.h	Sun Apr 29 23:04:36 2012 +0000
@@ -9,6 +9,8 @@
 
 	int sc_reload_value;
 
+	uint32_t sc_clksrc;
+
 	void *sc_ih;			/* interrupt handler */
 };
 
--- a/sys/arch/arm/imx/imxepitreg.h	Tue Apr 17 19:25:17 2012 +0000
+++ b/sys/arch/arm/imx/imxepitreg.h	Sun Apr 29 23:04:36 2012 +0000
@@ -1,6 +1,6 @@
-/*	$NetBSD: imxepitreg.h,v 1.1 2010/11/13 06:51:37 bsh Exp $ */
+/*	$NetBSD: imxepitreg.h,v 1.1.16.1 2012/04/29 23:04:38 mrg Exp $ */
 /*
- * Copyright (c) 2009, 2010  Genetec corp.  All rights reserved.
+ * Copyright (c) 2009, 2010, 2012  Genetec corp.  All rights reserved.
  * Written by Hashimoto Kenichi for Genetec corp.
  *
  * Redistribution and use in source and binary forms, with or without
@@ -37,11 +37,15 @@
 #define	 EPITCR_IOVW	__BIT(17)
 #define	 EPITCR_DBGEN	__BIT(18)
 #define	 EPITCR_WAITEN	__BIT(19)
-#define	 EPITCR_DOZEN	__BIT(20)
+#define	 EPITCR_DOZEN	__BIT(20)	/* not in iMX51 */
 #define	 EPITCR_STOPEN	__BIT(21)
 #define	 EPITCR_OM	__BITS(22,23)
-#define	 EPITCR_CLKSRC_MASK	__BITS(24,25)
-#define	 EPITCR_CLKSRC_HIGH	(0x2 << 24)
+#define	 EPITCR_CLKSRC_SHIFT	24
+#define	 EPITCR_CLKSRC_MASK	__BITS(25, EPITCR_CLKSRC_SHIFT)
+#define	 EPITCR_CLKSRC_IPG	(1 << EPITCR_CLKSRC_SHIFT)
+#define	 EPITCR_CLKSRC_IPGHIGH	(2 << EPITCR_CLKSRC_SHIFT)
+#define	 EPITCR_CLKSRC_IPG32K	(3 << EPITCR_CLKSRC_SHIFT)
+#define	 EPITCR_CLKSRC_HIGH	(2 << EPITCR_CLKSRC_SHIFT)
 
 #define	EPIT_EPITSR	0x0004
 #define	EPIT_EPITLR	0x0008
--- a/sys/arch/evbarm/conf/ADI_BRH	Tue Apr 17 19:25:17 2012 +0000
+++ b/sys/arch/evbarm/conf/ADI_BRH	Sun Apr 29 23:04:36 2012 +0000
@@ -1,4 +1,4 @@
-#	$NetBSD: ADI_BRH,v 1.55.2.1 2012/02/18 07:31:45 mrg Exp $
+#	$NetBSD: ADI_BRH,v 1.55.2.2 2012/04/29 23:04:38 mrg Exp $
 #
 #	ADI_BRH -- ADI Engineering "Big Red Head" i80200 Evaluation Board
 #
@@ -98,10 +98,6 @@
 
 options 	SYSVMSG		# System V-like message queues
 options 	SYSVSEM		# System V-like semaphores
-#options 	SEMMNI=10	# number of semaphore identifiers
-#options 	SEMMNS=60	# number of semaphores in system
-#options 	SEMUME=10	# max number of undo entries per process
-#options 	SEMMNU=30	# number of undo structures in system
 options 	SYSVSHM		# System V-like memory sharing
 
 # Device options
--- a/sys/arch/evbarm/conf/ARMADILLO210	Tue Apr 17 19:25:17 2012 +0000
+++ b/sys/arch/evbarm/conf/ARMADILLO210	Sun Apr 29 23:04:36 2012 +0000
@@ -1,4 +1,4 @@
-#	$NetBSD: ARMADILLO210,v 1.19.2.2 2012/03/11 01:52:20 mrg Exp $
+#	$NetBSD: ARMADILLO210,v 1.19.2.3 2012/04/29 23:04:38 mrg Exp $
 #
 #	ARMADILLO210 -- Atmark Techno, Armadillo-210
 #
@@ -89,10 +89,6 @@
 # Shared memory options
 #options 	SYSVMSG		# System V-like message queues
 #options 	SYSVSEM		# System V-like semaphores
-#options 	SEMMNI=10	# number of semaphore identifiers
-#options 	SEMMNS=60	# number of semaphores in system
-#options 	SEMUME=10	# max number of undo entries per process
-#options 	SEMMNU=30	# number of undo structures in system
 #options 	SYSVSHM		# System V-like memory sharing
 
 # Device options
--- a/sys/arch/evbarm/conf/ARMADILLO9	Tue Apr 17 19:25:17 2012 +0000
+++ b/sys/arch/evbarm/conf/ARMADILLO9	Sun Apr 29 23:04:36 2012 +0000
@@ -1,4 +1,4 @@
-#	$NetBSD: ARMADILLO9,v 1.31.2.2 2012/03/11 01:52:20 mrg Exp $
+#	$NetBSD: ARMADILLO9,v 1.31.2.3 2012/04/29 23:04:38 mrg Exp $
 #
 #	ARMADILLO9 -- Atmark Techno, Armadillo-9
 #
@@ -89,10 +89,6 @@
 # Shared memory options
 options 	SYSVMSG		# System V-like message queues
 options 	SYSVSEM		# System V-like semaphores
-#options 	SEMMNI=10	# number of semaphore identifiers
-#options 	SEMMNS=60	# number of semaphores in system
-#options 	SEMUME=10	# max number of undo entries per process
-#options 	SEMMNU=30	# number of undo structures in system
 options 	SYSVSHM		# System V-like memory sharing
 
 # Device options
--- a/sys/arch/evbarm/conf/BEAGLEBOARD	Tue Apr 17 19:25:17 2012 +0000
+++ b/sys/arch/evbarm/conf/BEAGLEBOARD	Sun Apr 29 23:04:36 2012 +0000
@@ -1,5 +1,5 @@
 #
-#	$NetBSD: BEAGLEBOARD,v 1.23.2.1 2012/02/18 07:31:46 mrg Exp $
+#	$NetBSD: BEAGLEBOARD,v 1.23.2.2 2012/04/29 23:04:38 mrg Exp $
 #
 #	BEAGLEBOARD -- TI OMAP 3530 Eval Board Kernel
 #
@@ -106,10 +106,6 @@
 
 options 	SYSVMSG		# System V-like message queues
 options 	SYSVSEM		# System V-like semaphores
-#options 	SEMMNI=10	# number of semaphore identifiers
-#options 	SEMMNS=60	# number of semaphores in system
-#options 	SEMUME=10	# max number of undo entries per process
-#options 	SEMMNU=30	# number of undo structures in system
 options 	SYSVSHM		# System V-like memory sharing
 
 # Device options
--- a/sys/arch/evbarm/conf/CP3100	Tue Apr 17 19:25:17 2012 +0000
+++ b/sys/arch/evbarm/conf/CP3100	Sun Apr 29 23:04:36 2012 +0000
@@ -1,4 +1,4 @@
-#	$NetBSD: CP3100,v 1.23.2.2 2012/03/11 01:52:20 mrg Exp $
+#	$NetBSD: CP3100,v 1.23.2.3 2012/04/29 23:04:38 mrg Exp $
 #
 #	CP3100 -- Certance CP3100 Kernel
 #
@@ -103,10 +103,6 @@
 
 options 	SYSVMSG		# System V-like message queues
 options 	SYSVSEM		# System V-like semaphores
-#options 	SEMMNI=10	# number of semaphore identifiers
-#options 	SEMMNS=60	# number of semaphores in system
-#options 	SEMUME=10	# max number of undo entries per process
-#options 	SEMMNU=30	# number of undo structures in system
 options 	SYSVSHM		# System V-like memory sharing
 
 # Device options
--- a/sys/arch/evbarm/conf/GEMINI	Tue Apr 17 19:25:17 2012 +0000
+++ b/sys/arch/evbarm/conf/GEMINI	Sun Apr 29 23:04:36 2012 +0000
@@ -96,10 +96,6 @@
 
 options 	SYSVMSG		# System V-like message queues
 options 	SYSVSEM		# System V-like semaphores
-#options 	SEMMNI=10	# number of semaphore identifiers
-#options 	SEMMNS=60	# number of semaphores in system
-#options 	SEMUME=10	# max number of undo entries per process
-#options 	SEMMNU=30	# number of undo structures in system
 options 	SYSVSHM		# System V-like memory sharing
 
 # Device options
--- a/sys/arch/evbarm/conf/GEMINI_MASTER	Tue Apr 17 19:25:17 2012 +0000
+++ b/sys/arch/evbarm/conf/GEMINI_MASTER	Sun Apr 29 23:04:36 2012 +0000
@@ -97,10 +97,6 @@
 
 options 	SYSVMSG		# System V-like message queues
 options 	SYSVSEM		# System V-like semaphores
-#options 	SEMMNI=10	# number of semaphore identifiers
-#options 	SEMMNS=60	# number of semaphores in system
-#options 	SEMUME=10	# max number of undo entries per process
-#options 	SEMMNU=30	# number of undo structures in system
 options 	SYSVSHM		# System V-like memory sharing
 
 # Device options
--- a/sys/arch/evbarm/conf/GEMINI_SLAVE	Tue Apr 17 19:25:17 2012 +0000
+++ b/sys/arch/evbarm/conf/GEMINI_SLAVE	Sun Apr 29 23:04:36 2012 +0000
@@ -96,10 +96,6 @@
 
 options 	SYSVMSG		# System V-like message queues
 options 	SYSVSEM		# System V-like semaphores
-#options 	SEMMNI=10	# number of semaphore identifiers
-#options 	SEMMNS=60	# number of semaphores in system
-#options 	SEMUME=10	# max number of undo entries per process
-#options 	SEMMNU=30	# number of undo structures in system
 options 	SYSVSHM		# System V-like memory sharing
 
 # Device options
--- a/sys/arch/evbarm/conf/GUMSTIX	Tue Apr 17 19:25:17 2012 +0000
+++ b/sys/arch/evbarm/conf/GUMSTIX	Sun Apr 29 23:04:36 2012 +0000
@@ -1,4 +1,4 @@
-#	$NetBSD: GUMSTIX,v 1.61.2.2 2012/03/11 01:52:20 mrg Exp $
+#	$NetBSD: GUMSTIX,v 1.61.2.3 2012/04/29 23:04:38 mrg Exp $
 #
 #	GUMSTIX -- Gumstix. Inc. gumstix platforms kernel
 #
@@ -125,10 +125,6 @@
 
 #options 	SYSVMSG		# System V-like message queues
 #options 	SYSVSEM		# System V-like semaphores
-#options 	SEMMNI=10	# number of semaphore identifiers
-#options 	SEMMNS=60	# number of semaphores in system
-#options 	SEMUME=10	# max number of undo entries per process
-#options 	SEMMNU=30	# number of undo structures in system
 #options 	SYSVSHM		# System V-like memory sharing
 
 # Device options
--- a/sys/arch/evbarm/conf/HDL_G	Tue Apr 17 19:25:17 2012 +0000
+++ b/sys/arch/evbarm/conf/HDL_G	Sun Apr 29 23:04:36 2012 +0000
@@ -1,4 +1,4 @@
-# $NetBSD: HDL_G,v 1.24.2.2 2012/03/11 01:52:20 mrg Exp $
+# $NetBSD: HDL_G,v 1.24.2.3 2012/04/29 23:04:38 mrg Exp $
 #
 #       HDL_G -- I-O DATA HDL-G Kernel
 #
@@ -112,10 +112,6 @@
 
 options 	SYSVMSG		# System V-like message queues
 options 	SYSVSEM		# System V-like semaphores
-#options 	SEMMNI=10	# number of semaphore identifiers
-#options 	SEMMNS=60	# number of semaphores in system
-#options 	SEMUME=10	# max number of undo entries per process
-#options 	SEMMNU=30	# number of undo structures in system
 options 	SYSVSHM		# System V-like memory sharing
 
 # Device options
--- a/sys/arch/evbarm/conf/IMX31LITE	Tue Apr 17 19:25:17 2012 +0000
+++ b/sys/arch/evbarm/conf/IMX31LITE	Sun Apr 29 23:04:36 2012 +0000
@@ -1,4 +1,4 @@
-#	$NetBSD: IMX31LITE,v 1.15.2.1 2012/02/18 07:31:47 mrg Exp $
+#	$NetBSD: IMX31LITE,v 1.15.2.2 2012/04/29 23:04:38 mrg Exp $
 #
 #	IMX31LITE -- Freescale IMX31LITE Evaluation Board Kernel
 #
@@ -97,10 +97,6 @@
 
 options 	SYSVMSG		# System V-like message queues
 options 	SYSVSEM		# System V-like semaphores
-#options 	SEMMNI=10	# number of semaphore identifiers
-#options 	SEMMNS=60	# number of semaphores in system
-#options 	SEMUME=10	# max number of undo entries per process
-#options 	SEMMNU=30	# number of undo structures in system
 options 	SYSVSHM		# System V-like memory sharing
 
 # Device options
--- a/sys/arch/evbarm/conf/INTEGRATOR	Tue Apr 17 19:25:17 2012 +0000
+++ b/sys/arch/evbarm/conf/INTEGRATOR	Sun Apr 29 23:04:36 2012 +0000
@@ -1,4 +1,4 @@
-#	$NetBSD: INTEGRATOR,v 1.63.2.1 2012/02/18 07:31:47 mrg Exp $
+#	$NetBSD: INTEGRATOR,v 1.63.2.2 2012/04/29 23:04:38 mrg Exp $
 #
 #	GENERIC -- ARM Integrator board Generic kernel
 #
@@ -98,10 +98,6 @@
 
 #options 	SYSVMSG		# System V-like message queues
 #options 	SYSVSEM		# System V-like semaphores
-#options 	SEMMNI=10	# number of semaphore identifiers
-#options 	SEMMNS=60	# number of semaphores in system
-#options 	SEMUME=10	# max number of undo entries per process
-#options 	SEMMNU=30	# number of undo structures in system
 #options 	SYSVSHM		# System V-like memory sharing
 
 # Device options
@@ -155,6 +151,7 @@
 # PL010 uart
 plcom0		at ifpga? offset 0x06000000 irq 1
 plcom1		at ifpga? offset 0x07000000 irq 2
+#options 	PLCOM_DEBUG
 
 # PL030 real time clock
 plrtc0		at ifpga? offset 0x05000000
--- a/sys/arch/evbarm/conf/IQ31244	Tue Apr 17 19:25:17 2012 +0000
+++ b/sys/arch/evbarm/conf/IQ31244	Sun Apr 29 23:04:36 2012 +0000
@@ -1,4 +1,4 @@
-#	$NetBSD: IQ31244,v 1.54.2.1 2012/02/18 07:31:47 mrg Exp $
+#	$NetBSD: IQ31244,v 1.54.2.2 2012/04/29 23:04:38 mrg Exp $
 #
 #	IQ31244 -- Intel IQ31244 Evaluation Board Kernel
 #
@@ -98,10 +98,6 @@
 
 options 	SYSVMSG		# System V-like message queues
 options 	SYSVSEM		# System V-like semaphores
-#options 	SEMMNI=10	# number of semaphore identifiers
-#options 	SEMMNS=60	# number of semaphores in system
-#options 	SEMUME=10	# max number of undo entries per process
-#options 	SEMMNU=30	# number of undo structures in system
 options 	SYSVSHM		# System V-like memory sharing
 
 # Device options
--- a/sys/arch/evbarm/conf/IQ80310	Tue Apr 17 19:25:17 2012 +0000
+++ b/sys/arch/evbarm/conf/IQ80310	Sun Apr 29 23:04:36 2012 +0000
@@ -1,4 +1,4 @@
-#	$NetBSD: IQ80310,v 1.73.2.1 2012/02/18 07:31:47 mrg Exp $
+#	$NetBSD: IQ80310,v 1.73.2.2 2012/04/29 23:04:38 mrg Exp $
 #
 #	IQ80310 -- Intel IQ80310 Evaluation Board Kernel
 #
@@ -98,10 +98,6 @@
 
 options 	SYSVMSG		# System V-like message queues
 options 	SYSVSEM		# System V-like semaphores
-#options 	SEMMNI=10	# number of semaphore identifiers
-#options 	SEMMNS=60	# number of semaphores in system
-#options 	SEMUME=10	# max number of undo entries per process
-#options 	SEMMNU=30	# number of undo structures in system
 options 	SYSVSHM		# System V-like memory sharing
 
 # Device options
--- a/sys/arch/evbarm/conf/IQ80321	Tue Apr 17 19:25:17 2012 +0000
+++ b/sys/arch/evbarm/conf/IQ80321	Sun Apr 29 23:04:36 2012 +0000
@@ -1,4 +1,4 @@
-#	$NetBSD: IQ80321,v 1.69.2.1 2012/02/18 07:31:47 mrg Exp $
+#	$NetBSD: IQ80321,v 1.69.2.2 2012/04/29 23:04:38 mrg Exp $
 #
 #	IQ80321 -- Intel IQ80321 Evaluation Board Kernel
 #
@@ -98,10 +98,6 @@
 
 options 	SYSVMSG		# System V-like message queues
 options 	SYSVSEM		# System V-like semaphores
-#options 	SEMMNI=10	# number of semaphore identifiers
-#options 	SEMMNS=60	# number of semaphores in system
-#options 	SEMUME=10	# max number of undo entries per process
-#options 	SEMMNU=30	# number of undo structures in system
 options 	SYSVSHM		# System V-like memory sharing
 
 # Device options
--- a/sys/arch/evbarm/conf/IXDP425	Tue Apr 17 19:25:17 2012 +0000
+++ b/sys/arch/evbarm/conf/IXDP425	Sun Apr 29 23:04:36 2012 +0000
@@ -1,4 +1,4 @@
-#	$NetBSD: IXDP425,v 1.34.2.1 2012/02/18 07:31:48 mrg Exp $
+#	$NetBSD: IXDP425,v 1.34.2.2 2012/04/29 23:04:38 mrg Exp $
 #
 #	IXDP425 -- Intel IXDP425/IXCDP1100 Development Platform
 #
@@ -102,10 +102,6 @@
 
 options 	SYSVMSG		# System V-like message queues
 options 	SYSVSEM		# System V-like semaphores
-#options 	SEMMNI=10	# number of semaphore identifiers
-#options 	SEMMNS=60	# number of semaphores in system
-#options 	SEMUME=10	# max number of undo entries per process
-#options 	SEMMNU=30	# number of undo structures in system
 options 	SYSVSHM		# System V-like memory sharing
 
 # Device options
--- a/sys/arch/evbarm/conf/IXM1200	Tue Apr 17 19:25:17 2012 +0000
+++ b/sys/arch/evbarm/conf/IXM1200	Sun Apr 29 23:04:36 2012 +0000
@@ -1,4 +1,4 @@
-#	$NetBSD: IXM1200,v 1.46.2.1 2012/02/18 07:31:48 mrg Exp $
+#	$NetBSD: IXM1200,v 1.46.2.2 2012/04/29 23:04:38 mrg Exp $
 #
 #	IXM1200 -- Intel IXM1200 Evaluation Board Kernel
 #
@@ -97,10 +97,6 @@
 
 options 	SYSVMSG		# System V-like message queues
 options 	SYSVSEM		# System V-like semaphores
-#options 	SEMMNI=10	# number of semaphore identifiers
-#options 	SEMMNS=60	# number of semaphores in system
-#options 	SEMUME=10	# max number of undo entries per process
-#options 	SEMMNU=30	# number of undo structures in system
 options 	SYSVSHM		# System V-like memory sharing
 
 # Device options
--- a/sys/arch/evbarm/conf/LUBBOCK	Tue Apr 17 19:25:17 2012 +0000
+++ b/sys/arch/evbarm/conf/LUBBOCK	Sun Apr 29 23:04:36 2012 +0000
@@ -96,10 +96,6 @@
 
 #options 	SYSVMSG		# System V-like message queues
 #options 	SYSVSEM		# System V-like semaphores
-#options 	SEMMNI=10	# number of semaphore identifiers
-#options 	SEMMNS=60	# number of semaphores in system
-#options 	SEMUME=10	# max number of undo entries per process
-#options 	SEMMNU=30	# number of undo structures in system
 #options 	SYSVSHM		# System V-like memory sharing
 
 # Device options
--- a/sys/arch/evbarm/conf/MMNET_GENERIC	Tue Apr 17 19:25:17 2012 +0000
+++ b/sys/arch/evbarm/conf/MMNET_GENERIC	Sun Apr 29 23:04:36 2012 +0000
@@ -1,4 +1,4 @@
-# $NetBSD: MMNET_GENERIC,v 1.2.2.2 2012/03/11 01:52:20 mrg Exp $
+# $NetBSD: MMNET_GENERIC,v 1.2.2.3 2012/04/29 23:04:38 mrg Exp $
 #
 # GENERIC machine description file
 #
@@ -22,7 +22,7 @@
 
 options 	INCLUDE_CONFIG_FILE	# embed config file in kernel binary
 
-#ident 		"GENERIC-$Revision: 1.2.2.2 $"
+#ident 		"GENERIC-$Revision: 1.2.2.3 $"
 
 maxusers	32		# estimated number of users
 
@@ -59,10 +59,6 @@
 
 options 	SYSVMSG		# System V-like message queues
 options 	SYSVSEM		# System V-like semaphores
-#options 	SEMMNI=10	# number of semaphore identifiers
-#options 	SEMMNS=60	# number of semaphores in system
-#options 	SEMUME=10	# max number of undo entries per process
-#options 	SEMMNU=30	# number of undo structures in system
 options 	SYSVSHM		# System V-like memory sharing
 
 #options 	USERCONF	# userconf(4) support
--- a/sys/arch/evbarm/conf/MPCSA_GENERIC	Tue Apr 17 19:25:17 2012 +0000
+++ b/sys/arch/evbarm/conf/MPCSA_GENERIC	Sun Apr 29 23:04:36 2012 +0000
@@ -1,4 +1,4 @@
-# $NetBSD: MPCSA_GENERIC,v 1.24.2.2 2012/03/11 01:52:20 mrg Exp $
+# $NetBSD: MPCSA_GENERIC,v 1.24.2.3 2012/04/29 23:04:38 mrg Exp $
 #
 # GENERIC machine description file
 #
@@ -22,7 +22,7 @@
 
 options 	INCLUDE_CONFIG_FILE	# embed config file in kernel binary
 
-#ident 		"GENERIC-$Revision: 1.24.2.2 $"
+#ident 		"GENERIC-$Revision: 1.24.2.3 $"
 
 maxusers	32		# estimated number of users
 
@@ -59,10 +59,6 @@
 
 options 	SYSVMSG		# System V-like message queues
 options 	SYSVSEM		# System V-like semaphores
-#options 	SEMMNI=10	# number of semaphore identifiers
-#options 	SEMMNS=60	# number of semaphores in system
-#options 	SEMUME=10	# max number of undo entries per process
-#options 	SEMMNU=30	# number of undo structures in system
 options 	SYSVSHM		# System V-like memory sharing
 
 #options 	USERCONF	# userconf(4) support
--- a/sys/arch/evbarm/conf/NAPPI	Tue Apr 17 19:25:17 2012 +0000
+++ b/sys/arch/evbarm/conf/NAPPI	Sun Apr 29 23:04:36 2012 +0000
@@ -1,4 +1,4 @@
-#	$NetBSD: NAPPI,v 1.42.2.1 2012/02/18 07:31:49 mrg Exp $
+#	$NetBSD: NAPPI,v 1.42.2.2 2012/04/29 23:04:38 mrg Exp $
 #
 #	NAPPI -- Netwise APlication Platform Board Kernel
 #
@@ -97,10 +97,6 @@
 
 options 	SYSVMSG		# System V-like message queues
 options 	SYSVSEM		# System V-like semaphores
-#options 	SEMMNI=10	# number of semaphore identifiers
-#options 	SEMMNS=60	# number of semaphores in system
-#options 	SEMUME=10	# max number of undo entries per process
-#options 	SEMMNU=30	# number of undo structures in system
 options 	SYSVSHM		# System V-like memory sharing
 
 # Console options.
--- a/sys/arch/evbarm/conf/NETWALKER	Tue Apr 17 19:25:17 2012 +0000
+++ b/sys/arch/evbarm/conf/NETWALKER	Sun Apr 29 23:04:36 2012 +0000
@@ -1,6 +1,6 @@
-#	$NetBSD: NETWALKER,v 1.6.2.1 2012/02/18 07:31:49 mrg Exp $
+#	$NetBSD: NETWALKER,v 1.6.2.2 2012/04/29 23:04:38 mrg Exp $
 #
-#	NETWALKER -- Sharp
+#	NETWALKER -- http://www.sharp.co.jp/netwalker/
 #
 
 include	"arch/evbarm/conf/std.netwalker"
@@ -17,7 +17,7 @@
 #options 	NTP		# NTP phase/frequency locked loop
 
 # CPU options
-options 	CPU_CORTEXA8	# Support the ARM11 core
+options 	CPU_CORTEXA8	# Support the ARM-v7a core
 options 	IMX51
 options 	PMAPCOUNTERS
 
@@ -103,10 +103,6 @@
 
 options 	SYSVMSG		# System V-like message queues
 options 	SYSVSEM		# System V-like semaphores
-#options 	SEMMNI=10	# number of semaphore identifiers
-#options 	SEMMNS=60	# number of semaphores in system
-#options 	SEMUME=10	# max number of undo entries per process
-#options 	SEMMNU=30	# number of undo structures in system
 options 	SYSVSHM		# System V-like memory sharing
 
 # Device options
@@ -181,6 +177,10 @@
 #imxuart2	at axi? addr 0x7000c000 irq 33
 options		IMXUARTCONSOLE
 
+# Clock Control
+imxccm0		at axi? addr 0x73fd4000
+options		IMX51_CKIL_FREQ=32768
+
 # Enhanced Periodic Interrupt Timer
 imxclock0	at axi? addr 0x73fac000 size 0x4000 irq 40
 imxclock1	at axi? addr 0x73fb0000 size 0x4000 irq 41
@@ -194,6 +194,14 @@
 imxgpio2	at axi? addr 0x73f8c000
 imxgpio3	at axi? addr 0x73f90000
 
+# SD/MMC
+sdhc0    	at axi? addr 0x70004000 irq 1	     # eSDHC1
+#sdhc1   	at axi? addr 0x70008000 irq 2	     # eSDHC2
+sdmmc*		at sdhc?
+ld*		at sdmmc?			# MMC/SD card
+#options 	SDHC_DEBUG
+#options 	SDMMC_DEBUG
+
 # USB
 imxusbc0  at axi?  addr 0x73f80000
 ehci0	  at imxusbc0	unit 0	irq 18 # OTG
@@ -247,6 +255,26 @@
 ugensa* at uhub? port ?
 ucom*	at ugensa?
 
+# IPUv3 LCD Controller
+ipu0		at axi?
+wsdisplay0	at wsemuldisplaydev? console ?
+wsdisplay*	at wsemuldisplaydev?
+#options	IPUV3_DEBUG=1
+#options	LCD_DEBUG
+options 	IMXIPUCONSOLE
+
+# various options for wscons - we try to look as much like a standard
+# sun console as possible
+options 	WSEMUL_VT100		# sun terminal emulation
+options 	WS_DEFAULT_FG=WSCOL_WHITE
+options 	WS_DEFAULT_BG=WSCOL_BLACK
+options		WS_KERNEL_FG=WSCOL_GREEN
+options		WS_KERNEL_BG=WSCOL_BLACK
+options 	WSDISPLAY_COMPAT_PCVT		# emulate some ioctls
+options 	WSDISPLAY_COMPAT_USL		# VT handling
+options 	WSDISPLAY_COMPAT_RAWKBD		# can get raw scancodes
+options 	WSDISPLAY_DEFAULTSCREENS=4
+
 # SCSI bus support
 scsibus* at scsi?
 
@@ -275,3 +303,4 @@
 
 # wscons pseudo-devices
 pseudo-device	wsmux			# mouse & keyboard multiplexor
+pseudo-device	wsfont
--- a/sys/arch/evbarm/conf/NETWALKER_MD	Tue Apr 17 19:25:17 2012 +0000
+++ b/sys/arch/evbarm/conf/NETWALKER_MD	Sun Apr 29 23:04:36 2012 +0000
@@ -1,6 +1,6 @@
-#       $NetBSD: NETWALKER_MD,v 1.2 2010/11/23 11:13:56 hannken Exp $
+#       $NetBSD: NETWALKER_MD,v 1.2.14.1 2012/04/29 23:04:38 mrg Exp $
 #
-#	M2ID -- i.MX51 evaluation board
+#	NETWALKER_MD -- Sharp Netwalker kernel with a ramdisk.
 #
 
 include "arch/evbarm/conf/NETWALKER"
@@ -11,5 +11,5 @@
 options 	MEMORY_DISK_RBFLAGS=RB_SINGLE	# boot in single-user mode
 
 # disk/mass storage pseudo-devices
-pseudo-device	md	
+pseudo-device	md
 
--- a/sys/arch/evbarm/conf/NSLU2	Tue Apr 17 19:25:17 2012 +0000
+++ b/sys/arch/evbarm/conf/NSLU2	Sun Apr 29 23:04:36 2012 +0000
@@ -1,4 +1,4 @@
-#	$NetBSD: NSLU2,v 1.21.2.1 2012/02/18 07:31:49 mrg Exp $
+#	$NetBSD: NSLU2,v 1.21.2.2 2012/04/29 23:04:38 mrg Exp $
 #
 #	Linksys NSLU2 "Slug" NAS Device
 #
@@ -101,10 +101,6 @@
 
 #options 	SYSVMSG		# System V-like message queues
 #options 	SYSVSEM		# System V-like semaphores
-#options 	SEMMNI=10	# number of semaphore identifiers
-#options 	SEMMNS=60	# number of semaphores in system
-#options 	SEMUME=10	# max number of undo entries per process
-#options 	SEMMNU=30	# number of undo structures in system
 #options 	SYSVSHM		# System V-like memory sharing
 
 # Device options
--- a/sys/arch/evbarm/conf/OSK5912	Tue Apr 17 19:25:17 2012 +0000
+++ b/sys/arch/evbarm/conf/OSK5912	Sun Apr 29 23:04:36 2012 +0000
@@ -94,10 +94,6 @@
 
 options 	SYSVMSG		# System V-like message queues
 options 	SYSVSEM		# System V-like semaphores
-#options 	SEMMNI=10	# number of semaphore identifiers
-#options 	SEMMNS=60	# number of semaphores in system
-#options 	SEMUME=10	# max number of undo entries per process
-#options 	SEMMNU=30	# number of undo structures in system
 options 	SYSVSHM		# System V-like memory sharing
 
 # Device options
--- a/sys/arch/evbarm/conf/OVERO	Tue Apr 17 19:25:17 2012 +0000
+++ b/sys/arch/evbarm/conf/OVERO	Sun Apr 29 23:04:36 2012 +0000
@@ -1,5 +1,5 @@
 #
-#	$NetBSD: OVERO,v 1.10.2.2 2012/03/11 01:52:20 mrg Exp $
+#	$NetBSD: OVERO,v 1.10.2.3 2012/04/29 23:04:38 mrg Exp $
 #
 #	OVERO -- Gumstix. Inc. Overo platforms kernel
 #
@@ -120,10 +120,6 @@
 
 #options 	SYSVMSG		# System V-like message queues
 #options 	SYSVSEM		# System V-like semaphores
-#options 	SEMMNI=10	# number of semaphore identifiers
-#options 	SEMMNS=60	# number of semaphores in system
-#options 	SEMUME=10	# max number of undo entries per process
-#options 	SEMMNU=30	# number of undo structures in system
 #options 	SYSVSHM		# System V-like memory sharing
 
 # Device options
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/sys/arch/evbarm/conf/README.evbarm	Sun Apr 29 23:04:36 2012 +0000
@@ -0,0 +1,47 @@
+$NetBSD: README.evbarm,v 1.1.4.2 2012/04/29 23:04:38 mrg Exp $
+
+config		date		boards
+-------------------------------------------------------------------------------
+ADI_BRH		2003/01/25	ADI Eng. Big Read Head i80200 eval board
+ARMADILLO210	2006/02/06	Atmark Techno Armadillo-210
+ARMADILLO9	2005/11/13	Atmark Techno Armadillo-9
+BEAGLEBOARD	2008/10/22	TI OMAP3530 BeagleBoard
+CP3100		2006/11/08	Certance IOP321 CP-3100
+DEVKIT8000	2010/09/08	Embest OMAP3530 DevKit8000 eval Kit 
+DNS323		2010/10/02	D-Link DNS-323 Marvell SoC based NAS
+GEMINI		2008/10/24	Cortina Systems SL3516 eval board
+GUMSTIX		2006/10/16	Gumstix Inc. PXA255/270 based boards
+HDL_G		2006/04/16	I-O DATA HDL-G Giga LANDISK
+HPT5325		2012/03/31	HP t5325 Thin Client
+IGEPV2		2010/06/16	IGEPv2 OMAP3530 eval board
+IMX31LITE	2008/04/27	Freescale i.M31 DEV LITE KIT
+INTEGRATOR	2001/10/27	ARM Integrator board
+IQ31244		2003/05/14	Intel IQ31244 reference board
+IQ80310		2001/09/05	Intel IQ80310 eval board
+IQ80321		2002/03/27	Intel IQ321 eval board
+IXDP425		2003/04/08	Intel IXDP425/IXCDP1100 development platform
+IXM1200		2002/07/15	Intel IMX1200 eval board
+KUROBOX_PRO	2010/10/02	Kuroutoshikou KURO-BOX/PRO
+LUBBOCK		2003/06/18	Intel Lubbock DBPXA250 board
+MARVELL_NAS	2010/10/02	Generic Marvell SoC based NAS
+MINI2440	2012/01/30	FrendlyARM Mini2440 S3C2440 SoC board
+MMNET_GENERIC	2011/11/04	Propox MMnet1002 board
+MPCSA_GENERIC	2008/07/03	MPCSA Atmel AT91RM9200 based board
+MV2120		2011/07/20	HP Media Vault MV2011 Marvell Orion board
+NAPPI		2002/07/15	Netwise APlication Platform Board
+NETWALKER	2010/11/13	Sharp NetWalker
+NSLU2		2006/02/28	Linksys NSLU2 (a.k.a. "Slug")
+OSK5912		2007/01/06	TI OMAP 5912 OSK board
+OVERO		2010/07/10	Gumstix Inc. OMAP3530 based Overo boards
+SHEEVAPLUG	2010/10/02	Marvell SheevaPlug
+SMDK2410	2003/07/31	Samsung SMDK2410 S3C2410 eval board
+SMDK2800	2002/11/20	Samsung SMDK2800 S3C2800 eval board
+TEAMASA_NPWR	2002/02/07	Team ASA Npwr IOP310 based server appliance
+TEAMASA_NPWR_FC	2003/12/24	Team ASA NPWR-FC i80321 server appliance
+TISDP2420	2008/04/27	TI OMAP 2420 eval board
+TISDP2430	2008/04/27	TI OMAP 2430 eval board
+TOASTER		2005/08/14	NetBSD/toaster based on TS-7200
+TS7200		2004/12/23	Technologic Systems TS-7200 board
+TWINTAIL	2005/02/26	Genetec corp. "Twintail" PXA255 eval board
+VIPER		2005/06/06	Arcom Viper PXA255 ARM board
+ZAO425		2003/05/23	NOVATEC NTNP425B "ZAO425" IXP425 eval board
--- a/sys/arch/evbarm/conf/SMDK2410	Tue Apr 17 19:25:17 2012 +0000
+++ b/sys/arch/evbarm/conf/SMDK2410	Sun Apr 29 23:04:36 2012 +0000
@@ -1,4 +1,4 @@
-#	$NetBSD: SMDK2410,v 1.45.2.1 2012/02/18 07:31:49 mrg Exp $
+#	$NetBSD: SMDK2410,v 1.45.2.2 2012/04/29 23:04:38 mrg Exp $
 #
 #	SMDK2410 -- Samsung's S3C2410 evaluation board.
 #
@@ -116,10 +116,6 @@
 
 options 	SYSVMSG		# System V-like message queues
 options 	SYSVSEM		# System V-like semaphores
-#options 	SEMMNI=10	# number of semaphore identifiers
-#options 	SEMMNS=60	# number of semaphores in system
-#options 	SEMUME=10	# max number of undo entries per process
-#options 	SEMMNU=30	# number of undo structures in system
 options 	SYSVSHM		# System V-like memory sharing
 
 # Miscellaneous kernel options
--- a/sys/arch/evbarm/conf/SMDK2800	Tue Apr 17 19:25:17 2012 +0000
+++ b/sys/arch/evbarm/conf/SMDK2800	Sun Apr 29 23:04:36 2012 +0000
@@ -1,4 +1,4 @@
-#	$NetBSD: SMDK2800,v 1.45.2.1 2012/02/18 07:31:49 mrg Exp $
+#	$NetBSD: SMDK2800,v 1.45.2.2 2012/04/29 23:04:38 mrg Exp $
 #
 #	SMDK2800 -- Samsung's S3C2800 evaluation board.
 #
@@ -105,10 +105,6 @@
 
 #options 	SYSVMSG		# System V-like message queues
 #options 	SYSVSEM		# System V-like semaphores
-#options 	SEMMNI=10	# number of semaphore identifiers
-#options 	SEMMNS=60	# number of semaphores in system
-#options 	SEMUME=10	# max number of undo entries per process
-#options 	SEMMNU=30	# number of undo structures in system
 #options 	SYSVSHM		# System V-like memory sharing
 
 # Miscellaneous kernel options
--- a/sys/arch/evbarm/conf/TEAMASA_NPWR	Tue Apr 17 19:25:17 2012 +0000
+++ b/sys/arch/evbarm/conf/TEAMASA_NPWR	Sun Apr 29 23:04:36 2012 +0000
@@ -1,4 +1,4 @@
-#	$NetBSD: TEAMASA_NPWR,v 1.70.2.1 2012/02/18 07:31:49 mrg Exp $
+#	$NetBSD: TEAMASA_NPWR,v 1.70.2.2 2012/04/29 23:04:38 mrg Exp $
 #
 #	TEAMASA_NPWR -- Team ASA, Inc. Npwr -- XScale/IOP310-based
 #	server appliance.
@@ -101,10 +101,6 @@
 
 options 	SYSVMSG		# System V-like message queues
 options 	SYSVSEM		# System V-like semaphores
-#options 	SEMMNI=10	# number of semaphore identifiers
-#options 	SEMMNS=60	# number of semaphores in system
-#options 	SEMUME=10	# max number of undo entries per process
-#options 	SEMMNU=30	# number of undo structures in system
 options 	SYSVSHM		# System V-like memory sharing
 
 # Device options
--- a/sys/arch/evbarm/conf/TEAMASA_NPWR_FC	Tue Apr 17 19:25:17 2012 +0000
+++ b/sys/arch/evbarm/conf/TEAMASA_NPWR_FC	Sun Apr 29 23:04:36 2012 +0000
@@ -1,4 +1,4 @@
-#	$NetBSD: TEAMASA_NPWR_FC,v 1.34.2.1 2012/02/18 07:31:50 mrg Exp $
+#	$NetBSD: TEAMASA_NPWR_FC,v 1.34.2.2 2012/04/29 23:04:39 mrg Exp $
 #
 #	TeamASA NPWR-FC, i80321-based SBC
 #
@@ -99,10 +99,6 @@
 
 options 	SYSVMSG		# System V-like message queues
 options 	SYSVSEM		# System V-like semaphores
-#options 	SEMMNI=10	# number of semaphore identifiers
-#options 	SEMMNS=60	# number of semaphores in system
-#options 	SEMUME=10	# max number of undo entries per process
-#options 	SEMMNU=30	# number of undo structures in system
 options 	SYSVSHM		# System V-like memory sharing
 
 # Device options
--- a/sys/arch/evbarm/conf/TISDP2420	Tue Apr 17 19:25:17 2012 +0000
+++ b/sys/arch/evbarm/conf/TISDP2420	Sun Apr 29 23:04:36 2012 +0000
@@ -1,5 +1,5 @@
 #
-#	$NetBSD: TISDP2420,v 1.18.2.1 2012/02/18 07:31:50 mrg Exp $
+#	$NetBSD: TISDP2420,v 1.18.2.2 2012/04/29 23:04:39 mrg Exp $
 #
 #	TISDP2420 -- TI OMAP 2420 Eval Board Kernel
 #
@@ -106,10 +106,6 @@
 
 options 	SYSVMSG		# System V-like message queues
 options 	SYSVSEM		# System V-like semaphores
-#options 	SEMMNI=10	# number of semaphore identifiers
-#options 	SEMMNS=60	# number of semaphores in system
-#options 	SEMUME=10	# max number of undo entries per process
-#options 	SEMMNU=30	# number of undo structures in system
 options 	SYSVSHM		# System V-like memory sharing
 
 # Device options
--- a/sys/arch/evbarm/conf/TISDP2430	Tue Apr 17 19:25:17 2012 +0000
+++ b/sys/arch/evbarm/conf/TISDP2430	Sun Apr 29 23:04:36 2012 +0000
@@ -1,5 +1,5 @@
 #
-#	$NetBSD: TISDP2430,v 1.18.2.1 2012/02/18 07:31:50 mrg Exp $
+#	$NetBSD: TISDP2430,v 1.18.2.2 2012/04/29 23:04:39 mrg Exp $
 #
 #	TISDP2430 -- TI OMAP 2430 Eval Board Kernel
 #
@@ -105,10 +105,6 @@
 
 options 	SYSVMSG		# System V-like message queues
 options 	SYSVSEM		# System V-like semaphores
-#options 	SEMMNI=10	# number of semaphore identifiers
-#options 	SEMMNS=60	# number of semaphores in system
-#options 	SEMUME=10	# max number of undo entries per process
-#options 	SEMMNU=30	# number of undo structures in system
 options 	SYSVSHM		# System V-like memory sharing
 
 # Device options
--- a/sys/arch/evbarm/conf/TS7200	Tue Apr 17 19:25:17 2012 +0000
+++ b/sys/arch/evbarm/conf/TS7200	Sun Apr 29 23:04:36 2012 +0000
@@ -1,4 +1,4 @@
-#	$NetBSD: TS7200,v 1.46.2.1 2012/02/18 07:31:50 mrg Exp $
+#	$NetBSD: TS7200,v 1.46.2.2 2012/04/29 23:04:39 mrg Exp $
 #
 #	TS7200 - Kernel for Technologic Systems TS7200 ARM hardware
 #
@@ -103,10 +103,6 @@
 
 options 	SYSVMSG		# System V-like message queues
 options 	SYSVSEM		# System V-like semaphores
-options 	SEMMNI=10	# number of semaphore identifiers
-options 	SEMMNS=60	# number of semaphores in system
-options 	SEMUME=10	# max number of undo entries per process
-options 	SEMMNU=30	# number of undo structures in system
 options 	SYSVSHM		# System V-like memory sharing
 
 # Device options
--- a/sys/arch/evbarm/conf/TWINTAIL	Tue Apr 17 19:25:17 2012 +0000
+++ b/sys/arch/evbarm/conf/TWINTAIL	Sun Apr 29 23:04:36 2012 +0000
@@ -1,4 +1,4 @@
-#	$NetBSD: TWINTAIL,v 1.47.2.2 2012/04/05 21:33:13 mrg Exp $
+#	$NetBSD: TWINTAIL,v 1.47.2.3 2012/04/29 23:04:39 mrg Exp $
 #
 #	TWINTAIL -- Genetec corp. G4255EB-X002 Evaluation Board Kernel
 #
@@ -106,10 +106,6 @@
 
 #options 	SYSVMSG		# System V-like message queues
 #options 	SYSVSEM		# System V-like semaphores
-#options 	SEMMNI=10	# number of semaphore identifiers
-#options 	SEMMNS=60	# number of semaphores in system
-#options 	SEMUME=10	# max number of undo entries per process
-#options 	SEMMNU=30	# number of undo structures in system
 #options 	SYSVSHM		# System V-like memory sharing
 
 # Device options
--- a/sys/arch/evbarm/conf/VIPER	Tue Apr 17 19:25:17 2012 +0000
+++ b/sys/arch/evbarm/conf/VIPER	Sun Apr 29 23:04:36 2012 +0000
@@ -1,4 +1,4 @@
-#	$NetBSD: VIPER,v 1.23 2011/11/22 21:25:10 tls Exp $
+#	$NetBSD: VIPER,v 1.23.2.1 2012/04/29 23:04:39 mrg Exp $
 #
 #	Arcom Viper
 #
@@ -93,10 +93,6 @@
 
 options 	SYSVMSG		# System V-like message queues
 options 	SYSVSEM		# System V-like semaphores
-options 	SEMMNI=10	# number of semaphore identifiers
-options 	SEMMNS=60	# number of semaphores in system
-options 	SEMUME=10	# max number of undo entries per process
-options 	SEMMNU=30	# number of undo structures in system
 options 	SYSVSHM		# System V-like memory sharing
 
 # Device options
--- a/sys/arch/evbarm/conf/ZAO425	Tue Apr 17 19:25:17 2012 +0000
+++ b/sys/arch/evbarm/conf/ZAO425	Sun Apr 29 23:04:36 2012 +0000
@@ -1,4 +1,4 @@
-#	$NetBSD: ZAO425,v 1.42.2.1 2012/02/18 07:31:50 mrg Exp $
+#	$NetBSD: ZAO425,v 1.42.2.2 2012/04/29 23:04:39 mrg Exp $
 #
 #	ZAO425 -- Intel IXP425
 #
@@ -102,10 +102,6 @@
 
 options 	SYSVMSG		# System V-like message queues
 options 	SYSVSEM		# System V-like semaphores
-#options 	SEMMNI=10	# number of semaphore identifiers
-#options 	SEMMNS=60	# number of semaphores in system
-#options 	SEMUME=10	# max number of undo entries per process
-#options 	SEMMNU=30	# number of undo structures in system
 options 	SYSVSHM		# System V-like memory sharing
 
 # Device options
--- a/sys/arch/evbarm/conf/files.netwalker	Tue Apr 17 19:25:17 2012 +0000
+++ b/sys/arch/evbarm/conf/files.netwalker	Sun Apr 29 23:04:36 2012 +0000
@@ -1,6 +1,6 @@
-#	$NetBSD: files.netwalker,v 1.2 2010/11/30 13:07:29 bsh Exp $
+#	$NetBSD: files.netwalker,v 1.2.14.1 2012/04/29 23:04:39 mrg Exp $
 #
-# Sharp
+# Sharp Netwalker
 #
 
 file	arch/evbarm/netwalker/netwalker_machdep.c
@@ -14,3 +14,8 @@
 device imxusbc_axi
 attach imxusbc at axi with imxusbc_axi
 file   arch/evbarm/netwalker/netwalker_usb.c	imxusbc_axi
+
+# LCD controller
+attach	ipu at axi with lcd_netwalker
+file	arch/evbarm/netwalker/netwalker_lcd.c	lcd_netwalker
+defflag	opt_netwalker_lcd.h			LCD_DEBUG
--- a/sys/arch/evbarm/conf/std.netwalker	Tue Apr 17 19:25:17 2012 +0000
+++ b/sys/arch/evbarm/conf/std.netwalker	Sun Apr 29 23:04:36 2012 +0000
@@ -1,4 +1,4 @@
-#	$NetBSD: std.netwalker,v 1.1 2010/11/13 07:31:32 bsh Exp $
+#	$NetBSD: std.netwalker,v 1.1.16.1 2012/04/29 23:04:39 mrg Exp $
 #
 # standard NetBSD/evbarm options for Sharp NetWalker
 
@@ -14,12 +14,12 @@
 options 	EXEC_ELF32
 options 	EXEC_SCRIPT
 options 	KERNEL_BASE_EXT=0xc0000000
-makeoptions	CPUFLAGS="-mcpu=arm1136j-s"
+makeoptions	CPUFLAGS="-mcpu=cortex-a8"
 
 # To support easy transit to ../arch/arm/arm32
 options 	ARM32
 options 	CORTEX_PMC
-options 	CORTEX_CCNT_HZ=720000000
+options 	CORTEX_PMC_CCNT_HZ=800000000
 
 makeoptions	LOADADDRESS="0x90100000"
 makeoptions	BOARDTYPE="netwalker"
--- a/sys/arch/evbarm/dev/plcom.c	Tue Apr 17 19:25:17 2012 +0000
+++ b/sys/arch/evbarm/dev/plcom.c	Sun Apr 29 23:04:36 2012 +0000
@@ -1,4 +1,4 @@
-/*	$NetBSD: plcom.c,v 1.32.8.1 2012/02/18 07:31:50 mrg Exp $	*/
+/*	$NetBSD: plcom.c,v 1.32.8.2 2012/04/29 23:04:39 mrg Exp $	*/
 
 /*-
  * Copyright (c) 2001 ARM Ltd
@@ -94,7 +94,7 @@
  */
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: plcom.c,v 1.32.8.1 2012/02/18 07:31:50 mrg Exp $");
+__KERNEL_RCSID(0, "$NetBSD: plcom.c,v 1.32.8.2 2012/04/29 23:04:39 mrg Exp $");
 
 #include "opt_plcom.h"
 #include "opt_ddb.h"
@@ -280,9 +280,9 @@
 #ifdef PLCOM_DEBUG
 int	plcom_debug = 0;
 
-void plcomstatus (struct plcom_softc *, char *);
+void plcomstatus (struct plcom_softc *, const char *);
 void
-plcomstatus(struct plcom_softc *sc, char *str)
+plcomstatus(struct plcom_softc *sc, const char *str)
 {
 	struct tty *tp = sc->sc_tty;
 
@@ -304,6 +304,7 @@
 }
 #endif
 
+/* XXX this function is not used? */
 int
 plcomprobe1(bus_space_tag_t iot, bus_space_handle_t ioh)
 {
--- a/sys/arch/evbarm/dev/plcomreg.h	Tue Apr 17 19:25:17 2012 +0000
+++ b/sys/arch/evbarm/dev/plcomreg.h	Sun Apr 29 23:04:36 2012 +0000
@@ -1,4 +1,4 @@
-/*	$NetBSD: plcomreg.h,v 1.1 2001/10/27 16:22:06 rearnsha Exp $	*/
+/*	$NetBSD: plcomreg.h,v 1.1.164.1 2012/04/29 23:04:39 mrg Exp $	*/
 
 /*-
  * Copyright (c) 2001 ARM Ltd
@@ -34,14 +34,14 @@
 #define	PLCOM_TOLERANCE	30	/* baud rate tolerance, in 0.1% units */
 
 /* control register */
-#define CR_LBE		0x80	/* Loopback enable */
-#define CR_RTIE		0x40	/* Receive timeout interrupt enable */
-#define CR_TIE		0x20	/* Transmit interrupt enable */
-#define CR_RIE		0x10	/* Receive interrrupt enable */
-#define CR_MSIE		0x08	/* Modem status interrupt enable */
-#define CR_SIRLP	0x04	/* IrDA SIR Low power mode */
-#define CR_SIREN	0x02	/* SIR Enable */
-#define CR_UARTEN	0x01	/* Uart enable */
+#define	CR_LBE		0x80	/* Loopback enable */
+#define	CR_RTIE		0x40	/* Receive timeout interrupt enable */
+#define	CR_TIE		0x20	/* Transmit interrupt enable */
+#define	CR_RIE		0x10	/* Receive interrrupt enable */
+#define	CR_MSIE		0x08	/* Modem status interrupt enable */
+#define	CR_SIRLP	0x04	/* IrDA SIR Low power mode */
+#define	CR_SIREN	0x02	/* SIR Enable */
+#define	CR_UARTEN	0x01	/* Uart enable */
 
 /* interrupt identification register */
 #define	IIR_IMASK	0x0f
@@ -51,15 +51,15 @@
 #define	IIR_MIS		0x01
 
 /* line control register */
-#define LCR_WLEN	0x60	/* Mask of size bits */
+#define	LCR_WLEN	0x60	/* Mask of size bits */
 #define	LCR_8BITS	0x60	/* 8 bits per serial word */
 #define	LCR_7BITS	0x40	/* 7 bits */
 #define	LCR_6BITS	0x20	/* 6 bits */
 #define	LCR_5BITS	0x00	/* 5 bits */
-#define LCR_FEN		0x10	/* FIFO enable */
+#define	LCR_FEN		0x10	/* FIFO enable */
 #define	LCR_STP2	0x08	/* 2 stop bits per serial word */
-#define LCR_EPS		0x04	/* Even parity select */
-#define LCR_PEN		0x02	/* Parity enable */
+#define	LCR_EPS		0x04	/* Even parity select */
+#define	LCR_PEN		0x02	/* Parity enable */
 #define	LCR_PEVEN	(LCR_PEN | LCR_EPS)
 #define	LCR_PODD	LCR_PEN
 #define	LCR_PNONE	0x00	/* No parity */
@@ -71,10 +71,10 @@
 
 /* receive status register */
 
-#define RSR_OE		0x08	/* Overrun Error */
-#define RSR_BE		0x04	/* Break */
-#define RSR_PE		0x02	/* Parity Error */
-#define RSR_FE		0x01	/* Framing Error */
+#define	RSR_OE		0x08	/* Overrun Error */
+#define	RSR_BE		0x04	/* Break */
+#define	RSR_PE		0x02	/* Parity Error */
+#define	RSR_FE		0x01	/* Framing Error */
 
 /* flag register */
 #define	FR_TXFE		0x80	/* Transmit fifo empty */
@@ -93,17 +93,17 @@
 #define	MSR_CTS		FR_CTS
 
 /* Register offsets */
-#define plcom_dr	0x00
-#define plcom_rsr	0x04
-#define plcom_ecr	0x04
-#define plcom_lcr	0x08
-#define plcom_dlbh	0x0c
-#define plcom_dlbl	0x10
-#define plcom_cr	0x14
-#define plcom_fr	0x18
-#define plcom_iir	0x1c
-#define plcom_icr	0x1c
-#define plcom_ilpr	0x20
+#define	plcom_dr	0x00
+#define	plcom_rsr	0x04
+#define	plcom_ecr	0x04
+#define	plcom_lcr	0x08
+#define	plcom_dlbh	0x0c
+#define	plcom_dlbl	0x10
+#define	plcom_cr	0x14
+#define	plcom_fr	0x18
+#define	plcom_iir	0x1c
+#define	plcom_icr	0x1c
+#define	plcom_ilpr	0x20
 
 /* IFPGA specific */
-#define PLCOM_UART_SIZE	0x24
+#define	PLCOM_UART_SIZE	0x24
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/sys/arch/evbarm/netwalker/netwalker_lcd.c	Sun Apr 29 23:04:36 2012 +0000
@@ -0,0 +1,268 @@
+/*	$NetBSD: netwalker_lcd.c,v 1.1.2.2 2012/04/29 23:04:39 mrg Exp $	*/
+
+/*-
+ * Copyright (c) 2011, 2012 Genetec corp. All rights reserved.
+ * Written by Hashimoto Kenichi for Genetec corp.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/conf.h>
+#include <sys/uio.h>
+#include <sys/malloc.h>
+#include <sys/device.h>
+
+#include <dev/cons.h>
+#include <dev/wscons/wsconsio.h>
+#include <dev/wscons/wsdisplayvar.h>
+#include <dev/wscons/wscons_callbacks.h>
+
+#include <sys/bus.h>
+#include <arm/imx/imx51var.h>
+#include <arm/imx/imx51reg.h>
+#include <arm/imx/imx51_ipuv3var.h>
+#include <arm/imx/imx51_ipuv3reg.h>
+#include <arm/imx/imx51_iomuxreg.h>
+#include <arm/imx/imxgpiovar.h>
+
+#include "opt_imx51_ipuv3.h"
+#include "opt_netwalker_lcd.h"
+
+#include "wsdisplay.h"
+#include "ioconf.h"
+
+int lcd_match(device_t, cfdata_t, void *);
+void lcd_attach(device_t, device_t, void *);
+
+void netwalker_cnattach(void);
+
+#if NWSDISPLAY > 0
+#else
+#ifdef LCD_DEBUG
+static void draw_test_pattern(struct imx51_ipuv3_softc *,
+    struct imx51_ipuv3_screen *);
+#endif
+
+/*
+ * Interface to LCD framebuffer without wscons
+ */
+extern struct cfdriver ipu_cd;
+
+dev_type_open(lcdopen);
+dev_type_close(lcdclose);
+dev_type_ioctl(lcdioctl);
+dev_type_mmap(lcdmmap);
+const struct cdevsw ipu_cdevsw = {
+	lcdopen, lcdclose, noread, nowrite, lcdioctl,
+	nostop, notty, nopoll, lcdmmap, nokqfilter, D_TTY
+};
+
+#endif
+
+CFATTACH_DECL_NEW(lcd_netwalker, sizeof (struct imx51_ipuv3_softc),
+    lcd_match, lcd_attach, NULL, NULL);
+
+int
+lcd_match( device_t parent, cfdata_t cf, void *aux )
+{
+	return 1;
+}
+
+/* Sharp's LCD */
+static const struct lcd_panel_geometry sharp_panel =
+{
+	.panel_width = 1024,	/* Width */
+	.panel_height = 600,	/* Height */
+
+	.pixel_clk = 30076000,
+
+	.hsync_width = 8,
+	.left  = 20,
+	.right = 20,
+
+	.vsync_width = 4,
+	.upper = 2,
+	.lower = 2,
+
+	.panel_info = 0,
+};
+
+#define PANEL	sharp_panel
+
+void lcd_attach( device_t parent, device_t self, void *aux )
+{
+	struct imx51_ipuv3_softc *sc = device_private(self);
+	struct axi_attach_args *axia = aux;
+	bus_space_tag_t iot = axia->aa_iot;
+
+	sc->dev = self;
+
+#if (NWSDISPLAY > 0) && defined(IMXIPUCONSOLE)
+	netwalker_cnattach();
+#endif
+
+#if 0
+	/* IOMUX registers are already set correctly for LCD display */
+	iomux_mux_config(iomux_ipuv3_config);
+#endif
+
+	/* XXX move this to imx51_ipuv3.c */
+	{
+		bus_space_handle_t mipi_ioh;
+		uint32_t reg;
+
+		if (bus_space_map(iot, 0x83fdc000, 0x1000, 0, &mipi_ioh))
+			aprint_error_dev(self, "can't map MIPI HSC");
+		else {
+			bus_space_write_4(iot, mipi_ioh, 0x000, 0xf00);
+
+			reg = bus_space_read_4(iot, mipi_ioh, 0x800);
+			bus_space_write_4(iot, mipi_ioh, 0x800, reg | 0x0ff);
+
+			reg = bus_space_read_4(iot, mipi_ioh, 0x800);
+			bus_space_write_4(iot, mipi_ioh, 0x800, reg | 0x10000);
+		}
+	}
+
+	/* LCD power on */
+	gpio_set_direction(GPIO_NO(4, 9), GPIO_DIR_OUT);
+	gpio_set_direction(GPIO_NO(4, 10), GPIO_DIR_OUT);
+	gpio_set_direction(GPIO_NO(3, 3), GPIO_DIR_OUT);
+
+	gpio_data_write(GPIO_NO(3, 3), 1);
+	gpio_data_write(GPIO_NO(4, 9), 1);
+	delay(180 * 1000);
+	gpio_data_write(GPIO_NO(4, 10), 1);
+
+	/* pwm pin (100%) */
+	gpio_set_direction(GPIO_NO(1, 2), GPIO_DIR_OUT);
+	gpio_data_write(GPIO_NO(1, 2), 1);
+
+	gpio_set_direction(GPIO_NO(2, 13), GPIO_DIR_OUT);
+	gpio_data_write(GPIO_NO(2, 13), 1);
+
+	imx51_ipuv3_attach_sub(sc, aux, &PANEL);
+
+#if NWSDISPLAY == 0
+	{
+		struct imx51_ipuv3_screen *screen;
+		int error;
+
+		error = imx51_ipuv3_new_screen(sc, 16, &screen);
+#ifdef LCD_DEBUG
+		draw_test_pattern(sc, screen);
+#endif
+		if (error == 0) {
+			sc->active = screen;
+			imx51_ipuv3_start_dma(sc, screen);
+		}
+	}
+#endif
+}
+
+#if NWSDISPLAY > 0
+void
+netwalker_cnattach(void)
+{
+	imx51_ipuv3_cnattach(&PANEL);
+	return;
+}
+#else
+
+int
+lcdopen(dev_t dev, int oflags, int devtype, struct lwp *l)
+{
+	return 0;
+}
+
+int
+lcdclose(dev_t dev, int fflag, int devtype, struct lwp *l)
+{
+	return 0;
+}
+
+paddr_t
+lcdmmap(dev_t dev, off_t offset, int size)
+{
+	struct imx51_ipuv3_softc *sc =
+	    device_lookup_private(&ipu_cd, minor(dev));
+	struct imx51_ipuv3_screen *scr = sc->active;
+
+	return bus_dmamem_mmap(sc->dma_tag, scr->segs, scr->nsegs,
+	    offset, 0, BUS_DMA_WAITOK|BUS_DMA_COHERENT);
+}
+
+int
+lcdioctl(dev_t dev, u_long cmd, void *data,
+    int fflag, struct lwp *l)
+{
+	return EOPNOTSUPP;
+}
+
+#ifdef LCD_DEBUG
+static void
+draw_test_pattern(struct imx51_ipuv3_softc *sc,
+    struct imx51_ipuv3_screen *scr)
+{
+	int x, y;
+	uint16_t color, *line;
+	char *buf = (char *)(scr->buf_va);
+
+	printf("%s: buf_va %p, size 0x%x\n", __func__, buf,
+	       (uint)scr->buf_size);
+	printf("%s: panel %d x %d\n", __func__,
+	    sc->geometry->panel_width,
+	    sc->geometry->panel_height);
+#define	rgb(r,g,b)	(((r)<<11) | ((g)<<5) | (b))
+
+	for (y=0; y < sc->geometry->panel_height; ++y) {
+		line = (uint16_t *)(buf + scr->stride * y);
+
+		for (x=0; x < sc->geometry->panel_width; ++x) {
+			switch (((x/30) + (y/10)) % 8) {
+			default:
+			case 0: color = rgb(0x00, 0x00, 0x00); break;
+			case 1: color = rgb(0x00, 0x00, 0x1f); break;
+			case 2: color = rgb(0x00, 0x3f, 0x00); break;
+			case 3: color = rgb(0x00, 0x3f, 0x1f); break;
+			case 4: color = rgb(0x1f, 0x00, 0x00); break;
+			case 5: color = rgb(0x1f, 0x00, 0x1f); break;
+			case 6: color = rgb(0x1f, 0x3f, 0x00); break;
+			case 7: color = rgb(0x1f, 0x3f, 0x1f); break;
+			}
+
+			line[x] = color;
+		}
+	}
+
+	for (x=0; x < MIN(sc->geometry->panel_height,
+		sc->geometry->panel_width); ++x) {
+		line = (uint16_t *)(buf + scr->stride * x);
+		line[x] = rgb(0x1f, 0x3f, 0x1f);
+	}
+}
+#endif
+
+#endif /* NWSDISPLAY > 0 */
+
+
--- a/sys/arch/evbarm/netwalker/netwalker_machdep.c	Tue Apr 17 19:25:17 2012 +0000
+++ b/sys/arch/evbarm/netwalker/netwalker_machdep.c	Sun Apr 29 23:04:36 2012 +0000
@@ -1,4 +1,4 @@
-/*	$NetBSD: netwalker_machdep.c,v 1.5 2011/07/01 20:42:37 dyoung Exp $	*/
+/*	$NetBSD: netwalker_machdep.c,v 1.5.6.1 2012/04/29 23:04:39 mrg Exp $	*/
 
 /*
  * Copyright (c) 2002, 2003, 2005, 2010  Genetec Corporation. 
@@ -102,7 +102,7 @@
  */
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: netwalker_machdep.c,v 1.5 2011/07/01 20:42:37 dyoung Exp $");
+__KERNEL_RCSID(0, "$NetBSD: netwalker_machdep.c,v 1.5.6.1 2012/04/29 23:04:39 mrg Exp $");
 
 #include "opt_ddb.h"
 #include "opt_kgdb.h"
@@ -922,49 +922,264 @@
 }
 
 struct iomux_setup {
-	size_t  	pad_ctl_reg;
-	uint32_t	pad_ctl_val;
-	size_t  	mux_ctl_reg;
-	uint32_t	mux_ctl_val;
+	/* iomux registers are 32-bit wide, but upper 16 bits are not
+	 * used. */
+	uint16_t	reg;
+	uint16_t	val;
 };
 
-#define	IOMUX_DATA(padname, mux, pad)	\
-	IOMUX_DATA2(__CONCAT(IOMUXC_SW_MUX_CTL_PAD_,padname), mux, \
-		    __CONCAT(IOMUXC_SW_PAD_CTL_PAD_,padname), pad)
-		    
-	
-#define	IOMUX_DATA2(muxreg, muxval, padreg, padval)	\
-	{						\
-		.pad_ctl_reg = (padreg),		\
-		.pad_ctl_val = (padval),		\
-		.mux_ctl_reg = (muxreg),		\
-		.mux_ctl_val = (muxval)			\
+#define	IOMUX_M(padname, mux)		\
+	IOMUX_DATA(__CONCAT(IOMUXC_SW_MUX_CTL_PAD_,padname), mux)
+
+#define	IOMUX_P(padname, pad)		\
+	IOMUX_DATA(__CONCAT(IOMUXC_SW_PAD_CTL_PAD_,padname), pad)
+
+#define	IOMUX_MP(padname, mux, pad)	\
+	IOMUX_M(padname, mux), \
+	IOMUX_P(padname, pad)
+
+
+#define	IOMUX_DATA(offset, value)	\
+	{				\
+		.reg = (offset),	\
+		.val = (value),		\
 	}
 
 
+/* 
+ * set same values to IOMUX registers as linux kernel does 
+ */
 const struct iomux_setup iomux_setup_data[] = {
+#define	HYS	PAD_CTL_HYS
+#define	ODE	PAD_CTL_ODE
+#define	DSEHIGH	PAD_CTL_DSE_HIGH
+#define	DSEMID	PAD_CTL_DSE_MID
+#define	DSELOW	PAD_CTL_DSE_LOW
+#define	DSEMAX	PAD_CTL_DSE_MAX
+#define	SRE	PAD_CTL_SRE
+#define	KEEPER	PAD_CTL_KEEPER
+#define	PULL	PAD_CTL_PULL
+#define	PU_22K	PAD_CTL_PUS_22K_PU
+#define	PU_47K	PAD_CTL_PUS_47K_PU
+#define	PU_100K	PAD_CTL_PUS_100K_PU
+#define	PD_100K	PAD_CTL_PUS_100K_PD
+#define	HVE	PAD_CTL_HVE	/* Low output voltage */
 
-	/* left buttons */
-	IOMUX_DATA(EIM_EB2, IOMUX_CONFIG_ALT1,
-		   PAD_CTL_HYS),
-	/* right buttons */
-	IOMUX_DATA(EIM_EB3, IOMUX_CONFIG_ALT1,
-		   PAD_CTL_HYS),
+#define	ALT0	IOMUX_CONFIG_ALT0
+#define	ALT1	IOMUX_CONFIG_ALT1
+#define	ALT2	IOMUX_CONFIG_ALT2
+#define	ALT3	IOMUX_CONFIG_ALT3
+#define	ALT4	IOMUX_CONFIG_ALT4
+#define	ALT5	IOMUX_CONFIG_ALT5
+#define	ALT6	IOMUX_CONFIG_ALT6
+#define	ALT7	IOMUX_CONFIG_ALT7
+#define	SION	IOMUX_CONFIG_SION
+
+	/* left button */
+	IOMUX_MP(EIM_EB2, ALT1, HYS),
+	/* right button */
+	IOMUX_MP(EIM_EB3, ALT1, HYS),
 
 	/* UART1 */
-#if 1
-	IOMUX_DATA(UART1_RXD, IOMUX_CONFIG_ALT0,
-		   PAD_CTL_DSE_HIGH | PAD_CTL_SRE),
+	IOMUX_MP(UART1_RXD, ALT0, HYS | PULL | DSEHIGH | SRE),
+	IOMUX_MP(UART1_TXD, ALT0, HYS | PULL | DSEHIGH | SRE),
+	IOMUX_MP(UART1_RTS, ALT0, HYS | PULL | DSEHIGH),
+	IOMUX_MP(UART1_CTS, ALT0, HYS | PULL | DSEHIGH),
+
+	/* LCD Display */
+	IOMUX_M(DI1_PIN2, ALT0),
+	IOMUX_M(DI1_PIN3, ALT0),
+
+	IOMUX_DATA(IOMUXC_SW_PAD_CTL_GRP_DISP1_PKE0, PAD_CTL_PKE),
+#if 0
+	IOMUX_MP(DISP1_DAT0, ALT0, SRE | DSEMAX | PULL),
+	IOMUX_MP(DISP1_DAT1, ALT0, SRE | DSEMAX | PULL),
+	IOMUX_MP(DISP1_DAT2, ALT0, SRE | DSEMAX | PULL),
+	IOMUX_MP(DISP1_DAT3, ALT0, SRE | DSEMAX | PULL),
+	IOMUX_MP(DISP1_DAT4, ALT0, SRE | DSEMAX | PULL),
+	IOMUX_MP(DISP1_DAT5, ALT0, SRE | DSEMAX | PULL),
+#endif
+	IOMUX_M(DISP1_DAT6, ALT0),
+	IOMUX_M(DISP1_DAT7, ALT0),
+	IOMUX_M(DISP1_DAT8, ALT0),
+	IOMUX_M(DISP1_DAT9, ALT0),
+	IOMUX_M(DISP1_DAT10, ALT0),
+	IOMUX_M(DISP1_DAT11, ALT0),
+	IOMUX_M(DISP1_DAT12, ALT0),
+	IOMUX_M(DISP1_DAT13, ALT0),
+	IOMUX_M(DISP1_DAT14, ALT0),
+	IOMUX_M(DISP1_DAT15, ALT0),
+	IOMUX_M(DISP1_DAT16, ALT0),
+	IOMUX_M(DISP1_DAT17, ALT0),
+	IOMUX_M(DISP1_DAT18, ALT0),
+	IOMUX_M(DISP1_DAT19, ALT0),
+	IOMUX_M(DISP1_DAT20, ALT0),
+	IOMUX_M(DISP1_DAT21, ALT0),
+	IOMUX_M(DISP1_DAT22, ALT0),
+	IOMUX_M(DISP1_DAT23, ALT0),
+
+	IOMUX_MP(DI1_D0_CS, ALT4, KEEPER | DSEHIGH | SRE), /* GPIO3_3 */
+	IOMUX_DATA(IOMUXC_GPIO3_IPP_IND_G_IN_3_SELECT_INPUT, INPUT_DAISY_0),
+	IOMUX_MP(CSI2_D12, ALT3, KEEPER | DSEHIGH | SRE), /* GPIO4_9 */
+	IOMUX_MP(CSI2_D13, ALT3, KEEPER | DSEHIGH | SRE),
+	IOMUX_MP(GPIO1_2, ALT0, ODE | DSEHIGH),
+	IOMUX_MP(EIM_A19, ALT1, SRE | DSEHIGH),
+	/* XXX VGA pins */
+	IOMUX_M(DI_GP4, ALT4),
+	IOMUX_M(GPIO1_8, SION | ALT0),
+
+
+#if 0
+	IOMUX_MP(GPIO1_2, ALT1, DSEHIGH | ODE),	/* LCD backlight by PWM */
 #else
-	IOMUX_DATA(UART1_RXD, IOMUX_CONFIG_ALT3,	/* gpio4[28] */
-		   PAD_CTL_DSE_HIGH | PAD_CTL_SRE),
+	IOMUX_P(GPIO1_2, DSEHIGH | ODE),	/* LCD backlight by GPIO */
+#endif
+	IOMUX_MP(GPIO1_8, SION | ALT0, HYS | DSEMID | PU_100K),
+	/* I2C1 */
+	IOMUX_MP(EIM_D16, SION | ALT4, HYS | ODE | DSEHIGH | SRE),
+	IOMUX_MP(EIM_D19, SION | ALT4, SRE),	/* SCL */
+	IOMUX_MP(EIM_A19, ALT1, SRE | DSEHIGH), /* GPIO2_13 */
+
+#if 0
+	IOMUX_MP(EIM_A23, ALT1, 0),
+#else
+	IOMUX_M(EIM_A23, ALT1),	/* GPIO2_17 */
 #endif
-	IOMUX_DATA(UART1_TXD, IOMUX_CONFIG_ALT0,
-		   PAD_CTL_DSE_HIGH | PAD_CTL_SRE),
-	IOMUX_DATA(UART1_RTS, IOMUX_CONFIG_ALT0,
-		   PAD_CTL_DSE_HIGH),
-	IOMUX_DATA(UART1_CTS, IOMUX_CONFIG_ALT0,
-		   PAD_CTL_DSE_HIGH),
+
+	/* BT */
+	IOMUX_M(EIM_D20, ALT1),	/* GPIO2_4 BT host wakeup */
+	IOMUX_M(EIM_D22, ALT1),	/* GPIO2_6 BT RESET */
+	IOMUX_M(EIM_D23, ALT1),	/* GPIO2_7 BT wakeup */
+
+	/* UART3 */
+	IOMUX_MP(EIM_D24, ALT3, KEEPER | PU_100K | DSEHIGH | SRE),
+	IOMUX_MP(EIM_D25, ALT3, KEEPER | PU_100K | DSEHIGH | SRE), /* CTS */
+	IOMUX_MP(EIM_D26, ALT3, KEEPER | PU_100K | DSEHIGH | SRE), /* TXD */
+	IOMUX_MP(EIM_D27, ALT3, KEEPER | PU_100K | DSEHIGH | SRE), /* RTS */
+	IOMUX_M(NANDF_D15, ALT3),	/* GPIO3_25 */
+	IOMUX_MP(NANDF_D14, ALT3, HYS | PULL | PU_100K ),	/* GPIO3_26 */
+	IOMUX_M(CSI1_D9, ALT3),			/* GPIO3_13 */
+	IOMUX_M(CSI1_VSYNC, ALT3),		/* GPIO3_14 */
+	IOMUX_M(CSI1_HSYNC, ALT3),		/* GPIO3_15 */
+
+	/* audio pins */
+	IOMUX_MP(AUD3_BB_TXD, ALT0, DSEHIGH | PU_100K | SRE),
+		/* XXX: linux code:
+		   (PAD_CTL_SRE_FAST	     | PAD_CTL_DRV_HIGH |
+		   PAD_CTL_100K_PU	     | PAD_CTL_HYS_NONE |
+		   PAD_CTL_DDR_INPUT_CMOS | PAD_CTL_DRV_VOT_LOW), */
+
+	IOMUX_MP(AUD3_BB_RXD, ALT0, KEEPER | DSEHIGH | SRE),
+	IOMUX_MP(AUD3_BB_CK, ALT0, KEEPER | DSEHIGH | SRE),
+	IOMUX_MP(AUD3_BB_FS, ALT0, KEEPER | DSEHIGH | SRE),
+
+	/* headphone detect */
+	IOMUX_MP(NANDF_D14, ALT3, HYS | PULL | PU_100K),
+	IOMUX_MP(CSPI1_RDY, ALT3, SRE | DSEHIGH),
+	/* XXX more audio pins ? */
+
+	/* CSPI */
+	/* ??? doesn't work ??? */
+	IOMUX_P(CSPI1_MOSI, HYS | PULL | PD_100K | DSEHIGH | SRE),
+	IOMUX_P(CSPI1_MISO, HYS | PULL | PD_100K | DSEHIGH | SRE),
+	IOMUX_M(CSPI1_SS0, ALT3),
+	IOMUX_MP(CSPI1_SS1, ALT0, HYS | KEEPER | DSEHIGH | SRE),
+	IOMUX_MP(DI1_PIN11, ALT7, HYS | PULL | DSEHIGH | SRE),
+	IOMUX_P(CSPI1_SCLK, HYS | KEEPER | DSEHIGH | SRE),
+	/* 26M Osc */
+	IOMUX_MP(DI1_PIN12, ALT4, KEEPER | DSEHIGH | SRE), /* GPIO3_1 */
+
+	/* I2C */
+	IOMUX_MP(KEY_COL4, SION | ALT3, SRE),
+	IOMUX_DATA(IOMUXC_I2C2_IPP_SCL_IN_SELECT_INPUT, INPUT_DAISY_1),
+	IOMUX_MP(KEY_COL5, SION | ALT3, HYS | ODE | DSEHIGH | SRE),
+	IOMUX_DATA(IOMUXC_I2C2_IPP_SDA_IN_SELECT_INPUT, INPUT_DAISY_1),
+	IOMUX_DATA(IOMUXC_UART3_IPP_UART_RTS_B_SELECT_INPUT, INPUT_DAISY_3),
+#if 1
+	/* NAND */
+	IOMUX_MP(NANDF_WE_B, ALT0, HVE | DSEHIGH | PULL | PU_47K),
+	IOMUX_MP(NANDF_RE_B, ALT0, HVE | DSEHIGH | PULL | PU_47K),
+	IOMUX_MP(NANDF_ALE, ALT0, HVE | DSEHIGH | KEEPER),
+	IOMUX_MP(NANDF_CLE, ALT0, HVE | DSEHIGH | KEEPER),
+	IOMUX_MP(NANDF_WP_B, ALT0, HVE | DSEHIGH | PULL | PU_100K),
+	IOMUX_MP(NANDF_RB0, ALT0, HVE | DSELOW | PULL | PU_100K),
+	IOMUX_MP(NANDF_RB1, ALT0, HVE | DSELOW | PULL | PU_100K),
+	IOMUX_MP(NANDF_D7, ALT0, HVE | DSEHIGH | KEEPER | PU_100K),
+	IOMUX_MP(NANDF_D6, ALT0, HVE | DSEHIGH | KEEPER | PU_100K),
+	IOMUX_MP(NANDF_D5, ALT0, HVE | DSEHIGH | KEEPER | PU_100K),
+	IOMUX_MP(NANDF_D4, ALT0, HVE | DSEHIGH | KEEPER | PU_100K),
+	IOMUX_MP(NANDF_D3, ALT0, HVE | DSEHIGH | KEEPER | PU_100K),
+	IOMUX_MP(NANDF_D2, ALT0, HVE | DSEHIGH | KEEPER | PU_100K),
+	IOMUX_MP(NANDF_D1, ALT0, HVE | DSEHIGH | KEEPER | PU_100K),
+	IOMUX_MP(NANDF_D0, ALT0, HVE | DSEHIGH | KEEPER | PU_100K),
+#endif
+
+	/* Batttery pins */
+	IOMUX_MP(NANDF_D13, ALT3, HYS | DSEHIGH),
+	IOMUX_MP(NANDF_D12, ALT3, HYS | DSEHIGH),
+#if 0
+	IOMUX_MP(NANDF_D11, ALT3, HYS | DSEHIGH),
+#endif
+	IOMUX_MP(NANDF_D10, ALT3, HYS | DSEHIGH),
+
+	/* SD1 */
+	IOMUX_MP(SD1_CMD, SION | ALT0, DSEHIGH | SRE),
+	IOMUX_MP(SD1_CLK, SION | ALT0, KEEPER | PU_47K | DSEHIGH),
+	IOMUX_MP(SD1_DATA0, ALT0, DSEHIGH | SRE),
+	IOMUX_MP(SD1_DATA1, ALT0, DSEHIGH | SRE),
+	IOMUX_MP(SD1_DATA2, ALT0, DSEHIGH | SRE),
+	IOMUX_MP(SD1_DATA3, ALT0, DSEHIGH | SRE),
+	IOMUX_MP(GPIO1_0, SION | ALT0, HYS | PU_100K),
+
+	/* SD2 */
+	IOMUX_P(SD2_CMD, HVE | PU_22K | DSEMAX | SRE),
+	IOMUX_P(SD2_CLK, HVE | PU_22K | DSEMAX | SRE),
+	IOMUX_P(SD2_DATA0, HVE | PU_22K | DSEMAX | SRE),
+	IOMUX_P(SD2_DATA1, HVE | PU_22K | DSEMAX | SRE),
+	IOMUX_P(SD2_DATA2, HVE | PU_22K | DSEMAX | SRE),
+	IOMUX_P(SD2_DATA3, HVE | PU_22K | DSEMAX | SRE),
+
+	/* USB */
+	IOMUX_MP(USBH1_CLK, ALT0, HYS | KEEPER | DSEHIGH | SRE),
+	IOMUX_MP(USBH1_DIR, ALT0, HYS | KEEPER | DSEHIGH | SRE),
+	IOMUX_MP(USBH1_STP, ALT0, HYS | KEEPER | DSEHIGH | SRE),
+	IOMUX_MP(USBH1_NXT, ALT0, HYS | KEEPER | PU_100K | DSEHIGH | SRE),
+	IOMUX_MP(USBH1_DATA0, ALT0, HYS | KEEPER | DSEHIGH | SRE),
+	IOMUX_MP(USBH1_DATA1, ALT0, HYS | KEEPER | DSEHIGH | SRE),
+	IOMUX_MP(USBH1_DATA2, ALT0, HYS | KEEPER | DSEHIGH | SRE),
+	IOMUX_MP(USBH1_DATA3, ALT0, HYS | KEEPER | DSEHIGH | SRE),
+	IOMUX_MP(USBH1_DATA4, ALT0, HYS | KEEPER | DSEHIGH | SRE),
+	IOMUX_MP(USBH1_DATA5, ALT0, HYS | KEEPER | DSEHIGH | SRE),
+	IOMUX_MP(USBH1_DATA6, ALT0, HYS | KEEPER | DSEHIGH | SRE),
+	IOMUX_MP(USBH1_DATA7, ALT0, HYS | KEEPER | DSEHIGH | SRE),
+	IOMUX_MP(EIM_D17, ALT1, KEEPER | DSEHIGH | SRE),
+	IOMUX_MP(EIM_D21, ALT1, KEEPER | DSEHIGH | SRE),
+	IOMUX_P(GPIO1_7, /*ALT0,*/ DSEHIGH | SRE),	/* USB Hub reset */
+
+#undef	ODE
+#undef	HYS
+#undef	SRE
+#undef	PULL
+#undef	KEEPER
+#undef	PU_22K
+#undef	PU_47K
+#undef	PU_100K
+#undef	PD_100K
+#undef	HVE
+#undef	DSEMAX
+#undef	DSEHIGH
+#undef	DSEMID
+#undef	DSELOW
+
+#undef	ALT0
+#undef	ALT1
+#undef	ALT2
+#undef	ALT3
+#undef	ALT4
+#undef	ALT5
+#undef	ALT6
+#undef	ALT7
+#undef	SION
 };
 
 static void
@@ -973,29 +1188,12 @@
 	int i;
 	const struct iomux_setup *p;
 
-#if 0	/* These are all done already by Netwalker's bootloader. */
-	/* set IO multiplexor for UART1 */
-	uint32_t reg;
-	uint32_t addr;
-
-	/* input */
-	addr = NETWALKER_IOMUXC_VBASE + MUX_IN_UART1_IPP_UART_RXD_MUX;
-	reg = INPUT_DAISY_0;
-	ioreg_write(addr, reg);
-	addr = NETWALKER_IOMUXC_VBASE + MUX_IN_UART1_IPP_UART_RTS_B;
-	reg = INPUT_DAISY_0;
-	ioreg_write(addr, reg);
-#endif
-
+	/* Initialize all IOMUX registers */
 	for (i=0; i < __arraycount(iomux_setup_data); ++i) {
 		p = iomux_setup_data + i;
 
-		ioreg_write(NETWALKER_IOMUXC_VBASE + 
-			    p->pad_ctl_reg,
-			    p->pad_ctl_val);
-		ioreg_write(NETWALKER_IOMUXC_VBASE + 
-			    p->mux_ctl_reg,
-			    p->mux_ctl_val);
+		ioreg_write(NETWALKER_IOMUXC_VBASE + p->reg,
+			    p->val);
 	}
 
 
@@ -1032,7 +1230,7 @@
 #endif	/* CONSDEVNAME */
 
 #ifndef	IMXUART_FREQ
-#define	IMXUART_FREQ	66355200
+#define	IMXUART_FREQ	66500000
 #endif
 
 void
--- a/sys/arch/evbarm/netwalker/netwalker_usb.c	Tue Apr 17 19:25:17 2012 +0000
+++ b/sys/arch/evbarm/netwalker/netwalker_usb.c	Sun Apr 29 23:04:36 2012 +0000
@@ -25,7 +25,7 @@
  *
  */
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: netwalker_usb.c,v 1.1 2010/12/09 04:40:22 bsh Exp $");
+__KERNEL_RCSID(0, "$NetBSD: netwalker_usb.c,v 1.1.14.1 2012/04/29 23:04:39 mrg Exp $");
 
 #include <sys/param.h>
 #include <sys/systm.h>
@@ -144,7 +144,7 @@
 	uint32_t reg;
 
 	/* output HIGH to USBH1_STP */
-	gpio_data_write(GPIO_NO(1,27), 1);
+	gpio_data_write(GPIO_NO(1, 27), 1);
 	gpio_set_direction(GPIO_NO(1, 27), GPIO_DIR_OUT);
 
 	iomux_mux_config(iomux_usb1_config);
@@ -173,14 +173,13 @@
 	bus_space_write_4(usbc->sc_iot, usbc->sc_ioh,
 			  USBOH3_USBCTRL, reg);
 
-	iomux_set_function(MUX_PIN_USBH1_STP, IOMUX_CONFIG_ALT0);
+	iomux_set_function(MUX_PIN(USBH1_STP), IOMUX_CONFIG_ALT0);
 
 
 	/* HUB RESET release */
 	gpio_data_write(GPIO_NO(1, 7), 1);
 	gpio_set_direction(GPIO_NO(1, 7), GPIO_DIR_OUT);
 
-
 	/* Drive 26M_OSC_EN line high 3_1 */
 	gpio_data_write(GPIO_NO(3, 1), 1);
 	gpio_set_direction(GPIO_NO(3, 1), GPIO_DIR_OUT);
@@ -193,7 +192,7 @@
 	delay(10 * 1000);
 	gpio_data_write(GPIO_NO(2, 5), 1);
 	gpio_set_direction(GPIO_NO(2, 5), GPIO_DIR_OUT);
-	iomux_set_function(MUX_PIN_EIM_D21, IOMUX_CONFIG_ALT1);
+	iomux_set_function(MUX_PIN(EIM_D21), IOMUX_CONFIG_ALT1);
 	delay(5 * 1000);
 }
 
@@ -206,7 +205,7 @@
 	{
 		/* Initially setup this pin for GPIO, and change to
 		 * USBH1_STP later */
-		.pin = MUX_PIN_USBH1_STP,
+		.pin = MUX_PIN(USBH1_STP),
 		.mux = IOMUX_CONFIG_ALT2,
 		.pad = (PAD_CTL_SRE | PAD_CTL_DSE_HIGH |
 		    PAD_CTL_KEEPER | PAD_CTL_HYS)
@@ -214,14 +213,14 @@
 
 	{
 		/* Clock */
-		.pin = MUX_PIN_USBH1_CLK,
+		.pin = MUX_PIN(USBH1_CLK),
 		.mux = IOMUX_CONFIG_ALT0,
-		.pad = (PAD_CTL_SRE | PAD_CTL_DSE_HIGH | 
+		.pad = (PAD_CTL_SRE | PAD_CTL_DSE_HIGH |
 		    PAD_CTL_KEEPER | PAD_CTL_HYS)
 	},
 	{
 		/* DIR */
-		.pin = MUX_PIN_USBH1_DIR,
+		.pin = MUX_PIN(USBH1_DIR),
 		.mux = IOMUX_CONFIG_ALT0,
 		.pad = (PAD_CTL_SRE | PAD_CTL_DSE_HIGH |
 		    PAD_CTL_KEEPER | PAD_CTL_HYS)
@@ -229,7 +228,7 @@
 
 	{
 		/* NXT */
-		.pin = MUX_PIN_USBH1_NXT,
+		.pin = MUX_PIN(USBH1_NXT),
 		.mux = IOMUX_CONFIG_ALT0,
 		.pad = (PAD_CTL_SRE | PAD_CTL_DSE_HIGH |
 		    PAD_CTL_KEEPER | PAD_CTL_HYS)
@@ -238,7 +237,7 @@
 #define	USBH1_DATA_CONFIG(n)					\
 	{							\
 		/* DATA n */					\
-		.pin = __CONCAT(MUX_PIN_USBH1_DATA,n),		\
+		.pin = MUX_PIN(USBH1_DATA##n),			\
 		.mux = IOMUX_CONFIG_ALT0,			\
 		.pad = (PAD_CTL_SRE | PAD_CTL_DSE_HIGH |	\
 		    PAD_CTL_KEEPER | PAD_CTL_PUS_100K_PU |	\
@@ -257,24 +256,31 @@
 
 	{
 		/* USB_CLK_EN_B  GPIO2[1]*/
-		.pin = MUX_PIN_EIM_D17,
+		.pin = MUX_PIN(EIM_D17),
 		.mux = IOMUX_CONFIG_ALT1,
 		.pad = (PAD_CTL_DSE_HIGH | PAD_CTL_PKE | PAD_CTL_SRE),
 	},
 
 	{
 		/* USB PHY RESETB */
-		.pin = MUX_PIN_EIM_D21,
+		.pin = MUX_PIN(EIM_D21),
 		.mux = IOMUX_CONFIG_ALT1,
 		.pad = (PAD_CTL_DSE_HIGH | PAD_CTL_KEEPER |
 		    PAD_CTL_PUS_100K_PU | PAD_CTL_SRE)
 	},
 	{
 		/* USB HUB RESET */
-		.pin = MUX_PIN_GPIO1_7,
+		.pin = MUX_PIN(GPIO1_7),
 		.mux = IOMUX_CONFIG_ALT0,
 		.pad = (PAD_CTL_DSE_HIGH | PAD_CTL_SRE),
 	},
+	{
+		/* 26M_OSC pin settings */
+		.pin = MUX_PIN(DI1_PIN12),
+		.mux = IOMUX_CONFIG_ALT4,
+		.pad = (PAD_CTL_DSE_HIGH | PAD_CTL_KEEPER |
+		    PAD_CTL_SRE),
+	},
 
 	/* end of table */
 	{.pin = IOMUX_CONF_EOT}
--- a/sys/arch/evbppc/obs405/rbus_machdep.c	Tue Apr 17 19:25:17 2012 +0000
+++ b/sys/arch/evbppc/obs405/rbus_machdep.c	Sun Apr 29 23:04:36 2012 +0000
@@ -1,4 +1,4 @@
-/*	$NetBSD: rbus_machdep.c,v 1.8 2011/06/22 18:06:32 matt Exp $	*/
+/*	$NetBSD: rbus_machdep.c,v 1.8.6.1 2012/04/29 23:04:39 mrg Exp $	*/
 
 /*
  * Copyright (c) 2003
@@ -80,8 +80,8 @@
 rbus_pccbb_parent_mem(struct pci_attach_args *pa)
 {
 	bus_space_tag_t bst = pa->pa_memt;
-	
-	return rbus_new_root_share(bst, bst->pbs_extent, bst->pbs_base,
+
+	return rbus_new_root_delegate(bst, bst->pbs_base,
 	    bst->pbs_limit - bst->pbs_base, 0);
 }
 
@@ -89,7 +89,7 @@
 rbus_pccbb_parent_io(struct pci_attach_args *pa)
 {
 	bus_space_tag_t bst = pa->pa_iot;
-	
-	return rbus_new_root_share(bst, bst->pbs_extent, bst->pbs_base,
+
+	return rbus_new_root_delegate(bst, bst->pbs_base,
 	    bst->pbs_limit - bst->pbs_base, 0);
 }
--- a/sys/arch/hp700/conf/GENERIC	Tue Apr 17 19:25:17 2012 +0000
+++ b/sys/arch/hp700/conf/GENERIC	Sun Apr 29 23:04:36 2012 +0000
@@ -1,4 +1,4 @@
-# $NetBSD: GENERIC,v 1.108.2.2 2012/03/11 01:52:21 mrg Exp $
+# $NetBSD: GENERIC,v 1.108.2.3 2012/04/29 23:04:39 mrg Exp $
 #
 # GENERIC machine description file
 #
@@ -23,7 +23,7 @@
 options 	INCLUDE_CONFIG_FILE	# embed config file in kernel binary
 options 	SYSCTL_INCLUDE_DESCR	# Include sysctl descriptions in kernel
 
-#ident 		"GENERIC-$Revision: 1.108.2.2 $"
+#ident 		"GENERIC-$Revision: 1.108.2.3 $"
 
 maxusers	32		# estimated number of users
 
@@ -40,7 +40,6 @@
 options 	HP8700_CPU		# PCX-W2 (in 32bit mode)
 
 # CPU-related options.
-options 	FPEMUL		# floating point emulation XXX DO NOT REMOVE
 options 	USELEDS		# blink 'em
 
 # delay between "rebooting ..." message and hardware reset, in milliseconds
--- a/sys/arch/hp700/dev/apic.c	Tue Apr 17 19:25:17 2012 +0000
+++ b/sys/arch/hp700/dev/apic.c	Sun Apr 29 23:04:36 2012 +0000
@@ -1,6 +1,6 @@
-/*	$NetBSD: apic.c,v 1.12.8.1 2012/04/05 21:33:14 mrg Exp $	*/
+/*	$NetBSD: apic.c,v 1.12.8.2 2012/04/29 23:04:39 mrg Exp $	*/
 
-/*	$OpenBSD: apic.c,v 1.7 2007/10/06 23:50:54 krw Exp $	*/
+/*	$OpenBSD: apic.c,v 1.14 2011/05/01 21:59:39 kettenis Exp $	*/
 
 /*
  * Copyright (c) 2005 Michael Shalayeff
@@ -178,53 +178,61 @@
 	if (aiv == NULL)
 		return NULL;
 
+	cnt = malloc(sizeof(struct evcnt), M_DEVBUF, M_NOWAIT);
+	if (cnt == NULL) {
+		free(aiv, M_DEVBUF);
+		return NULL;
+	}
+
 	aiv->sc = sc;
 	aiv->ih = ih;
 	aiv->handler = handler;
 	aiv->arg = arg;
 	aiv->next = NULL;
-	aiv->cnt = NULL;
-	if (apic_intr_list[irq]) {
-		cnt = malloc(sizeof(struct evcnt), M_DEVBUF, M_NOWAIT);
-		if (cnt == NULL) {
+	aiv->cnt = cnt;
+
+	biv = apic_intr_list[irq];
+	if (biv == NULL) {
+		iv = hp700_intr_establish(pri, apic_intr, aiv, &ir_cpu, irq);
+		if (iv == NULL) {
 			free(aiv, M_DEVBUF);
+			free(cnt, M_DEVBUF);
+
 			return NULL;
 		}
+	}
 
-		snprintf(aiv->aiv_name, sizeof(aiv->aiv_name), "line %d irq %d",
-		    line, irq);
+	snprintf(aiv->aiv_name, sizeof(aiv->aiv_name), "line %d irq %d",
+	    line, irq);
 
-		evcnt_attach_dynamic(cnt, EVCNT_TYPE_INTR, NULL,
-		    device_xname(sc->sc_dv), aiv->aiv_name);
-		biv = apic_intr_list[irq];
+	evcnt_attach_dynamic(cnt, EVCNT_TYPE_INTR, NULL,
+	    device_xname(sc->sc_dv), aiv->aiv_name);
+
+	if (biv) {
 		while (biv->next)
 			biv = biv->next;
 		biv->next = aiv;
-		aiv->cnt = cnt;
 		return arg;
 	}
 
-	iv = hp700_intr_establish(pri, apic_intr, aiv, &ir_cpu, irq);
-	if (iv) {
-		ent0 = (31 - irq) & APIC_ENT0_VEC;
-		ent0 |= apic_get_int_ent0(sc, line);
+	ent0 = (31 - irq) & APIC_ENT0_VEC;
+	ent0 |= apic_get_int_ent0(sc, line);
 #if 0
-		if (cold) {
-			sc->sc_imr |= (1 << irq);
-			ent0 |= APIC_ENT0_MASK;
-		}
+	if (cold) {
+		sc->sc_imr |= (1 << irq);
+		ent0 |= APIC_ENT0_MASK;
+	}
 #endif
-		apic_write(sc->sc_regs, APIC_ENT0(line), APIC_ENT0_MASK);
-		apic_write(sc->sc_regs, APIC_ENT1(line),
-		    ((hpa & 0x0ff00000) >> 4) | ((hpa & 0x000ff000) << 12));
-		apic_write(sc->sc_regs, APIC_ENT0(line), ent0);
+	apic_write(sc->sc_regs, APIC_ENT0(line), APIC_ENT0_MASK);
+	apic_write(sc->sc_regs, APIC_ENT1(line),
+	    ((hpa & 0x0ff00000) >> 4) | ((hpa & 0x000ff000) << 12));
+	apic_write(sc->sc_regs, APIC_ENT0(line), ent0);
 
-		/* Signal EOI. */
-		elroy_write32(&r->apic_eoi,
-		    htole32((31 - irq) & APIC_ENT0_VEC));
+	/* Signal EOI. */
+	elroy_write32(&r->apic_eoi,
+	    htole32((31 - irq) & APIC_ENT0_VEC));
 
-		apic_intr_list[irq] = aiv;
-	}
+	apic_intr_list[irq] = aiv;
 
 	return (arg);
 }
@@ -244,11 +252,11 @@
 	int claimed = 0;
 
 	while (iv) {
-		if (iv->handler(iv->arg)) {
-			if (iv->cnt)
-				iv->cnt->ev_count++;
-			claimed = 1;
-		}
+		claimed = iv->handler(iv->arg);
+		if (claimed && iv->cnt)
+			iv->cnt->ev_count++;
+		if (claimed)
+			break;
 		iv = iv->next;
 	}
 	/* Signal EOI. */
--- a/sys/arch/hp700/dev/cpu.c	Tue Apr 17 19:25:17 2012 +0000
+++ b/sys/arch/hp700/dev/cpu.c	Sun Apr 29 23:04:36 2012 +0000
@@ -1,4 +1,4 @@
-/*	$NetBSD: cpu.c,v 1.19.8.2 2012/04/05 21:33:14 mrg Exp $	*/
+/*	$NetBSD: cpu.c,v 1.19.8.3 2012/04/29 23:04:39 mrg Exp $	*/
 
 /*	$OpenBSD: cpu.c,v 1.29 2009/02/08 18:33:28 miod Exp $	*/
 
@@ -29,7 +29,7 @@
  */
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.19.8.2 2012/04/05 21:33:14 mrg Exp $");
+__KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.19.8.3 2012/04/29 23:04:39 mrg Exp $");
 
 #include "opt_multiprocessor.h"
 
@@ -146,23 +146,14 @@
 		aprint_normal(", %u/%u D/I BTLBs", pdc_btlb.finfo.num_i,
 		    pdc_btlb.finfo.num_d);
 	}
+	aprint_normal("\n");
 
 	/*
 	 * Describe the floating-point support.
 	 */
-#ifndef	FPEMUL
-	if (!fpu_present)
-		aprint_normal("\n%s: no floating point support",
-		    self->dv_xname);
-	else
-#endif /* !FPEMUL */
-	{
-		aprint_normal("\n%s: %s floating point, rev %d", self->dv_xname,
-		    hppa_mod_info(HPPA_TYPE_FPU, (fpu_version >> 16) & 0x1f),
-		    (fpu_version >> 11) & 0x1f);
-	}
-
-	aprint_normal("\n");
+	aprint_normal("%s: %s floating point, rev %d\n", self->dv_xname,
+	    hppa_mod_info(HPPA_TYPE_FPU, (fpu_version >> 16) & 0x1f),
+	    (fpu_version >> 11) & 0x1f);
 
 	/* sanity against luser amongst config editors */
 	if (ca->ca_irq != 31) {
--- a/sys/arch/hp700/dev/ssio.c	Tue Apr 17 19:25:17 2012 +0000
+++ b/sys/arch/hp700/dev/ssio.c	Sun Apr 29 23:04:36 2012 +0000
@@ -1,4 +1,4 @@
-/*	$NetBSD: ssio.c,v 1.2 2011/07/01 18:33:09 dyoung Exp $	*/
+/*	$NetBSD: ssio.c,v 1.2.6.1 2012/04/29 23:04:39 mrg Exp $	*/
 
 /*	$OpenBSD: ssio.c,v 1.7 2009/03/08 22:19:04 miod Exp $	*/
 
@@ -160,8 +160,8 @@
 	if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_NS)
 		return 0;
 
-        if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_NS_PC87560)
-                return 1;
+	if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_NS_PC87560)
+		return 1;
 
 	return 0;
 }
@@ -204,10 +204,10 @@
 	sc->sc_ih = pci_intr_establish(pa->pa_pc, ih, IPL_TTY, ssio_intr,
 	    sc);
 	if (sc->sc_ih == NULL) {
-                aprint_error_dev(self, "could not establish interrupt");
-                if (intrstr != NULL)
-                        aprint_error(" at %s", intrstr);
-                aprint_error("\n");
+		aprint_error_dev(self, "could not establish interrupt");
+		if (intrstr != NULL)
+			aprint_error(" at %s", intrstr);
+		aprint_error("\n");
 		goto unmap_ic2;
 	}
 	aprint_normal_dev(self, "interrupting at %s\n", intrstr);
@@ -324,7 +324,7 @@
 	irq = bus_space_read_1(sc->sc_iot, sc->sc_ic1h, 0);
 	irq &= 0x07;
 
-	if (irq  == 7) {
+	if (irq == 7) {
 		bus_space_write_1(sc->sc_iot, sc->sc_ic1h, 0, 0x0b);
 		isr = bus_space_read_1(sc->sc_iot, sc->sc_ic1h, 0);
 		if ((isr & 0x80) == 0)
--- a/sys/arch/hp700/hp700/locore.S	Tue Apr 17 19:25:17 2012 +0000
+++ b/sys/arch/hp700/hp700/locore.S	Sun Apr 29 23:04:36 2012 +0000
@@ -1,4 +1,4 @@
-/*	$NetBSD: locore.S,v 1.55.8.2 2012/04/05 21:33:14 mrg Exp $	*/
+/*	$NetBSD: locore.S,v 1.55.8.3 2012/04/29 23:04:39 mrg Exp $	*/
 /*	$OpenBSD: locore.S,v 1.158 2008/07/28 19:08:46 miod Exp $	*/
 
 /*
@@ -1034,13 +1034,6 @@
 	ldw	HPPA_FRAME_ARG(0)(%r3), %arg0
 
 noras:
-	/*
-	 * As an optimization, hppa_fpu_bootstrap
-	 * replaces this branch instruction with a
-	 * nop if there is a hardware FPU.
-	 */
-ALTENTRY(hppa_fpu_nop1)
-	b,n	switch_return
 
 	/*
 	 * We do have a hardware FPU.  If the LWP
--- a/sys/arch/hp700/hp700/machdep.c	Tue Apr 17 19:25:17 2012 +0000
+++ b/sys/arch/hp700/hp700/machdep.c	Sun Apr 29 23:04:36 2012 +0000
@@ -1,4 +1,4 @@
-/*	$NetBSD: machdep.c,v 1.100.6.4 2012/04/05 21:33:14 mrg Exp $	*/
+/*	$NetBSD: machdep.c,v 1.100.6.5 2012/04/29 23:04:40 mrg Exp $	*/
 
 /*-
  * Copyright (c) 2001, 2002 The NetBSD Foundation, Inc.
@@ -58,7 +58,7 @@
  */
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: machdep.c,v 1.100.6.4 2012/04/05 21:33:14 mrg Exp $");
+__KERNEL_RCSID(0, "$NetBSD: machdep.c,v 1.100.6.5 2012/04/29 23:04:40 mrg Exp $");
 
 #include "opt_cputype.h"
 #include "opt_ddb.h"
@@ -1059,7 +1059,7 @@
 	error = pdcproc_btlb_insert(sp, va, pa, sz, prot, i);
 	if (error < 0) {
 #ifdef BTLBDEBUG
-		DPRINTF(("WARNING: BTLB insert failed (%d)\n", error);
+		DPRINTF(("WARNING: BTLB insert failed (%d)\n", error));
 #endif
 	}
 	return error;
--- a/sys/arch/hppa/hppa/fpu.c	Tue Apr 17 19:25:17 2012 +0000
+++ b/sys/arch/hppa/hppa/fpu.c	Sun Apr 29 23:04:36 2012 +0000
@@ -1,4 +1,4 @@
-/*	$NetBSD: fpu.c,v 1.23 2011/01/23 09:44:59 skrll Exp $	*/
+/*	$NetBSD: fpu.c,v 1.23.8.1 2012/04/29 23:04:40 mrg Exp $	*/
 
 /*
  * Copyright (c) 2002 The NetBSD Foundation, Inc.
@@ -34,7 +34,7 @@
  */
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: fpu.c,v 1.23 2011/01/23 09:44:59 skrll Exp $");
+__KERNEL_RCSID(0, "$NetBSD: fpu.c,v 1.23.8.1 2012/04/29 23:04:40 mrg Exp $");
 
 #include <sys/param.h>
 #include <sys/systm.h>
@@ -82,7 +82,8 @@
 void hppa_fpu_swapout(struct pcb *);
 void hppa_fpu_swap(struct fpreg *, struct fpreg *);
 
-#ifdef FPEMUL
+static int hppa_fpu_ls(struct trapframe *, struct lwp *);
+
 /*
  * Given a trapframe and a general register number, the 
  * FRAME_REG macro returns a pointer to that general
@@ -131,7 +132,6 @@
 	_FRAME_POSITION(tf_sp),		/* r30 */
 	_FRAME_POSITION(tf_r31),
 };
-#endif /* FPEMUL */
 
 /*
  * Bootstraps the FPU.
@@ -141,69 +141,43 @@
 {
 	uint32_t junk[2];
 	uint32_t vers[2];
-	extern u_int hppa_fpu_nop0;
-	extern u_int hppa_fpu_nop1;
 
 	/* See if we have a present and functioning hardware FPU. */
 	fpu_present = (ccr_enable & HPPA_FPUS) == HPPA_FPUS;
 
+	KASSERT(fpu_present);
 	/* Initialize the FPU and get its version. */
-	if (fpu_present) {
 
-		/*
-		 * To somewhat optimize the emulation
-		 * assist trap handling and context
-		 * switching (to save them from having
-	 	 * to always load and check fpu_present),
-		 * there are two instructions in locore.S
-		 * that are replaced with nops when 
-		 * there is a hardware FPU.
-	 	 */
-		hppa_fpu_nop0 = OPCODE_NOP;
-		hppa_fpu_nop1 = OPCODE_NOP;
-		fcacheall();
-
-		/*
-		 * We track what process has the FPU,
-		 * and how many times we have to swap
-		 * in and out.
-		 */
+	/*
+	 * We track what process has the FPU,
+	 * and how many times we have to swap
+	 * in and out.
+	 */
 
-		/*
-		 * The PA-RISC 1.1 Architecture manual is 
-		 * pretty clear that the copr,0,0 must be 
-		 * wrapped in double word stores of fr0, 
-		 * otherwise its operation is undefined.
-		 */
-		__asm volatile(
-			"	ldo	%0, %%r22	\n"
-			"	fstds	%%fr0, 0(%%r22)	\n"
-			"	ldo	%1, %%r22	\n"
-			"	copr,0,0		\n"
-			"	fstds	%%fr0, 0(%%r22)	\n"
-			: "=m" (junk), "=m" (vers) : : "r22");
+	/*
+	 * The PA-RISC 1.1 Architecture manual is 
+	 * pretty clear that the copr,0,0 must be 
+	 * wrapped in double word stores of fr0, 
+	 * otherwise its operation is undefined.
+	 */
+	__asm volatile(
+		"	ldo	%0, %%r22	\n"
+		"	fstds	%%fr0, 0(%%r22)	\n"
+		"	ldo	%1, %%r22	\n"
+		"	copr,0,0		\n"
+		"	fstds	%%fr0, 0(%%r22)	\n"
+		: "=m" (junk), "=m" (vers) : : "r22");
 
-		/*
-		 * Now mark that no process has the FPU,
-		 * and disable it, so the first time it
-		 * gets used the process' state gets
-		 * swapped in.
-		 */
-		fpu_csw = 0;
-		curcpu()->ci_fpu_state = 0;
-		mtctl(ccr_enable & (CCR_MASK ^ HPPA_FPUS), CR_CCR);	
-	} 
-#ifdef FPEMUL
-	else
-		/*
-		 * XXX This is a hack - to avoid
-		 * having to set up the emulator so
-		 * it can work for one instruction for
-		 * proc0, we dispatch the copr,0,0 opcode 
-		 * into the emulator directly.  
-		 */
-		decode_0c(OPCODE_COPR_0_0, 0, 0, vers);
-#endif /* FPEMUL */
+	/*
+	 * Now mark that no process has the FPU,
+	 * and disable it, so the first time it
+	 * gets used the process' state gets
+	 * swapped in.
+	 */
+	fpu_csw = 0;
+	curcpu()->ci_fpu_state = 0;
+	mtctl(ccr_enable & (CCR_MASK ^ HPPA_FPUS), CR_CCR);	
+
 	fpu_version = vers[0];
 }
 
@@ -218,12 +192,10 @@
 	struct pcb *pcb = lwp_getpcb(l);
 	struct cpu_info *ci = curcpu();
 
-	if (!fpu_present)
-		return;
+	KASSERT(fpu_present);
 
 	/*
-	 * If we have a hardware FPU, and this process'
-	 * state is currently in it, swap it out.
+	 * If this process' state is currently in hardware, swap it out.
 	 */
 	
 	if (ci->ci_fpu_state == 0 ||
@@ -235,12 +207,9 @@
 	ci->ci_fpu_state = 0;
 }
 
-#ifdef FPEMUL
-
 /*
  * This emulates a coprocessor load/store instruction.
  */
-static int hppa_fpu_ls(struct trapframe *, struct lwp *);
 static int 
 hppa_fpu_ls(struct trapframe *frame, struct lwp *l)
 {
@@ -448,5 +417,3 @@
 		trapsignal(l, &ksi);
 	}
 }
-
-#endif /* FPEMUL */
--- a/sys/arch/hppa/hppa/trap.S	Tue Apr 17 19:25:17 2012 +0000
+++ b/sys/arch/hppa/hppa/trap.S	Sun Apr 29 23:04:36 2012 +0000
@@ -1,4 +1,4 @@
-/*	$NetBSD: trap.S,v 1.60.8.3 2012/04/05 21:33:15 mrg Exp $	*/
+/*	$NetBSD: trap.S,v 1.60.8.4 2012/04/29 23:04:40 mrg Exp $	*/
 
 /*-
  * Copyright (c) 2002 The NetBSD Foundation, Inc.
@@ -267,7 +267,6 @@
 	/* We can now set the frame pointer */
 	copy	%t3, %r3
 
-#if defined(DDB) || defined(KGDB) || defined(FPEMUL)
 	stw	%r4 , TF_R4 -TRAPFRAME_SIZEOF(%sr1, %t3)
 	stw	%r5 , TF_R5 -TRAPFRAME_SIZEOF(%sr1, %t3)
 	stw	%r6 , TF_R6 -TRAPFRAME_SIZEOF(%sr1, %t3)
@@ -283,7 +282,7 @@
 	stw	%r16, TF_R16-TRAPFRAME_SIZEOF(%sr1, %t3)
 	stw	%r17, TF_R17-TRAPFRAME_SIZEOF(%sr1, %t3)
 	stw	%r18, TF_R18-TRAPFRAME_SIZEOF(%sr1, %t3)
-#endif /* DDB || KGDB || FPEMUL */
+
 	stw	%r0, 0(%sr1, %t3)	/* terminate frame */
 	copy	%r0 , %r3
 	stw	%r0, HPPA_FRAME_PSP(%sr1, %sp)
@@ -445,11 +444,11 @@
 	ldw	TF_R1(%t3), %r1
 	ldw	TF_R2(%t3), %r2
 	ldw	TF_R3(%t3), %r3
+
 	/*
 	 * See the comment in the trap handling code below about why we need to
 	 * save and restore all general registers under these cases.
 	 */
-#if defined(DDB) || defined(KGDB) || defined(FPEMUL)
 	ldw	TF_R4(%t3), %r4
 	ldw	TF_R5(%t3), %r5
 	ldw	TF_R6(%t3), %r6
@@ -465,7 +464,7 @@
 	ldw	TF_R16(%t3), %r16
 	ldw	TF_R17(%t3), %r17
 	ldw	TF_R18(%t3), %r18
-#endif /* DDB || KGDB || FPEMUL */
+
 	ldw	TF_R19(%t3), %t4
 	/*	%r20(%t3) is used as a temporary and will be restored later */
 	/*	%r21(%t2) is used as a temporary and will be restored later */
@@ -900,7 +899,7 @@
 	 */
 	extru	%arg0, 5, 6, %r1
 	comib,=,n 4, %r1, L$emulate_sfu
-	comib,=,n 0xe, %r1, hppa_fpu_nop0
+	comib,=,n 0xe, %r1, hppa_fpu_emulate
 
 	/*
 	 * If the uid field in the instruction is not zero or one, indicating a
@@ -912,10 +911,7 @@
 
 	/*
 	 * If we're still here, this is a FPU coprocessor instruction.  That we
-	 * trapped to emulate it means one of three things.
-	 *
-	 * If we do not have a hardware FPU, we need to emulate this instr-
-	 * uction.
+	 * trapped to emulate it means one of two things.
 	 *
 	 * If we do have a hardware FPU but it is disabled, we trapped because
 	 * the current process' state is not loaded into the FPU.  We load that
@@ -926,14 +922,7 @@
 	 * emulate it.
 	 */
 
-	/*
-	 * As an optimization, hppa_fpu_bootstrap replaces this branch inst-
-	 * ruction with a nop if there is a hardware FPU.
-	 *
-	 * Otherwise, this is the branch to emulate an FPU coprocessor.
-	 */
-ALTENTRY(hppa_fpu_nop0)
-	b,n	L$emulate_fpu
+hppa_fpu_emulate:
 
 	/*
 	 * We have a hardware FPU.  If it is enabled,  branch to emulate the
@@ -1096,19 +1085,6 @@
 	fstds,ma %fr30, 8(%arg0)
 	fstds    %fr31, 0(%arg0)
 
-	ldo	-248(%arg0), %arg0
-	ldil	L%dcache_stride, %r1
-	ldw	R%dcache_stride(%r1), %r1
-	fdc,m	%r1(%arg0)
-	fdc,m	%r1(%arg0)
-	fdc,m	%r1(%arg0)
-	fdc,m	%r1(%arg0)
-	fdc,m	%r1(%arg0)
-	fdc,m	%r1(%arg0)
-	fdc,m	%r1(%arg0)
-	fdc,m	%r1(%arg0)
-	sync
-
 L$fpu_swap_in:
 
 	/*
@@ -1162,18 +1138,6 @@
 	fldds,ma -8(%arg1), %fr1
 	fldds     0(%arg1), %fr0	/* fr0 must be restored last */
 
-	ldil	L%dcache_stride, %r1
-	ldw	R%dcache_stride(%r1), %r1
-	fdc,m	%r1(%arg1)
-	fdc,m	%r1(%arg1)
-	fdc,m	%r1(%arg1)
-	fdc,m	%r1(%arg1)
-	fdc,m	%r1(%arg1)
-	fdc,m	%r1(%arg1)
-	fdc,m	%r1(%arg1)
-	fdc,m	%r1(%arg1)
-	sync
-
 L$fpu_swap_done:
 
 	/* Increment the switch count and return. */
@@ -2160,7 +2124,6 @@
 	 *
 	 * See similar #ifdefs in the syscall entry and exit code.
 	 */
-#if defined(DDB) || defined(KGDB) || defined(FPEMUL)
 	stw	%r4, TF_R4(%t3)
 	stw	%r5, TF_R5(%t3)
 	stw	%r6, TF_R6(%t3)
@@ -2176,7 +2139,7 @@
 	stw	%r16, TF_R16(%t3)
 	stw	%r17, TF_R17(%t3)
 	stw	%r18, TF_R18(%t3)
-#endif /* DDB || KGDB || FPEMUL */
+
 	stw	%t4, TF_R19(%t3)
 	stw	%r23,TF_R23(%t3)
 	stw	%r24,TF_R24(%t3)
--- a/sys/arch/hppa/hppa/trap.c	Tue Apr 17 19:25:17 2012 +0000
+++ b/sys/arch/hppa/hppa/trap.c	Sun Apr 29 23:04:36 2012 +0000
@@ -1,4 +1,4 @@
-/*	$NetBSD: trap.c,v 1.96.8.3 2012/03/11 01:52:21 mrg Exp $	*/
+/*	$NetBSD: trap.c,v 1.96.8.4 2012/04/29 23:04:40 mrg Exp $	*/
 
 /*-
  * Copyright (c) 2001, 2002 The NetBSD Foundation, Inc.
@@ -58,7 +58,7 @@
  */
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: trap.c,v 1.96.8.3 2012/03/11 01:52:21 mrg Exp $");
+__KERNEL_RCSID(0, "$NetBSD: trap.c,v 1.96.8.4 2012/04/29 23:04:40 mrg Exp $");
 
 /* #define INTRDEBUG */
 /* #define TRAPDEBUG */
@@ -631,21 +631,7 @@
 #endif
 
 	case T_EMULATION | T_USER:
-#ifdef FPEMUL
 		hppa_fpu_emulate(frame, l, opcode);
-#else  /* !FPEMUL */
-		/*
-		 * We don't have FPU emulation, so signal the
-		 * process with a SIGFPE.
-		 */
-		
-		KSI_INIT_TRAP(&ksi);
-		ksi.ksi_signo = SIGFPE;
-		ksi.ksi_code = SI_NOINFO;
-		ksi.ksi_trap = type;
-		ksi.ksi_addr = (void *)frame->tf_iioq_head;
-		trapsignal(l, &ksi);
-#endif /* !FPEMUL */
 		break;
 
 	case T_DATALIGN:
@@ -699,7 +685,7 @@
 		ksi.ksi_signo = SIGTRAP;
 		ksi.ksi_code = TRAP_TRACE;
 		ksi.ksi_trap = trapnum;
-		ksi.ksi_addr = (void *)frame->tf_iioq_head;
+		ksi.ksi_addr = (void *)(frame->tf_iioq_head & ~HPPA_PC_PRIV_MASK);
 #ifdef PTRACE
 		ss_clear_breakpoints(l);
 		if (opcode == SSBREAKPOINT)
@@ -707,7 +693,6 @@
 #endif
 		/* pass to user debugger */
 		trapsignal(l, &ksi);
- 
 		break;
 
 #ifdef PTRACE
@@ -718,7 +703,7 @@
 		ksi.ksi_signo = SIGTRAP;
 		ksi.ksi_code = TRAP_TRACE;
 		ksi.ksi_trap = trapnum;
-		ksi.ksi_addr = (void *)frame->tf_iioq_head;
+		ksi.ksi_addr = (void *)(frame->tf_iioq_head & ~HPPA_PC_PRIV_MASK);
 
                 /* pass to user debugger */
 		trapsignal(l, &ksi);
--- a/sys/arch/i386/acpi/acpi_wakecode.S	Tue Apr 17 19:25:17 2012 +0000
+++ b/sys/arch/i386/acpi/acpi_wakecode.S	Sun Apr 29 23:04:36 2012 +0000
@@ -1,4 +1,4 @@
-/*	$NetBSD: acpi_wakecode.S,v 1.14 2009/08/24 10:16:12 jmcneill Exp $	*/
+/*	$NetBSD: acpi_wakecode.S,v 1.14.16.1 2012/04/29 23:04:40 mrg Exp $	*/
 
 /*-
  * Copyright (c) 2002 The NetBSD Foundation, Inc.
@@ -165,7 +165,7 @@
 	movl	WAKEUP_r_cr3 + ACPI_WAKEUP_ADDR,%eax
 	movl	%eax,%cr3
 	movl	%cr0,%eax
-	orl	$(CR0_PE|CR0_PG|CR0_NE|CR0_TS|CR0_EM|CR0_MP|CR0_WP),%eax
+	orl	$(CR0_PE|CR0_PG|CR0_NE|CR0_TS|CR0_EM|CR0_MP|CR0_WP|CR0_AM),%eax
 	movl	%eax,%cr0
 
 	/* Flush the prefetch queue */
--- a/sys/arch/i386/conf/ALL	Tue Apr 17 19:25:17 2012 +0000
+++ b/sys/arch/i386/conf/ALL	Sun Apr 29 23:04:36 2012 +0000
@@ -1,4 +1,4 @@
-# $NetBSD: ALL,v 1.327.2.5 2012/03/11 01:52:21 mrg Exp $
+# $NetBSD: ALL,v 1.327.2.6 2012/04/29 23:04:40 mrg Exp $
 # From NetBSD: GENERIC,v 1.787 2006/10/01 18:37:54 bouyer Exp
 #
 # ALL machine description file
@@ -17,7 +17,7 @@
 
 options 	INCLUDE_CONFIG_FILE	# embed config file in kernel binary
 
-#ident 		"ALL-$Revision: 1.327.2.5 $"
+#ident 		"ALL-$Revision: 1.327.2.6 $"
 
 maxusers	64		# estimated number of users
 
@@ -158,6 +158,7 @@
 # The following two options can break /etc/fstab, so handle with care
 options 	DKWEDGE_METHOD_BSDLABEL	# Support disklabel entries as wedges
 options 	DKWEDGE_METHOD_MBR	# Support MBR partitions as wedges
+options 	DKWEDGE_METHOD_APPLE    # Support Apple partitions as wedges
 
 # File systems
 file-system 	FFS		# UFS
@@ -469,7 +470,8 @@
 elanpex*	at elansc?
 
 # Temperatures
-amdtemp* at pchb?			# AMD CPU Temperature sensors
+amdnb_misc* at pci?			# AMD NB Misc Configuration
+amdtemp* at amdnb_misc?			# AMD CPU Temperature sensors
 
 # PCI bridges
 amdpcib* at pci? dev ? function ?	# AMD 8111 PCI-ISA w/ HPET
@@ -776,7 +778,8 @@
 isp*	at pci? dev ? function ?	# Qlogic ISP [12]0x0 SCSI/FibreChannel
 mfi*	at pci? dev ? function ?	# LSI MegaRAID SAS
 mly*	at pci? dev ? function ?	# Mylex AcceleRAID and eXtremeRAID
-mpt*	at pci? dev ? function ?	# LSI Fusion SCSI/FC
+mpt*	at pci? dev ? function ?	# LSILogic 9x9 and 53c1030 (Fusion-MPT)
+mpii*	at pci? dev ? function ?	# LSI Logic Fusion-MPT II
 nca*	at pci? dev ? function ?	# Domex DMX-3191D
 njs*	at pci? dev ? function ?	# Workbit NinjaSCSI-32
 pcscp*	at pci? dev ? function ?	# AMD 53c974 PCscsi-PCI SCSI
@@ -2078,7 +2081,7 @@
 options HD64461VIDEO_DEBUG
 options HD64465PCMCIA_DEBUG
 options HDAUDIO_DEBUG
-options HDAUDIO_AFG_DEBUG
+options HDAFG_DEBUG
 options HDLCDEBUG
 options HIFN_DEBUG
 options HMEDEBUG
--- a/sys/arch/i386/conf/GENERIC	Tue Apr 17 19:25:17 2012 +0000
+++ b/sys/arch/i386/conf/GENERIC	Sun Apr 29 23:04:36 2012 +0000
@@ -1,4 +1,4 @@
-# $NetBSD: GENERIC,v 1.1058.2.3 2012/04/05 21:33:15 mrg Exp $
+# $NetBSD: GENERIC,v 1.1058.2.4 2012/04/29 23:04:40 mrg Exp $
 #
 # GENERIC machine description file
 #
@@ -22,7 +22,7 @@
 
 options 	INCLUDE_CONFIG_FILE	# embed config file in kernel binary
 
-#ident 		"GENERIC-$Revision: 1.1058.2.3 $"
+#ident 		"GENERIC-$Revision: 1.1058.2.4 $"
 
 maxusers	64		# estimated number of users
 
@@ -151,9 +151,10 @@
 # Wedge support
 options 	DKWEDGE_AUTODISCOVER	# Automatically add dk(4) instances
 options 	DKWEDGE_METHOD_GPT	# Supports GPT partitions as wedges
-# The following two options can break /etc/fstab, so handle with care
+# The following three options can break /etc/fstab, so handle with care
 #options 	DKWEDGE_METHOD_BSDLABEL	# Support disklabel entries as wedges
 #options 	DKWEDGE_METHOD_MBR	# Support MBR partitions as wedges
+#options	DKWEDGE_METHOD_APPLE    # Support Apple partitions as wedges
 
 file-system	FFS		# UFS
 file-system	NFS		# Network File System client
@@ -445,7 +446,8 @@
 elansc* at mainbus? bus ?		# AMD Elan SC520 System Controller
 
 # Temperatures
-amdtemp* at pchb?			# AMD CPU Temperature sensors
+amdnb_misc* at pci?			# AMD NB Misc Configuration
+amdtemp* at amdnb_misc?			# AMD CPU Temperature sensors
 
 # PCI bridges
 #amdpcib* at pci? dev ? function ?	# AMD 8111 PCI-ISA w/ HPET
@@ -740,7 +742,8 @@
 isp*	at pci? dev ? function ?	# Qlogic ISP [12]0x0 SCSI/FibreChannel
 mfi*	at pci? dev ? function ?	# LSI MegaRAID SAS
 mly*	at pci? dev ? function ?	# Mylex AcceleRAID and eXtremeRAID
-mpt*	at pci? dev ? function ?	# LSI Fusion SCSI/FC
+mpt*	at pci? dev ? function ?	# LSILogic 9x9 and 53c1030 (Fusion-MPT)
+mpii*	at pci? dev ? function ?	# LSI Logic Fusion-MPT II
 njs*	at pci? dev ? function ?	# Workbit NinjaSCSI-32
 pcscp*	at pci? dev ? function ?	# AMD 53c974 PCscsi-PCI SCSI
 siop*	at pci? dev ? function ?	# Symbios 53c8xx SCSI
@@ -1060,6 +1063,7 @@
 # CardBus network cards
 ath*	at cardbus? function ?	# Atheros 5210/5211/5212 802.11
 atw*	at cardbus? function ?	# ADMtek ADM8211 (802.11)
+bwi*	at cardbus? function ?	# Broadcom BCM43xx wireless
 ex*	at cardbus? function ?	# 3Com 3c575TX
 fxp*	at cardbus? function ?	# Intel i8255x
 ral*	at cardbus? function ?	# Ralink Technology RT25x0 802.11a/b/g
--- a/sys/arch/i386/conf/XEN3_DOM0	Tue Apr 17 19:25:17 2012 +0000
+++ b/sys/arch/i386/conf/XEN3_DOM0	Sun Apr 29 23:04:36 2012 +0000
@@ -1,4 +1,4 @@
-#	$NetBSD: XEN3_DOM0,v 1.57.2.3 2012/03/11 01:52:22 mrg Exp $
+#	$NetBSD: XEN3_DOM0,v 1.57.2.4 2012/04/29 23:04:40 mrg Exp $
 #
 #	XEN3_0: Xen 3.0 domain0 kernel
 
@@ -273,7 +273,8 @@
 
 # Hardware monitors
 
-amdtemp* at pchb?			# AMD CPU Temperature sensors
+amdnb_misc* at pci?			# AMD NB Misc Configuration
+amdtemp* at amdnb_misc?			# AMD CPU Temperature sensors
 
 # AMD 768 and 8111 power/ACPI controllers
 amdpm*	at pci? dev ? function ?	# RNG and SMBus 1.0 interface
@@ -464,7 +465,8 @@
 isp*	at pci? dev ? function ?	# Qlogic ISP [12]0x0 SCSI/FibreChannel
 mfi*	at pci? dev ? function ?	# LSI MegaRAID SAS
 mly*	at pci? dev ? function ?	# Mylex AcceleRAID and eXtremeRAID
-mpt*	at pci? dev ? function ?	# LSI Fusion SCSI/FC
+mpt*	at pci? dev ? function ?	# LSILogic 9x9 and 53c1030 (Fusion-MPT)
+mpii*	at pci? dev ? function ?	# LSI Logic Fusion-MPT II
 njs*	at pci? dev ? function ?	# Workbit NinjaSCSI-32
 pcscp*	at pci? dev ? function ?	# AMD 53c974 PCscsi-PCI SCSI
 siop*	at pci? dev ? function ?	# Symbios 53c8xx SCSI
--- a/sys/arch/i386/i386/compat_16_machdep.c	Tue Apr 17 19:25:17 2012 +0000
+++ b/sys/arch/i386/i386/compat_16_machdep.c	Sun Apr 29 23:04:36 2012 +0000
@@ -1,4 +1,4 @@
-/*	$NetBSD: compat_16_machdep.c,v 1.21 2010/11/06 11:40:24 uebayasi Exp $	*/
+/*	$NetBSD: compat_16_machdep.c,v 1.21.12.1 2012/04/29 23:04:40 mrg Exp $	*/
 
 /*-
  * Copyright (c) 1996, 1997, 1998, 2000 The NetBSD Foundation, Inc.
@@ -30,7 +30,7 @@
  */
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: compat_16_machdep.c,v 1.21 2010/11/06 11:40:24 uebayasi Exp $");
+__KERNEL_RCSID(0, "$NetBSD: compat_16_machdep.c,v 1.21.12.1 2012/04/29 23:04:40 mrg Exp $");
 
 #ifdef _KERNEL_OPT
 #include "opt_vm86.h"
@@ -260,7 +260,9 @@
 		/* NOTREACHED */
 	}
 
+	int svufpu = l->l_md.md_flags & MDL_USEDFPU;
 	buildcontext(l, sel, catcher, fp);
+	l->l_md.md_flags |= svufpu;
 
 	/* Remember that we're now on the signal stack. */
 	if (onstack)
--- a/sys/arch/i386/i386/genassym.cf	Tue Apr 17 19:25:17 2012 +0000
+++ b/sys/arch/i386/i386/genassym.cf	Sun Apr 29 23:04:36 2012 +0000
@@ -1,4 +1,4 @@
-#	$NetBSD: genassym.cf,v 1.90.6.1 2012/02/18 07:32:20 mrg Exp $
+#	$NetBSD: genassym.cf,v 1.90.6.2 2012/04/29 23:04:41 mrg Exp $
 
 #
 # Copyright (c) 1998, 2006, 2007, 2008 The NetBSD Foundation, Inc.
@@ -287,13 +287,11 @@
 define	CPU_INFO_WANT_PMAPLOAD	offsetof(struct cpu_info, ci_want_pmapload)
 define	CPU_INFO_TLBSTATE	offsetof(struct cpu_info, ci_tlbstate)
 define	TLBSTATE_VALID		TLBSTATE_VALID
-define	CPU_INFO_TLB_EVCNT	offsetof(struct cpu_info, ci_tlb_evcnt)
 define	CPU_INFO_CURLWP		offsetof(struct cpu_info, ci_curlwp)
 define	CPU_INFO_FPCURLWP	offsetof(struct cpu_info, ci_fpcurlwp)
 define	CPU_INFO_CURLDT		offsetof(struct cpu_info, ci_curldt)
 define	CPU_INFO_IDLELWP	offsetof(struct cpu_info, ci_data.cpu_idlelwp)
 define	CPU_INFO_PMAP		offsetof(struct cpu_info, ci_pmap)
-define	CPU_INFO_CPUMASK	offsetof(struct cpu_info, ci_cpumask)
 define	CPU_INFO_TSS		offsetof(struct cpu_info, ci_tss)
 define	CPU_INFO_TSS_SEL	offsetof(struct cpu_info, ci_tss_sel)
 define	CPU_INFO_ESP0		offsetof(struct cpu_info, ci_tss.tss_esp0)
--- a/sys/arch/i386/i386/locore.S	Tue Apr 17 19:25:17 2012 +0000
+++ b/sys/arch/i386/i386/locore.S	Sun Apr 29 23:04:36 2012 +0000
@@ -1,4 +1,4 @@
-/*	$NetBSD: locore.S,v 1.95.8.3 2012/03/06 18:26:37 mrg Exp $	*/
+/*	$NetBSD: locore.S,v 1.95.8.4 2012/04/29 23:04:41 mrg Exp $	*/
 
 /*
  * Copyright-o-rama!
@@ -129,7 +129,7 @@
  */
 
 #include <machine/asm.h>
-__KERNEL_RCSID(0, "$NetBSD: locore.S,v 1.95.8.3 2012/03/06 18:26:37 mrg Exp $");
+__KERNEL_RCSID(0, "$NetBSD: locore.S,v 1.95.8.4 2012/04/29 23:04:41 mrg Exp $");
 
 #include "opt_compat_oldboot.h"
 #include "opt_ddb.h"
@@ -682,7 +682,7 @@
  	 */
 	movl	%cr0,%eax		# get control word
 					# enable paging & NPX emulation
-	orl	$(CR0_PE|CR0_PG|CR0_NE|CR0_TS|CR0_EM|CR0_MP),%eax
+	orl	$(CR0_PE|CR0_PG|CR0_NE|CR0_TS|CR0_EM|CR0_MP|CR0_WP|CR0_AM),%eax
 	movl	%eax,%cr0		# and page NOW!
 
 	pushl	$begin			# jump to high mem
--- a/sys/arch/i386/i386/mptramp.S	Tue Apr 17 19:25:17 2012 +0000
+++ b/sys/arch/i386/i386/mptramp.S	Sun Apr 29 23:04:36 2012 +0000
@@ -1,4 +1,4 @@
-/*	$NetBSD: mptramp.S,v 1.22 2010/07/28 17:05:51 jym Exp $	*/
+/*	$NetBSD: mptramp.S,v 1.22.12.1 2012/04/29 23:04:41 mrg Exp $	*/
 
 /*-
  * Copyright (c) 2000 The NetBSD Foundation, Inc.
@@ -76,7 +76,7 @@
  */
 
 #include <machine/asm.h>
-__KERNEL_RCSID(0, "$NetBSD: mptramp.S,v 1.22 2010/07/28 17:05:51 jym Exp $");
+__KERNEL_RCSID(0, "$NetBSD: mptramp.S,v 1.22.12.1 2012/04/29 23:04:41 mrg Exp $");
 	
 #include "opt_mpbios.h"		/* for MPDEBUG */
 		
@@ -174,7 +174,7 @@
         movl    %ecx,%cr3               # load ptd addr into mmu
         movl    %cr0,%eax               # get control word
                                         # enable paging & NPX emulation
-        orl     $(CR0_PE|CR0_PG|CR0_NE|CR0_TS|CR0_EM|CR0_MP|CR0_WP),%eax
+        orl     $(CR0_PE|CR0_PG|CR0_NE|CR0_TS|CR0_EM|CR0_MP|CR0_WP|CR0_AM),%eax
         movl    %eax,%cr0               # and page NOW!
 
 #ifdef MPDEBUG
@@ -271,8 +271,6 @@
 	HALTT(0x30,%ecx)	
 	pushl	%ecx
 	call	_C_LABEL(cpu_hatch)
-	HALT(0x33)
-	jmp	_C_LABEL(idle_loop)
 	
 	.data
 _C_LABEL(mp_pdirpa):
--- a/sys/arch/i386/include/param.h	Tue Apr 17 19:25:17 2012 +0000
+++ b/sys/arch/i386/include/param.h	Sun Apr 29 23:04:36 2012 +0000
@@ -1,4 +1,4 @@
-/*	$NetBSD: param.h,v 1.72.14.1 2012/02/18 07:32:22 mrg Exp $	*/
+/*	$NetBSD: param.h,v 1.72.14.2 2012/04/29 23:04:41 mrg Exp $	*/
 
 /*-
  * Copyright (c) 1990 The Regents of the University of California.
@@ -41,6 +41,13 @@
  * Machine dependent constants for Intel 386.
  */
 
+/*
+ * MAXCPUS must be defined before cpu.h inclusion.  Note: i386 might
+ * support more CPUs, but due to the limited KVA space available on
+ * i386, such support would be inefficient.  Use amd64 instead.
+ */
+#define	MAXCPUS		32
+
 #ifdef _KERNEL
 #include <machine/cpu.h>
 #endif
--- a/sys/arch/ia64/conf/GENERIC	Tue Apr 17 19:25:17 2012 +0000
+++ b/sys/arch/ia64/conf/GENERIC	Sun Apr 29 23:04:36 2012 +0000
@@ -1,4 +1,4 @@
-# $NetBSD: GENERIC,v 1.4 2010/05/17 11:41:28 kiyohara Exp $
+# $NetBSD: GENERIC,v 1.4.12.1 2012/04/29 23:04:41 mrg Exp $
 #
 # GENERIC machine description file
 #
@@ -22,7 +22,7 @@
 
 options 	INCLUDE_CONFIG_FILE	# embed config file in kernel binary
 
-#ident 		"GENERIC-$Revision: 1.4 $"
+#ident 		"GENERIC-$Revision: 1.4.12.1 $"
 
 maxusers	32		# estimated number of users
 
@@ -45,8 +45,6 @@
 options 	DDB_HISTORY_SIZE=512	# enable history editing in DDB
 #options 	KGDB		# remote debugger
 #options 	KGDB_DEVNAME="\"com\"",KGDB_DEVADDR=0x3f8,KGDB_DEVRATE=9600
-#options		MALLOC_DEBUG
-#options		MALLOCLOG
 makeoptions	DEBUG="-g"	# compile full symbol table
 
 # File systems
--- a/sys/arch/ia64/conf/GENERIC.SKI	Tue Apr 17 19:25:17 2012 +0000
+++ b/sys/arch/ia64/conf/GENERIC.SKI	Sun Apr 29 23:04:36 2012 +0000
@@ -1,4 +1,4 @@
-# $NetBSD: GENERIC.SKI,v 1.7 2010/11/23 11:14:00 hannken Exp $
+# $NetBSD: GENERIC.SKI,v 1.7.12.1 2012/04/29 23:04:41 mrg Exp $
 #
 # GENERIC machine description file
 #
@@ -22,7 +22,7 @@
 
 options 	INCLUDE_CONFIG_FILE	# embed config file in kernel binary
 
-#ident 		"GENERIC-$Revision: 1.7 $"
+#ident 		"GENERIC-$Revision: 1.7.12.1 $"
 
 maxusers	32		# estimated number of users
 
@@ -44,8 +44,6 @@
 #options 	DDB_HISTORY_SIZE=512	# enable history editing in DDB
 #options 	KGDB		# remote debugger
 #options 	KGDB_DEVNAME="\"com\"",KGDB_DEVADDR=0x3f8,KGDB_DEVRATE=9600
-#options		MALLOC_DEBUG
-#options		MALLOCLOG
 makeoptions	DEBUG="-g"	# compile full symbol table
 
 # File systems
--- a/sys/arch/powerpc/booke/dev/pq3etsec.c	Tue Apr 17 19:25:17 2012 +0000
+++ b/sys/arch/powerpc/booke/dev/pq3etsec.c	Sun Apr 29 23:04:36 2012 +0000
@@ -1,4 +1,4 @@
-/*	$NetBSD: pq3etsec.c,v 1.9.6.1 2012/02/24 09:11:32 mrg Exp $	*/
+/*	$NetBSD: pq3etsec.c,v 1.9.6.2 2012/04/29 23:04:41 mrg Exp $	*/
 /*-
  * Copyright (c) 2010, 2011 The NetBSD Foundation, Inc.
  * All rights reserved.
@@ -38,7 +38,7 @@
 
 #include <sys/cdefs.h>
 
-__KERNEL_RCSID(0, "$NetBSD: pq3etsec.c,v 1.9.6.1 2012/02/24 09:11:32 mrg Exp $");
+__KERNEL_RCSID(0, "$NetBSD: pq3etsec.c,v 1.9.6.2 2012/04/29 23:04:41 mrg Exp $");
 
 #include <sys/param.h>
 #include <sys/cpu.h>
@@ -501,6 +501,8 @@
 	sc->sc_macstnaddr2 = etsec_read(sc, MACSTNADDR2);
 	sc->sc_macstnaddr1 = etsec_read(sc, MACSTNADDR1);
 	sc->sc_rctrl = RCTRL_DEFAULT;
+	sc->sc_ecntrl = etsec_read(sc, ECNTRL);
+	sc->sc_maccfg1 = etsec_read(sc, MACCFG1);
 	sc->sc_maccfg2 = MACCFG2_DEFAULT;
 
 	if (sc->sc_macstnaddr1 == 0 && sc->sc_macstnaddr2 == 0) {
--- a/sys/arch/powerpc/include/cpu.h	Tue Apr 17 19:25:17 2012 +0000
+++ b/sys/arch/powerpc/include/cpu.h	Sun Apr 29 23:04:36 2012 +0000
@@ -1,4 +1,4 @@
-/*	$NetBSD: cpu.h,v 1.88.6.2 2012/04/05 21:33:18 mrg Exp $	*/
+/*	$NetBSD: cpu.h,v 1.88.6.3 2012/04/29 23:04:41 mrg Exp $	*/
 
 /*
  * Copyright (C) 1999 Wolfgang Solfrank.
@@ -213,8 +213,12 @@
 	return ci;
 }
 
+#ifdef __clang__
+#define	curlwp			(curcpu()->ci_curlwp)
+#else
 register struct lwp *powerpc_curlwp __asm("r13");
 #define	curlwp			powerpc_curlwp
+#endif
 #define curpcb			(curcpu()->ci_curpcb)
 #define curpm			(curcpu()->ci_curpm)
 
--- a/sys/arch/sandpoint/conf/GENERIC	Tue Apr 17 19:25:17 2012 +0000
+++ b/sys/arch/sandpoint/conf/GENERIC	Sun Apr 29 23:04:36 2012 +0000
@@ -1,4 +1,4 @@
-# $NetBSD: GENERIC,v 1.61.2.3 2012/03/11 01:52:24 mrg Exp $
+# $NetBSD: GENERIC,v 1.61.2.4 2012/04/29 23:04:41 mrg Exp $
 #
 # machine description file for GENERIC NAS
 # 
@@ -22,7 +22,7 @@
 
 options 	INCLUDE_CONFIG_FILE	# embed config file in kernel binary
 
-#ident 		"GENERIC-$Revision: 1.61.2.3 $"
+#ident 		"GENERIC-$Revision: 1.61.2.4 $"
 
 maxusers	32
 
@@ -262,6 +262,7 @@
 cd*	at scsibus? target ? lun ?	# SCSI CD-ROM drives
 
 atapibus* at atapi?
+sd*	at atapibus? drive ? flags 0x0000	# ATAPI disk drives
 cd*	at atapibus? drive ? flags 0x0000	# ATAPI CD-ROM drives
 
 #
--- a/sys/arch/sandpoint/sandpoint/satmgr.c	Tue Apr 17 19:25:17 2012 +0000
+++ b/sys/arch/sandpoint/sandpoint/satmgr.c	Sun Apr 29 23:04:36 2012 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: satmgr.c,v 1.13.4.2 2012/02/24 09:11:33 mrg Exp $ */
+/* $NetBSD: satmgr.c,v 1.13.4.3 2012/04/29 23:04:41 mrg Exp $ */
 
 /*-
  * Copyright (c) 2010 The NetBSD Foundation, Inc.
@@ -120,25 +120,30 @@
 static void txintr(struct satmgr_softc *);
 static void startoutput(struct satmgr_softc *);
 static void swintr(void *);
+static void minit(struct satmgr_softc *);
 static void sinit(struct satmgr_softc *);
 static void qinit(struct satmgr_softc *);
 static void iinit(struct satmgr_softc *);
 static void kreboot(struct satmgr_softc *);
+static void mreboot(struct satmgr_softc *);
 static void sreboot(struct satmgr_softc *);
 static void qreboot(struct satmgr_softc *);
 static void ireboot(struct satmgr_softc *);
 static void kpwroff(struct satmgr_softc *);
+static void mpwroff(struct satmgr_softc *);
 static void spwroff(struct satmgr_softc *);
 static void qpwroff(struct satmgr_softc *);
 static void dpwroff(struct satmgr_softc *);
 static void ipwroff(struct satmgr_softc *);
 static void kbutton(struct satmgr_softc *, int);
+static void mbutton(struct satmgr_softc *, int);
 static void sbutton(struct satmgr_softc *, int);
 static void qbutton(struct satmgr_softc *, int);
 static void dbutton(struct satmgr_softc *, int);
 static void ibutton(struct satmgr_softc *, int);
 static void idosync(void *);
 static void iprepcmd(struct satmgr_softc *, int, int, int, int, int, int);
+static int  mbtnintr(void *);
 static void guarded_pbutton(void *);
 static void sched_sysmon_pbutton(void *);
 
@@ -154,6 +159,7 @@
     { "dlink",    NULL,  NULL,    dpwroff, dbutton },
     { "iomega",   iinit, ireboot, ipwroff, ibutton },
     { "kurobox",  NULL,  kreboot, kpwroff, kbutton },
+    { "kurot4",   minit, mreboot, mpwroff, mbutton },
     { "qnap",     qinit, qreboot, qpwroff, qbutton },
     { "synology", sinit, sreboot, spwroff, sbutton }
 };
@@ -300,6 +306,10 @@
 			satmgr_sysctl_fanhigh, 0, NULL, 0,
 			CTL_CREATE, CTL_EOL);
 	}
+	else if (strcmp(ops->family, "kurot4") == 0) {
+		intr_establish(2 + I8259_ICU,
+			IST_LEVEL, IPL_SERIAL, mbtnintr, sc);
+	}
 
 	md_reboot = satmgr_reboot;	/* cpu_reboot() hook */
 	if (ops->init != NULL)
@@ -436,6 +446,24 @@
 		goto again;
 }
 
+static void
+recv_sat_len(struct satmgr_softc *sc, char *buf, int len)
+{
+	int lsr;
+
+	lsr = CSR_READ(sc, LSR);
+	while (len > 0 && (lsr & LSR_RXRDY)) {
+		if (lsr & (LSR_BI | LSR_FE | LSR_PE)) {
+			(void) CSR_READ(sc, RBR);
+			lsr = CSR_READ(sc, LSR);
+			continue;
+		}
+		*buf++ = CSR_READ(sc, RBR);
+		len -= 1;
+		lsr = CSR_READ(sc, LSR);
+	}
+}
+
 static int
 satopen(dev_t dev, int flags, int fmt, struct lwp *l)
 {
@@ -719,14 +747,14 @@
 kreboot(struct satmgr_softc *sc)
 {
 
-	send_sat(sc, "CCGG");
+	send_sat(sc, "CCGG"); /* perform reboot */
 }
 
 static void
 kpwroff(struct satmgr_softc *sc)
 {
 
-	send_sat(sc, "EEGG");
+	send_sat(sc, "EEGG"); /* force power off */
 }
 
 static void
@@ -949,6 +977,81 @@
 	 */
 }
 
+static void msattalk(struct satmgr_softc *, const char *, char *, int);
+
+static void
+msattalk(struct satmgr_softc *sc, const char *cmd, char *rep, int n)
+{
+	int len, i;
+	uint8_t pa;
+
+	if (cmd[0] != 0x80)
+		len = 2 + cmd[0]; /* cmd[0] is data portion length */
+	else
+		len = 2; /* read report */
+
+	for (i = 0, pa = 0; i < len; i++)
+		pa += cmd[i];
+	pa = 0 - pa; /* parity formula */
+
+	CSR_WRITE(sc, IER, 0);
+	send_sat_len(sc, cmd, len);
+	send_sat_len(sc, &pa, 1);
+	 DELAY(2000); /* XXX */
+	recv_sat_len(sc, rep, n);
+	 DELAY(2000); /* XXX */
+	CSR_WRITE(sc, IER, 0x7f);
+}
+
+static void
+minit(struct satmgr_softc *sc)
+{
+	char report[4];
+
+	msattalk(sc, "\x00\x03", report, 4);	/* boot has completed */
+}
+
+static void
+mreboot(struct satmgr_softc *sc)
+{
+	char report[4];
+
+	msattalk(sc, "\x01\x35\x00", report, 4); /* stop watchdog timer */
+	msattalk(sc, "\x00\x0c", report, 4);	 /* shutdown in progress */
+	msattalk(sc, "\x00\x03", report, 4);	 /* boot has completed */
+	msattalk(sc, "\x00\x0e", report, 4);	 /* perform reboot */
+}
+
+static void
+mpwroff(struct satmgr_softc *sc)
+{
+	char report[4];
+
+	msattalk(sc, "\x01\x35\x00", report, 4); /* stop watchdog timer */
+	msattalk(sc, "\x00\x0c", report, 4);	 /* shutdown in progress */
+	msattalk(sc, "\x00\x03", report, 4);	 /* boot has completed */
+	msattalk(sc, "\x00\x06", report, 4);	 /* force power off */
+}
+
+static void
+mbutton(struct satmgr_softc *sc, int ch)
+{
+	/* can do nothing */
+}
+
+static int
+mbtnintr(void *arg)
+{
+	/* notified after 3 seconds guard time */
+	struct satmgr_softc *sc = arg;
+	char report[4];
+
+	msattalk(sc, "\x80\x36", report, 4);
+	if ((report[2] & 01) == 0) /* power button depressed */
+		sysmon_task_queue_sched(0, sched_sysmon_pbutton, sc);
+	return 1;
+}
+
 static void
 guarded_pbutton(void *arg)
 {
@@ -956,7 +1059,7 @@
 
 	/* we're now in callout(9) context */
 	sysmon_task_queue_sched(0, sched_sysmon_pbutton, sc);
-	send_sat(sc, "UU");
+	send_sat(sc, "UU"); /* make front panel LED flashing */
 }
 
 static void
--- a/sys/arch/sandpoint/stand/altboot/README.altboot	Tue Apr 17 19:25:17 2012 +0000
+++ b/sys/arch/sandpoint/stand/altboot/README.altboot	Sun Apr 29 23:04:36 2012 +0000
@@ -1,6 +1,6 @@
 /// notes about altboot ///
 
-$NetBSD: README.altboot,v 1.6.4.1 2012/02/18 07:33:04 mrg Exp $
+$NetBSD: README.altboot,v 1.6.4.2 2012/04/29 23:04:42 mrg Exp $
 
 Altboot is a functional bridge to fill the gap between a NAS product
 custom bootloader and the NetBSD kernel startup environment.  Altboot
@@ -48,6 +48,10 @@
 
    PPCBoot 2.0.0-A9 (Feb 13 2006 - 14:56:11)
 
+- KURO-BOX/T4 vendor custom U-Boot
+
+   U-Boot 2009.06-BUFFALO-svn1376 (Jul 11 2009 - 04:11:01) KURO-NAS/T4
+
 The standard use of altboot is to invoke it with a short script from
 U-Boot/PPCboot, where the altboot.bin image is stored in an unoccupied 128KB
 section of the target's HW NOR flash.  Combined with standard
@@ -57,11 +61,11 @@
 as a functional extension for them.
 
 In case the firmware was crippled by the vendor so that it only boots
-Linux U-Boot images (D-Link), you can still use altboot by uploading
-altboot.img instead of the Linux kernel.
+Linux U-Boot images (D-Link, Synology 2007), you can still use altboot by
+overwriting the Linux kernel with altboot.img.
 
 Altboot passes the following bootinfo records to the NetBSD/sandpoint
-kernel.
+kernel:
 - processor clock tick value driving MPC8241/8245.
 - serial console selection.
 - booted kernel filename and which device it was fetched from.
@@ -100,7 +104,12 @@
 Multiple arguments may be specified at once, although not all combinations
 make sense. The format of an altboot command line is:
 
-  [[<bootargs> ...] <devicename>:[<bootfile>]]
+  [[<bootargs> ...] <devicename>:[<bootfile>] ...]
+
+Multiple boot devices and/or paths may be specified, which are booted one
+after another until success. When no boot device is specified altboot tries
+to boot from all disk devices with a valid NetBSD disklabel, starting with
+unit 0.
 
 The following device names are supported:
 - tftp			boot from TFTP (address retrieved by DHCP)
--- a/sys/arch/sandpoint/stand/altboot/brdsetup.c	Tue Apr 17 19:25:17 2012 +0000
+++ b/sys/arch/sandpoint/stand/altboot/brdsetup.c	Sun Apr 29 23:04:36 2012 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: brdsetup.c,v 1.23.4.1 2012/02/18 07:33:04 mrg Exp $ */
+/* $NetBSD: brdsetup.c,v 1.23.4.2 2012/04/29 23:04:42 mrg Exp $ */
 
 /*-
  * Copyright (c) 2008 The NetBSD Foundation, Inc.
@@ -46,6 +46,7 @@
     void xxx ## setup(struct brdprop *); \
     void xxx ## brdfix(struct brdprop *); \
     void xxx ## pcifix(struct brdprop *); \
+    void xxx ## launch(struct brdprop *); \
     void xxx ## reset(void)
 
 BRD_DECL(mot);
@@ -56,6 +57,7 @@
 BRD_DECL(iomega);
 BRD_DECL(dlink);
 BRD_DECL(nhnas);
+BRD_DECL(kurot4);
 
 static void brdfixup(void);
 static void setup(void);
@@ -118,28 +120,28 @@
 	BRD_SANDPOINTX3,
 	0,
 	"com", 0x3f8, 115200,
-	motsetup, motbrdfix, motpcifix, NULL },
+	motsetup, motbrdfix, motpcifix, NULL, NULL },
     {
 	"encpp1",
 	"EnCore PP1",
 	BRD_ENCOREPP1,
 	0,
 	"com", 0x3f8, 115200,
-	encsetup, encbrdfix, encpcifix, NULL },
+	encsetup, encbrdfix, encpcifix, NULL, NULL },
     {
 	"kurobox",
 	"KuroBox",
 	BRD_KUROBOX,
 	0,
 	"eumb", 0x4600, 57600,
-	kurosetup, kurobrdfix, NULL, kuroreset },
+	kurosetup, kurobrdfix, NULL, NULL, kuroreset },
     {
 	"synology",
-	"Synology DS",
+	"Synology CS/DS/RS",
 	BRD_SYNOLOGY,
 	0,
 	"eumb", 0x4500, 115200,
-	synosetup, synobrdfix, NULL, synoreset },
+	synosetup, synobrdfix, synopcifix, synolaunch, synoreset },
     {
 	"qnap",
 	"QNAP TS",
@@ -147,35 +149,42 @@
 	33164691,	/* Linux source says 33000000, but the Synology  */
 			/* clock value delivers a much better precision. */
 	"eumb", 0x4500, 115200,
-	NULL, qnapbrdfix, NULL, qnapreset },
+	NULL, qnapbrdfix, NULL, NULL, qnapreset },
     {
 	"iomega",
 	"IOMEGA StorCenter G2",
 	BRD_STORCENTER,
 	0,
 	"eumb", 0x4500, 115200,
-	NULL, iomegabrdfix, NULL, iomegareset },
+	NULL, iomegabrdfix, NULL, NULL, iomegareset },
     {
 	"dlink",
 	"D-Link DSM-G600",
 	BRD_DLINKDSM,
 	33000000,
 	"eumb", 0x4500, 9600,
-	NULL, dlinkbrdfix, NULL, NULL },
+	NULL, dlinkbrdfix, NULL, NULL, NULL },
     {
 	"nhnas",
 	"Netronix NH-230/231",
 	BRD_NH230NAS,
 	33000000,
 	"eumb", 0x4500, 9600,
-	NULL, nhnasbrdfix, NULL, nhnasreset },
+	NULL, nhnasbrdfix, NULL, NULL, nhnasreset },
+    {
+	"kurot4",
+	"KuroBox/T4",
+	BRD_KUROBOXT4,
+	32768000,
+	"eumb", 0x4600, 57600,
+	NULL, kurot4brdfix, NULL, NULL, NULL },
     {
 	"unknown",
 	"Unknown board",
 	BRD_UNKNOWN,
 	0,
 	"eumb", 0x4500, 115200,
-	NULL, NULL, NULL, NULL }, /* must be the last */
+	NULL, NULL, NULL, NULL, NULL }, /* must be the last */
 };
 
 static struct brdprop *brdprop;
@@ -207,7 +216,7 @@
 	char *consname;
 	int consport;
 	uint32_t extclk;
-	unsigned pchb, pcib, dev11, dev13, dev15, dev16, val;
+	unsigned pchb, pcib, dev11, dev12, dev13, dev15, dev16, val;
 	extern struct btinfo_memory bi_mem;
 	extern struct btinfo_console bi_cons;
 	extern struct btinfo_clock bi_clk;
@@ -229,6 +238,7 @@
 	busclock = 0;
 
 	dev11 = pcimaketag(0, 11, 0);
+	dev12 = pcimaketag(0, 12, 0);
 	dev13 = pcimaketag(0, 13, 0);
 	dev15 = pcimaketag(0, 15, 0);
 	dev16 = pcimaketag(0, 16, 0);
@@ -243,7 +253,10 @@
 	}
 	else if (PCI_CLASS(pcicfgread(dev11, PCI_CLASS_REG)) == PCI_CLASS_ETH) {
 		/* ADMtek AN985 (tlp) or RealTek 8169S (re) at dev 11 */
-		brdtype = BRD_KUROBOX;
+		if (PCI_VENDOR(pcicfgread(dev12, PCI_ID_REG)) != 0x1095)
+			brdtype = BRD_KUROBOX;
+		else
+			brdtype = BRD_KUROBOXT4;
 	}
 	else if (PCI_VENDOR(pcicfgread(dev15, PCI_ID_REG)) == 0x11ab) {
 		/* SKnet/Marvell (sk) at dev 15 */
@@ -353,6 +366,15 @@
 }
 
 void
+launchfixup()
+{
+
+	if (brdprop->launch == NULL)
+		return;
+	(*brdprop->launch)(brdprop);
+}
+
+void
 encsetup(struct brdprop *brd)
 {
 
@@ -695,6 +717,50 @@
 }
 
 void
+synopcifix(struct brdprop *brd)
+{
+	static const char csmodel[4][7] = {
+		"CS406e", "CS406", "RS406", "CS407e"
+	};
+	volatile uint8_t *cpld = (volatile uint8_t *)0xff000000;
+	uint8_t pwrstate;
+
+	if (nata > 1) {
+		/*
+		 * CS/RS stations power-up their disks one after another.
+		 * We have to watch over the current power state in a CPLD
+		 * register, until all disks become available.
+		 */
+		printf("CPLD V1.%d for model %s\n", cpld[2] & 3,
+		    csmodel[(cpld[2] & 0x0c) >> 2]);
+		cpld[0] = 0x00; /* all drive LEDs blinking yellow */
+		do {
+			delay(1000 * 1000);
+			pwrstate = cpld[1];
+			printf("Power state: %02x\r", pwrstate);
+		} while (pwrstate != 0xff);
+		putchar('\n');
+	}
+}
+
+void
+synolaunch(struct brdprop *brd)
+{
+	volatile uint8_t *cpld = (volatile uint8_t *)0xff000000;
+	struct dkdev_ata *sata1, *sata2;
+
+	if (nata > 1) {
+		/* enable drive LEDs for active disk drives on CS/RS models */
+		sata1 = lata[0].drv;
+		sata2 = lata[1].drv;
+		cpld[0] = (sata1->presense[0] ? 0x80 : 0xc0) |
+		    (sata1->presense[1] ? 0x20 : 0x30) |
+		    (sata2->presense[0] ? 0x08 : 0x0c) |
+		    (sata2->presense[1] ? 0x02 : 0x03);
+	}
+}
+
+void
 synoreset()
 {
 
@@ -764,6 +830,13 @@
 }
 
 void
+kurot4brdfix(struct brdprop *brd)
+{
+
+	init_uart(uart2base, 38400, LCR_8BITS | LCR_PEVEN);
+}
+
+void
 _rtt(void)
 {
 	uint32_t msr;
--- a/sys/arch/sandpoint/stand/altboot/dsk.c	Tue Apr 17 19:25:17 2012 +0000
+++ b/sys/arch/sandpoint/stand/altboot/dsk.c	Sun Apr 29 23:04:36 2012 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: dsk.c,v 1.11.4.1 2012/02/18 07:33:05 mrg Exp $ */
+/* $NetBSD: dsk.c,v 1.11.4.2 2012/04/29 23:04:42 mrg Exp $ */
 
 /*-
  * Copyright (c) 2010 The NetBSD Foundation, Inc.
@@ -77,12 +77,12 @@
 static char *mkident(char *, int);
 static void set_xfermode(struct dkdev_ata *, int);
 static void decode_dlabel(struct disk *, char *);
+static struct disklabel *search_dmagic(char *);
 static int lba_read(struct disk *, int64_t, int, void *);
 static void issue48(struct dvata_chan *, int64_t, int);
 static void issue28(struct dvata_chan *, int64_t, int);
 static struct disk *lookup_disk(int);
 
-#define MAX_UNITS 8
 static struct disk ldisk[MAX_UNITS];
 
 int
@@ -306,7 +306,6 @@
         struct mbr_partition *mp, *bsdp;
 	struct disklabel *dlp;
 	struct partition *pp;
-	char *dp;
 	int i, first, rf_offset;
 
 	bsdp = NULL;
@@ -324,39 +323,26 @@
 	rf_offset = 0;
 	first = (bsdp) ? bswap32(bsdp->mbrp_start) : 0;
 	(*d->lba_read)(d, first + LABELSECTOR, 1, iobuf);
-	dp = iobuf /* + LABELOFFSET */;
-	for (i = 0; i < 512 - sizeof(struct disklabel); i++, dp += 4) {
-		dlp = (struct disklabel *)dp;
-		if (dlp->d_magic == DISKMAGIC && dlp->d_magic2 == DISKMAGIC) {
-			if (dlp->d_partitions[0].p_fstype == FS_RAID) {
-				printf("%s%c: raid\n", d->xname, i + 'a');
-				snprintf(d->xname, sizeof(d->xname), "raid.");
-				rf_offset = dlp->d_partitions[0].p_offset +
-				    RF_PROTECTED_SECTORS;
-				(*d->lba_read)(d, rf_offset + LABELSECTOR, 1,
-				    iobuf);
-				dp = iobuf /* + LABELOFFSET */;
-				for (i = 0; i < 512 - sizeof(struct disklabel); i++, dp += 4) {
-					dlp = (struct disklabel *)dp;
-					if (dlp->d_magic == DISKMAGIC &&
-					    dlp->d_magic2 == DISKMAGIC)
-						goto found;
-				}
-			} else	/* Not RAID */
-				goto found;
-		}
+	dlp = search_dmagic(iobuf);
+	if (dlp == NULL)
+		goto notfound;
+	if (dlp->d_partitions[0].p_fstype == FS_RAID) {
+		printf("%s%c: raid\n", d->xname, 0 + 'a');
+		snprintf(d->xname, sizeof(d->xname), "raid.");
+		rf_offset
+		    = dlp->d_partitions[0].p_offset + RF_PROTECTED_SECTORS;
+		(*d->lba_read)(d, rf_offset + LABELSECTOR, 1, iobuf);
+		dlp = search_dmagic(iobuf);
+		if (dlp == NULL)
+			goto notfound;
 	}
-	d->dlabel = NULL;
-	printf("%s: no disklabel\n", d->xname);
-	return;
-  found:
 	for (i = 0; i < dlp->d_npartitions; i += 1) {
 		const char *type;
 		pp = &dlp->d_partitions[i];
 		pp->p_offset += rf_offset;
 		type = NULL;
 		switch (pp->p_fstype) {
-		case FS_SWAP: /* swap */
+		case FS_SWAP:
 			type = "swap";
 			break;
 		case FS_BSDFFS:
@@ -372,6 +358,25 @@
 	}
 	d->dlabel = allocaligned(sizeof(struct disklabel), 4);
 	memcpy(d->dlabel, dlp, sizeof(struct disklabel));
+	return;
+  notfound:
+	d->dlabel = NULL;
+	printf("%s: no disklabel\n", d->xname);
+	return;
+}
+
+struct disklabel *
+search_dmagic(char *dp)
+{
+	int i;
+	struct disklabel *dlp;
+
+	for (i = 0; i < 512 - sizeof(struct disklabel); i += 4, dp += 4) {
+		dlp = (struct disklabel *)dp;
+		if (dlp->d_magic == DISKMAGIC && dlp->d_magic2 == DISKMAGIC)
+			return dlp;
+	}
+	return NULL;
 }
 
 static void
@@ -456,7 +461,18 @@
 lookup_disk(int unit)
 {
 
-	return &ldisk[unit];
+	return (unit >= 0 && unit < MAX_UNITS) ? &ldisk[unit] : NULL;
+}
+
+int
+dlabel_valid(int unit)
+{
+	struct disk *dsk;
+
+	dsk = lookup_disk(unit);
+	if (dsk == NULL)
+		return NULL;
+	return dsk->dlabel != NULL;
 }
 
 int
@@ -481,10 +497,10 @@
 
 	if ((d = lookup_disk(unit)) == NULL)
 		return ENXIO;
-	f->f_devdata = d;
 	if ((dlp = d->dlabel) == NULL || part >= dlp->d_npartitions)
 		return ENXIO;
 	d->part = part;
+	f->f_devdata = d;
 
 	snprintf(bi_path.bootpath, sizeof(bi_path.bootpath), name);
 	if (dlp->d_partitions[part].p_fstype == FS_BSDFFS) {
--- a/sys/arch/sandpoint/stand/altboot/globals.h	Tue Apr 17 19:25:17 2012 +0000
+++ b/sys/arch/sandpoint/stand/altboot/globals.h	Sun Apr 29 23:04:36 2012 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: globals.h,v 1.14.4.1 2012/02/18 07:33:05 mrg Exp $ */
+/* $NetBSD: globals.h,v 1.14.4.2 2012/04/29 23:04:42 mrg Exp $ */
 
 #ifdef DEBUG
 #define	DPRINTF(x)	printf x
@@ -22,6 +22,7 @@
 #define BRD_STORCENTER		103
 #define BRD_DLINKDSM		104
 #define BRD_NH230NAS		105
+#define BRD_KUROBOXT4		106
 #define BRD_UNKNOWN		-1
 
 struct brdprop {
@@ -35,6 +36,7 @@
 	void (*setup)(struct brdprop *);
 	void (*brdfix)(struct brdprop *);
 	void (*pcifix)(struct brdprop *);
+	void (*launch)(struct brdprop *);
 	void (*reset)(void);
 };
 
@@ -78,8 +80,14 @@
 	unsigned pvd;	/* device ID */
 	void *drv;	/* driver */
 };
+extern struct pcidev lata[2];
+extern struct pcidev lnif[2];
+extern struct pcidev lusb[3];
+extern int nata, nnif, nusb;
+
 void  pcisetup(void);
 void  pcifixup(void);
+void  launchfixup(void);
 unsigned pcimaketag(int, int, int);
 void  pcidecomposetag(unsigned, int *, int *, int *);
 int   pcifinddev(unsigned, unsigned, unsigned *);
@@ -159,8 +167,23 @@
 NIF_DECL(stg);
 
 /* DSK support */
+#define MAX_UNITS 4
+
+struct disk {
+	char xname[8];
+	void *dvops;
+	unsigned unittag;
+	uint16_t ident[128];
+	uint64_t nsect;
+	uint64_t first;
+	void *dlabel;
+	int part;
+	void *fsops;
+	int (*lba_read)(struct disk *, int64_t, int, void *);
+};
+
 int dskdv_init(void *);
-
+int dlabel_valid(int);
 int dsk_open(struct open_file *, ...);
 int dsk_close(struct open_file *);
 int dsk_strategy(void *, int, daddr_t, size_t, void *, size_t *);
@@ -222,19 +245,6 @@
 	char *iobuf;
 };
 
-struct disk {
-	char xname[8];
-	void *dvops;
-	unsigned unittag;
-	uint16_t ident[128];
-	uint64_t nsect;
-	uint64_t first;
-	void *dlabel;
-	int part;
-	void *fsops;
-	int (*lba_read)(struct disk *, int64_t, int, void *);
-};
-
 int spinwait_unbusy(struct dkdev_ata *, int, int, const char **);
 int perform_atareset(struct dkdev_ata *, int);
 void wakeup_drive(struct dkdev_ata *, int);
--- a/sys/arch/sandpoint/stand/altboot/main.c	Tue Apr 17 19:25:17 2012 +0000
+++ b/sys/arch/sandpoint/stand/altboot/main.c	Sun Apr 29 23:04:36 2012 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: main.c,v 1.15.4.1 2012/02/18 07:33:05 mrg Exp $ */
+/* $NetBSD: main.c,v 1.15.4.2 2012/04/29 23:04:42 mrg Exp $ */
 
 /*-
  * Copyright (c) 2007 The NetBSD Foundation, Inc.
@@ -119,15 +119,14 @@
 void
 main(int argc, char *argv[], char *bootargs_start, char *bootargs_end)
 {
+	unsigned long marks[MARK_MAX];
 	struct brdprop *brdprop;
-	unsigned long marks[MARK_MAX];
 	char *new_argv[MAX_ARGS];
+	char *bname;
 	ssize_t len;
-	int n, i, fd, howto;
-	char *bname;
+	int err, fd, howto, i, n;
 
-	printf("\n");
-	printf(">> %s altboot, revision %s\n", bootprog_name, bootprog_rev);
+	printf("\n>> %s altboot, revision %s\n", bootprog_name, bootprog_rev);
 
 	brdprop = brd_lookup(brdtype);
 	printf(">> %s, cpu %u MHz, bus %u MHz, %dMB SDRAM\n", brdprop->verbose,
@@ -218,10 +217,9 @@
 	}
 
 	/* intialize a disk driver */
-	for (n = 0; n < nata; n++)
-		if (dskdv_init(&lata[n]) != 0)
-			break;
-	if (n >= nata)
+	for (i = 0, n = 0; i < nata; i++)
+		n += dskdv_init(&lata[i]);
+	if (n == 0)
 		printf("IDE/SATA device driver was not found\n");
 
 	/* initialize a network interface */
@@ -234,7 +232,7 @@
 	/* wait 2s for user to enter interactive mode */
 	for (n = 200; n >= 0; n--) {
 		if (n % 100 == 0)
-			printf("Hit any key to enter interactive mode: %d\r",
+			printf("\rHit any key to enter interactive mode: %d",
 			    n / 100);
 		if (tstchar()) {
 #ifdef DEBUG
@@ -273,84 +271,113 @@
 		if (i >= sizeof(bootargs) / sizeof(bootargs[0]))
 			break;	/* break on first unknown string */
 	}
-	if (n >= argc)
-		bname = BNAME_DEFAULT;
-	else {
-		bname = argv[n];
-		if (check_bootname(bname) == 0) {
-			printf("%s not a valid bootname\n", bname);
-			goto loadfail;
+
+	/*
+	 * If no device name is given, we construct a list of drives
+	 * which have valid disklabels.
+	 */
+	if (n >= argc) {
+		n = 0;
+		argc = 0;
+		argv = alloc(MAX_UNITS * (sizeof(char *) + sizeof("wdN:")));
+		bname = (char *)(argv + MAX_UNITS);
+		for (i = 0; i < MAX_UNITS; i++) {
+			if (!dlabel_valid(i))
+				continue;
+			sprintf(bname, "wd%d:", i);
+			argv[argc++] = bname;
+			bname += sizeof("wdN:");
+		}
+		/* use default drive if no valid disklabel is found */
+		if (argc == 0) {
+			argc = 1;
+			argv[0] = BNAME_DEFAULT;
 		}
 	}
 
-	if ((fd = open(bname, 0)) < 0) {
-		if (errno == ENOENT)
-			printf("\"%s\" not found\n", bi_path.bootpath);
-		goto loadfail;
-	}
-	printf("loading \"%s\" ", bi_path.bootpath);
-	marks[MARK_START] = 0;
+	/* try to boot off kernel from the drive list */
+	while (n < argc) {
+		bname = argv[n++];
+
+		if (check_bootname(bname) == 0) {
+			printf("%s not a valid bootname\n", bname);