Recommit trunk
authormaxv <maxv@NetBSD.org>
Sat, 11 Nov 2017 11:00:46 +0000
branchtrunk
changeset 273215 aa0e903e2c12
parent 273214 9b55ab006ecd
child 273216 5cf4952a76bf
Recommit http://mail-index.netbsd.org/source-changes/2017/11/08/msg089525.html but use __INITIAL_MXCSR_MASK__ on Xen until someone figures out what's wrong with the Xen fpu.
sys/arch/x86/x86/cpu.c
sys/arch/x86/x86/fpu.c
sys/arch/x86/x86/identcpu.c
sys/arch/xen/x86/cpu.c
--- a/sys/arch/x86/x86/cpu.c	Sat Nov 11 09:10:19 2017 +0000
+++ b/sys/arch/x86/x86/cpu.c	Sat Nov 11 11:00:46 2017 +0000
@@ -1,4 +1,4 @@
-/*	$NetBSD: cpu.c,v 1.140 2017/11/11 09:10:19 bouyer Exp $	*/
+/*	$NetBSD: cpu.c,v 1.141 2017/11/11 11:00:46 maxv Exp $	*/
 
 /*
  * Copyright (c) 2000-2012 NetBSD Foundation, Inc.
@@ -62,7 +62,7 @@
  */
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.140 2017/11/11 09:10:19 bouyer Exp $");
+__KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.141 2017/11/11 11:00:46 maxv Exp $");
 
 #include "opt_ddb.h"
 #include "opt_mpbios.h"		/* for MPDEBUG */
@@ -541,6 +541,7 @@
 void
 cpu_init(struct cpu_info *ci)
 {
+	extern int x86_fpu_save;
 	uint32_t cr4 = 0;
 
 	lcr0(rcr0() | CR0_WP);
@@ -584,6 +585,10 @@
 		lcr4(cr4);
 	}
 
+	if (x86_fpu_save >= FPU_SAVE_FXSAVE) {
+		fpuinit_mxcsr_mask();
+	}
+
 	/* If xsave is enabled, enable all fpu features */
 	if (cr4 & CR4_OSXSAVE)
 		wrxcr(0, x86_xsave_features & XCR0_FPU);
--- a/sys/arch/x86/x86/fpu.c	Sat Nov 11 09:10:19 2017 +0000
+++ b/sys/arch/x86/x86/fpu.c	Sat Nov 11 11:00:46 2017 +0000
@@ -1,4 +1,4 @@
-/*	$NetBSD: fpu.c,v 1.26 2017/11/11 09:10:19 bouyer Exp $	*/
+/*	$NetBSD: fpu.c,v 1.27 2017/11/11 11:00:46 maxv Exp $	*/
 
 /*
  * Copyright (c) 2008 The NetBSD Foundation, Inc.  All
@@ -96,7 +96,7 @@
  */
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: fpu.c,v 1.26 2017/11/11 09:10:19 bouyer Exp $");
+__KERNEL_RCSID(0, "$NetBSD: fpu.c,v 1.27 2017/11/11 11:00:46 maxv Exp $");
 
 #include "opt_multiprocessor.h"
 
@@ -235,21 +235,20 @@
 {
 #ifndef XEN
 	union savefpu fpusave __aligned(16);
-	u_long cr0, psl;
+	u_long psl;
 
 	memset(&fpusave, 0, sizeof(fpusave));
 
 	/* Disable interrupts, and enable FPU */
 	psl = x86_read_psl();
 	x86_disable_intr();
-	cr0 = rcr0();
-	lcr0(cr0 & ~(CR0_EM|CR0_TS));
+	clts();
 
 	/* Fill in the FPU area */
 	fxsave(&fpusave);
 
 	/* Restore previous state */
-	lcr0(cr0);
+	stts();
 	x86_write_psl(psl);
 
 	if (fpusave.sv_xmm.fx_mxcsr_mask == 0) {
@@ -258,9 +257,6 @@
 		x86_fpu_mxcsr_mask = fpusave.sv_xmm.fx_mxcsr_mask;
 	}
 #else
-	/*
-	 * XXX: Does the detection above work on Xen?
-	 */
 	x86_fpu_mxcsr_mask = __INITIAL_MXCSR_MASK__;
 #endif
 }
--- a/sys/arch/x86/x86/identcpu.c	Sat Nov 11 09:10:19 2017 +0000
+++ b/sys/arch/x86/x86/identcpu.c	Sat Nov 11 11:00:46 2017 +0000
@@ -1,4 +1,4 @@
-/*	$NetBSD: identcpu.c,v 1.66 2017/11/11 09:10:19 bouyer Exp $	*/
+/*	$NetBSD: identcpu.c,v 1.67 2017/11/11 11:00:46 maxv Exp $	*/
 
 /*-
  * Copyright (c) 1999, 2000, 2001, 2006, 2007, 2008 The NetBSD Foundation, Inc.
@@ -30,7 +30,7 @@
  */
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: identcpu.c,v 1.66 2017/11/11 09:10:19 bouyer Exp $");
+__KERNEL_RCSID(0, "$NetBSD: identcpu.c,v 1.67 2017/11/11 11:00:46 maxv Exp $");
 
 #include "opt_xen.h"
 
@@ -753,8 +753,6 @@
 
 	x86_fpu_save = FPU_SAVE_FXSAVE;
 
-	fpuinit_mxcsr_mask();
-
 	/* See if xsave (for AVX) is supported */
 	if ((ci->ci_feat_val[1] & CPUID2_XSAVE) == 0)
 		return;
--- a/sys/arch/xen/x86/cpu.c	Sat Nov 11 09:10:19 2017 +0000
+++ b/sys/arch/xen/x86/cpu.c	Sat Nov 11 11:00:46 2017 +0000
@@ -1,4 +1,4 @@
-/*	$NetBSD: cpu.c,v 1.115 2017/11/11 09:10:19 bouyer Exp $	*/
+/*	$NetBSD: cpu.c,v 1.116 2017/11/11 11:00:47 maxv Exp $	*/
 
 /*-
  * Copyright (c) 2000 The NetBSD Foundation, Inc.
@@ -65,7 +65,7 @@
  */
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.115 2017/11/11 09:10:19 bouyer Exp $");
+__KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.116 2017/11/11 11:00:47 maxv Exp $");
 
 #include "opt_ddb.h"
 #include "opt_multiprocessor.h"
@@ -540,6 +540,10 @@
 			lcr4(rcr4() | CR4_OSXMMEXCPT);
 	}
 
+	if (x86_fpu_save >= FPU_SAVE_FXSAVE) {
+		fpuinit_mxcsr_mask();
+	}
+
 	atomic_or_32(&ci->ci_flags, CPUF_RUNNING);
 }