Add support for the Intel G45 AGP. From Arnaud Lacombe trunk
authorchristos <christos@NetBSD.org>
Sat, 29 Nov 2008 23:48:12 +0000
branchtrunk
changeset 175569 d733d57cfa1e
parent 175568 d91d3a01ea7b
child 175570 4493b5441455
Add support for the Intel G45 AGP. From Arnaud Lacombe
sys/arch/x86/pci/pchb.c
sys/dev/pci/agp.c
sys/dev/pci/agp_i810.c
sys/dev/pci/agpreg.h
sys/dev/pci/pcidevs
--- a/sys/arch/x86/pci/pchb.c	Sat Nov 29 23:16:26 2008 +0000
+++ b/sys/arch/x86/pci/pchb.c	Sat Nov 29 23:48:12 2008 +0000
@@ -1,4 +1,4 @@
-/*	$NetBSD: pchb.c,v 1.15 2008/11/08 17:26:28 christos Exp $ */
+/*	$NetBSD: pchb.c,v 1.16 2008/11/29 23:48:12 christos Exp $ */
 
 /*-
  * Copyright (c) 1996, 1998, 2000 The NetBSD Foundation, Inc.
@@ -30,7 +30,7 @@
  */
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: pchb.c,v 1.15 2008/11/08 17:26:28 christos Exp $");
+__KERNEL_RCSID(0, "$NetBSD: pchb.c,v 1.16 2008/11/29 23:48:12 christos Exp $");
 
 #include <sys/types.h>
 #include <sys/param.h>
@@ -383,6 +383,7 @@
 		case PCI_PRODUCT_INTEL_82G33_HB:
 		case PCI_PRODUCT_INTEL_82Q33_HB:
 		case PCI_PRODUCT_INTEL_82G35_HB:
+		case PCI_PRODUCT_INTEL_82GM45_HB:
 			/*
 			 * The host bridge is either in GFX mode (internal
 			 * graphics) or in AGP mode. In GFX mode, we pretend
--- a/sys/dev/pci/agp.c	Sat Nov 29 23:16:26 2008 +0000
+++ b/sys/dev/pci/agp.c	Sat Nov 29 23:48:12 2008 +0000
@@ -1,4 +1,4 @@
-/*	$NetBSD: agp.c,v 1.63 2008/11/08 17:26:28 christos Exp $	*/
+/*	$NetBSD: agp.c,v 1.64 2008/11/29 23:48:12 christos Exp $	*/
 
 /*-
  * Copyright (c) 2000 Doug Rabson
@@ -65,7 +65,7 @@
 
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: agp.c,v 1.63 2008/11/08 17:26:28 christos Exp $");
+__KERNEL_RCSID(0, "$NetBSD: agp.c,v 1.64 2008/11/29 23:48:12 christos Exp $");
 
 #include <sys/param.h>
 #include <sys/systm.h>
@@ -184,6 +184,8 @@
 	  NULL,			agp_i810_attach },
 	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82946GZ_HB,
 	  NULL,			agp_i810_attach },
+	{ PCI_VENDOR_INTEL,	PCI_PRODUCT_INTEL_82GM45_HB,
+	  NULL, 		agp_i810_attach },
 #endif
 
 #if NAGP_INTEL > 0
--- a/sys/dev/pci/agp_i810.c	Sat Nov 29 23:16:26 2008 +0000
+++ b/sys/dev/pci/agp_i810.c	Sat Nov 29 23:48:12 2008 +0000
@@ -1,4 +1,4 @@
-/*	$NetBSD: agp_i810.c,v 1.57 2008/11/08 17:26:28 christos Exp $	*/
+/*	$NetBSD: agp_i810.c,v 1.58 2008/11/29 23:48:12 christos Exp $	*/
 
 /*-
  * Copyright (c) 2000 Doug Rabson
@@ -30,7 +30,7 @@
  */
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: agp_i810.c,v 1.57 2008/11/08 17:26:28 christos Exp $");
+__KERNEL_RCSID(0, "$NetBSD: agp_i810.c,v 1.58 2008/11/29 23:48:12 christos Exp $");
 
 #include <sys/param.h>
 #include <sys/systm.h>
@@ -57,22 +57,6 @@
 #define READ1(off)	bus_space_read_1(isc->bst, isc->bsh, off)
 #define READ4(off)	bus_space_read_4(isc->bst, isc->bsh, off)
 #define WRITE4(off,v)	bus_space_write_4(isc->bst, isc->bsh, off, v)
-#define WRITEGTT(off, v)						\
-	do {								\
-		if (isc->chiptype == CHIP_I915 || isc->chiptype == CHIP_G33) { \
-			bus_space_write_4(isc->gtt_bst, isc->gtt_bsh,	\
-			    (u_int32_t)((off) >> AGP_PAGE_SHIFT) * 4,	\
-			    (v));					\
-		} else if (isc->chiptype == CHIP_I965) {		\
-			WRITE4(AGP_I965_GTT +				\
-			    (u_int32_t)((off) >> AGP_PAGE_SHIFT) * 4,	\
-			    (v));					\
-		} else {						\
-			WRITE4(AGP_I810_GTT +				\
-			    (u_int32_t)((off) >> AGP_PAGE_SHIFT) * 4,	\
-			    (v));					\
-		}							\
-	} while (0)
 
 #define CHIP_I810 0	/* i810/i815 */
 #define CHIP_I830 1	/* 830M/845G */
@@ -80,6 +64,7 @@
 #define CHIP_I915 3	/* 915G/915GM/945G/945GM/945GME */
 #define CHIP_I965 4	/* 965Q/965PM */
 #define CHIP_G33  5	/* G33/Q33/Q35 */
+#define CHIP_G4X  6	/* G45/Q45 */
 
 struct agp_i810_softc {
 	u_int32_t initial_aperture;	/* aperture size at startup */
@@ -117,6 +102,8 @@
 static int agp_i810_init(struct agp_softc *);
 
 static int agp_i810_init(struct agp_softc *);
+static void agp_i810_write_gtt_entry(struct agp_i810_softc *, off_t,
+				     u_int32_t);
 
 static struct agp_methods agp_i810_methods = {
 	agp_i810_get_aperture,
@@ -131,6 +118,33 @@
 	agp_i810_unbind_memory,
 };
 
+static void
+agp_i810_write_gtt_entry(struct agp_i810_softc *isc, off_t off, u_int32_t v)
+{
+	u_int32_t base_off;
+
+	base_off = 0;
+
+	switch (isc->chiptype) {
+	case CHIP_I810:
+	case CHIP_I830:
+	case CHIP_I855:
+		base_off = AGP_I810_GTT;
+		break;
+	case CHIP_I965:
+		base_off = AGP_I965_GTT;
+		break;
+	case CHIP_G4X:
+		base_off = AGP_G4X_GTT;
+		break;
+	case CHIP_I915:
+	case CHIP_G33:
+		break;
+	}
+		
+	WRITE4(base_off + (u_int32_t)(off >> AGP_PAGE_SHIFT) * 4, v);
+}
+
 /* XXXthorpej -- duplicated code (see arch/x86/pci/pchb.c) */
 static int
 agp_i810_vgamatch(struct pci_attach_args *pa)
@@ -170,6 +184,8 @@
 	case PCI_PRODUCT_INTEL_82G35_IGD:
 	case PCI_PRODUCT_INTEL_82G35_IGD_1:
 	case PCI_PRODUCT_INTEL_82946GZ_IGD:
+	case PCI_PRODUCT_INTEL_82GM45_IGD:
+	case PCI_PRODUCT_INTEL_82GM45_IGD_1:
 		return (1);
 	}
 
@@ -272,6 +288,9 @@
 	case PCI_PRODUCT_INTEL_82Q33_IGD:
 	case PCI_PRODUCT_INTEL_82Q33_IGD_1:
 		isc->chiptype = CHIP_G33;
+	case PCI_PRODUCT_INTEL_82GM45_IGD:
+	case PCI_PRODUCT_INTEL_82GM45_IGD_1:
+		isc->chiptype = CHIP_G4X;
 		break;
 	}
 
@@ -280,12 +299,17 @@
 	case CHIP_G33:
 		apbase = AGP_I915_GMADR;
 		break;
+	case CHIP_I965:
+	case CHIP_G4X:
+		apbase = AGP_I965_GMADR;
+		break;
 	default:
 		apbase = AGP_I810_GMADR;
 		break;
 	}
-	if (isc->chiptype == CHIP_I965) {
-		error = agp_i965_map_aperture(&isc->vga_pa, sc, AGP_I965_GMADR);
+
+	if (isc->chiptype == CHIP_I965 || isc->chiptype == CHIP_G4X) {
+		error = agp_i965_map_aperture(&isc->vga_pa, sc, apbase);
 	} else {
 		error = agp_map_aperture(&isc->vga_pa, sc, apbase);
 	}
@@ -313,7 +337,7 @@
 			agp_generic_detach(sc);
 			return error;
 		}
-	} else if (isc->chiptype == CHIP_I965) {
+	} else if (isc->chiptype == CHIP_I965 || isc->chiptype == CHIP_G4X) {
 		error = pci_mapreg_map(&isc->vga_pa, AGP_I965_MMADR,
 		    PCI_MAPREG_TYPE_MEM, 0, &isc->bst, &isc->bsh,
 		    &mmadr, &mmadrsize);
@@ -442,90 +466,157 @@
 
 		gatt->ag_physical = pgtblctl & ~1;
 	} else if (isc->chiptype == CHIP_I855 || isc->chiptype == CHIP_I915 ||
-		   isc->chiptype == CHIP_I965 || isc->chiptype == CHIP_G33) {
+		   isc->chiptype == CHIP_I965 || isc->chiptype == CHIP_G33 ||
+		   isc->chiptype == CHIP_G4X) {
 		pcireg_t reg;
-		u_int32_t pgtblctl, stolen;
+		u_int32_t pgtblctl, gtt_size, stolen;
 		u_int16_t gcc1;
 
 		reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_I855_GCC1);
 		gcc1 = (u_int16_t)(reg >> 16);
 
+		pgtblctl = READ4(AGP_I810_PGTBL_CTL);
+
 		/* Stolen memory is set up at the beginning of the aperture by
                  * the BIOS, consisting of the GATT followed by 4kb for the
 		 * BIOS display.
                  */
                 switch (isc->chiptype) {
 		case CHIP_I855:
-			stolen = 128 + 4;
+			gtt_size = 128;
 			break;
                 case CHIP_I915:
-			stolen = 256 + 4;
+			gtt_size = 256;
 			break;
 		case CHIP_I965:
-			stolen = 512 + 4;
+			switch (pgtblctl) {
+			case AGP_I810_PGTBL_SIZE_128KB:
+			case AGP_I810_PGTBL_SIZE_512KB:
+				gtt_size = 512;
+				break;
+			case AGP_I965_PGTBL_SIZE_1MB:
+				gtt_size = 1024;
+				break;
+			case AGP_I965_PGTBL_SIZE_2MB:
+				gtt_size = 1024;
+				break;
+			case AGP_I965_PGTBL_SIZE_1_5MB:
+				gtt_size = 1024;
+				break;
+			default:
+				aprint_error("Bad PGTBL size\n");
+				agp_generic_detach(sc);
+				return EINVAL;
+			}
 			break;
 		case CHIP_G33:
 			switch (gcc1 & AGP_G33_PGTBL_SIZE_MASK) {
 			case AGP_G33_PGTBL_SIZE_1M:
-				stolen = 1024 + 4;
+				gtt_size = 1024;
 				break;
 			case AGP_G33_PGTBL_SIZE_2M:
-				stolen = 2048 + 4;
+				gtt_size = 2048;
 				break;
 			default:
-				aprint_error(": bad gtt size\n");
+				aprint_error(": Bad PGTBL size\n");
 				agp_generic_detach(sc);
 				return EINVAL;
 			}
 			break;
+		case CHIP_G4X:
+			gtt_size = 0;
+			break;
 		default:
 			aprint_error(": bad chiptype\n");
 			agp_generic_detach(sc);
 			return EINVAL;
-               }
+		}
 
 		switch (gcc1 & AGP_I855_GCC1_GMS) {
 		case AGP_I855_GCC1_GMS_STOLEN_1M:
-			isc->stolen = (1024 - stolen) * 1024 / 4096;
+			stolen = 1024;
 			break;
 		case AGP_I855_GCC1_GMS_STOLEN_4M:
-			isc->stolen = (4096 - stolen) * 1024 / 4096;
+			stolen = 4 * 1024;
 			break;
 		case AGP_I855_GCC1_GMS_STOLEN_8M:
-			isc->stolen = (8192 - stolen) * 1024 / 4096;
+			stolen = 8 * 1024;
 			break;
 		case AGP_I855_GCC1_GMS_STOLEN_16M:
-			isc->stolen = (16384 - stolen) * 1024 / 4096;
+			stolen = 16 * 1024;
 			break;
 		case AGP_I855_GCC1_GMS_STOLEN_32M:
-			isc->stolen = (32768 - stolen) * 1024 / 4096;
+			stolen = 32 * 1024;
 			break;
 		case AGP_I915_GCC1_GMS_STOLEN_48M:
-			isc->stolen = (49152 - stolen) * 1024 / 4096;
+			stolen = 48 * 1024;
 			break;
 		case AGP_I915_GCC1_GMS_STOLEN_64M:
-			isc->stolen = (65536 - stolen) * 1024 / 4096;
+			stolen = 64 * 1024;
 			break;
 		case AGP_G33_GCC1_GMS_STOLEN_128M:
-			isc->stolen = ((128 * 1024) - stolen) * 1024 / 4096;
+			stolen = 128 * 1024;
 			break;
 		case AGP_G33_GCC1_GMS_STOLEN_256M:
-			isc->stolen = ((256 * 1024) - stolen) * 1024 / 4096;
+			stolen = 256 * 1024;
+			break;
+		case AGP_G4X_GCC1_GMS_STOLEN_96M:
+			stolen = 96 * 1024;
+			break;
+		case AGP_G4X_GCC1_GMS_STOLEN_160M:
+			stolen = 160 * 1024;
+			break;
+		case AGP_G4X_GCC1_GMS_STOLEN_224M:
+			stolen = 224 * 1024;
+			break;
+		case AGP_G4X_GCC1_GMS_STOLEN_352M:
+			stolen = 352 * 1024;
 			break;
 		default:
-			isc->stolen = 0;
 			aprint_error(
 			    ": unknown memory configuration, disabling\n");
 			agp_generic_detach(sc);
 			return EINVAL;
 		}
+
+		switch (gcc1 & AGP_I855_GCC1_GMS) {
+		case AGP_I915_GCC1_GMS_STOLEN_48M:
+		case AGP_I915_GCC1_GMS_STOLEN_64M:
+			if (isc->chiptype != CHIP_I915 &&
+			    isc->chiptype != CHIP_I965 &&
+			    isc->chiptype != CHIP_G33 &&
+			    isc->chiptype != CHIP_G4X)
+				stolen = 0;
+			break;
+		case AGP_G33_GCC1_GMS_STOLEN_128M:
+		case AGP_G33_GCC1_GMS_STOLEN_256M:
+			if (isc->chiptype != CHIP_I965 &&
+			    isc->chiptype != CHIP_G33 &&
+			    isc->chiptype != CHIP_G4X)
+				stolen = 0;
+			break;
+		case AGP_G4X_GCC1_GMS_STOLEN_96M:
+		case AGP_G4X_GCC1_GMS_STOLEN_160M:
+		case AGP_G4X_GCC1_GMS_STOLEN_224M:
+		case AGP_G4X_GCC1_GMS_STOLEN_352M:
+			if (isc->chiptype != CHIP_I965 &&
+			    isc->chiptype != CHIP_G4X)
+				stolen = 0;
+			break;
+		}
+
+		/* BIOS space */
+		if (isc->chiptype != CHIP_G4X)
+			gtt_size += 4;
+
+		isc->stolen = (stolen - gtt_size) * 1024 / 4096;
+
 		if (isc->stolen > 0) {
 			aprint_normal(": detected %dk stolen memory\n%s",
 			    isc->stolen * 4, device_xname(sc->as_dev));
 		}
 
 		/* GATT address is already in there, make sure it's enabled */
-		pgtblctl = READ4(AGP_I810_PGTBL_CTL);
 		pgtblctl |= 1;
 		WRITE4(AGP_I810_PGTBL_CTL, pgtblctl);
 
@@ -579,41 +670,59 @@
 {
 	struct agp_i810_softc *isc = sc->as_chipc;
 	pcireg_t reg;
+	u_int32_t size;
 	u_int16_t miscc, gcc1, msac;
 
+	size = 0;
+
 	switch (isc->chiptype) {
 	case CHIP_I810:
 		reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_I810_SMRAM);
 		miscc = (u_int16_t)(reg >> 16);
 		if ((miscc & AGP_I810_MISCC_WINSIZE) ==
 		    AGP_I810_MISCC_WINSIZE_32)
-			return 32 * 1024 * 1024;
+			size = 32 * 1024 * 1024;
 		else
-			return 64 * 1024 * 1024;
+			size = 64 * 1024 * 1024;
+		break;
 	case CHIP_I830:
 		reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_I830_GCC0);
 		gcc1 = (u_int16_t)(reg >> 16);
 		if ((gcc1 & AGP_I830_GCC1_GMASIZE) == AGP_I830_GCC1_GMASIZE_64)
-			return 64 * 1024 * 1024;
+			size = 64 * 1024 * 1024;
 		else
-			return 128 * 1024 * 1024;
+			size = 128 * 1024 * 1024;
+		break;
 	case CHIP_I855:
-		return 128 * 1024 * 1024;
+		size = 128 * 1024 * 1024;
+		break;
 	case CHIP_I915:
 	case CHIP_G33:
 		reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_I915_MSAC);
 		msac = (u_int16_t)(reg >> 16);
 		if (msac & AGP_I915_MSAC_APER_128M)
-			return 128 * 1024 * 1024;
+			size = 128 * 1024 * 1024;
 		else
-			return 256 * 1024 * 1024;
+			size = 256 * 1024 * 1024;
+		break;
 	case CHIP_I965:
-		return 512 * 1024 * 1024;
+		size = 512 * 1024 * 1024;
+		break;
+	case CHIP_G4X:
+		reg = pci_conf_read(sc->as_pc, sc->as_tag, AGP_G4X_MSAC);
+		msac = (u_int16_t)(reg >> 16);
+		switch (msac & AGP_G4X_MSAC_MASK) {
+		case AGP_G4X_MSAC_APER_256M:
+			size = 256 * 1024 * 1024;		
+		case AGP_G4X_MSAC_APER_512M:
+			size = 512 * 1024 * 1024;
+		}
+		break;
 	default:
 		aprint_error(": Unknown chipset\n");
 	}
 
-	return 0;
+	return size;
 }
 
 static int
@@ -710,7 +819,7 @@
 		}
 	}
 
-	WRITEGTT(offset, physical | 1);
+	agp_i810_write_gtt_entry(isc, offset, physical | 1);
 	return 0;
 }
 
@@ -732,7 +841,7 @@
 		}
 	}
 
-	WRITEGTT(offset, 0);
+	agp_i810_write_gtt_entry(isc, offset, 0);
 	return 0;
 }
 
@@ -864,7 +973,7 @@
 	}
 
 	if (mem->am_type == 2) {
-		WRITEGTT(offset, mem->am_physical | 1);
+		agp_i810_write_gtt_entry(isc, offset, mem->am_physical | 1);
 		mem->am_offset = offset;
 		mem->am_is_bound = 1;
 		return 0;
@@ -877,7 +986,7 @@
 		return EINVAL;
 
 	for (i = 0; i < mem->am_size; i += AGP_PAGE_SIZE)
-		WRITEGTT(offset, i | 3);
+		agp_i810_write_gtt_entry(isc, offset, i | 3);
 	mem->am_is_bound = 1;
 	return 0;
 }
@@ -889,7 +998,7 @@
 	u_int32_t i;
 
 	if (mem->am_type == 2) {
-		WRITEGTT(mem->am_offset, 0);
+		agp_i810_write_gtt_entry(isc, mem->am_offset, 0);
 		mem->am_offset = 0;
 		mem->am_is_bound = 0;
 		return 0;
@@ -902,7 +1011,7 @@
 		return EINVAL;
 
 	for (i = 0; i < mem->am_size; i += AGP_PAGE_SIZE)
-		WRITEGTT(i, 0);
+		agp_i810_write_gtt_entry(isc, i, 0);
 	mem->am_is_bound = 0;
 	return 0;
 }
--- a/sys/dev/pci/agpreg.h	Sat Nov 29 23:16:26 2008 +0000
+++ b/sys/dev/pci/agpreg.h	Sat Nov 29 23:48:12 2008 +0000
@@ -1,4 +1,4 @@
-/*	$NetBSD: agpreg.h,v 1.19 2008/03/11 13:36:14 joerg Exp $	*/
+/*	$NetBSD: agpreg.h,v 1.20 2008/11/29 23:48:12 christos Exp $	*/
 
 /*-
  * Copyright (c) 2000 Doug Rabson
@@ -176,10 +176,19 @@
  * Memory mapped register offsets for i810 chipset.
  */
 #define AGP_I810_PGTBL_CTL	0x2020
-#define AGP_I810_DRT		0x3000
-#define AGP_I810_DRT_UNPOPULATED 0x00
-#define AGP_I810_DRT_POPULATED	0x01
-#define AGP_I810_GTT		0x10000
+
+/**
+ * This field determines the actual size of the global GTT on the 965
+ * and G33
+ */
+#define AGP_I810_PGTBL_SIZE_MASK	0x0000000e
+#define AGP_I810_PGTBL_SIZE_512KB	(0 << 1)
+#define AGP_I810_PGTBL_SIZE_256KB	(1 << 1)
+#define AGP_I810_PGTBL_SIZE_128KB	(2 << 1)
+#define AGP_I810_DRT			0x3000
+#define AGP_I810_DRT_UNPOPULATED	0x00
+#define AGP_I810_DRT_POPULATED		0x01
+#define AGP_I810_GTT			0x10000
 
 /*
  * Config registers for i830MG device 0
@@ -220,16 +229,16 @@
 #define AGP_I915_GMADR			0x18
 #define AGP_I915_GTTADR			0x1c
 #define AGP_I915_GCC1			0x52
-#define 	AGP_I915_GCC1_GMS		0x70
-#define 	AGP_I915_GCC1_GMS_STOLEN_0M	0x00
-#define 	AGP_I915_GCC1_GMS_STOLEN_1M	0x10
-#define 	AGP_I915_GCC1_GMS_STOLEN_8M	0x30
-#define 	AGP_I915_GCC1_GMS_STOLEN_16M	0x40
-#define 	AGP_I915_GCC1_GMS_STOLEN_32M	0x50
-#define 	AGP_I915_GCC1_GMS_STOLEN_48M	0x60
-#define 	AGP_I915_GCC1_GMS_STOLEN_64M	0x70
+#define AGP_I915_GCC1_GMS		0x70
+#define AGP_I915_GCC1_GMS_STOLEN_0M	0x00
+#define AGP_I915_GCC1_GMS_STOLEN_1M	0x10
+#define	AGP_I915_GCC1_GMS_STOLEN_8M	0x30
+#define AGP_I915_GCC1_GMS_STOLEN_16M	0x40
+#define AGP_I915_GCC1_GMS_STOLEN_32M	0x50
+#define AGP_I915_GCC1_GMS_STOLEN_48M	0x60
+#define AGP_I915_GCC1_GMS_STOLEN_64M	0x70
 #define AGP_I915_MSAC			0x60 /* upper word */
-#define 	AGP_I915_MSAC_APER_128M		0x02
+#define AGP_I915_MSAC_APER_128M		0x02
 
 /*
  * Config registers for 965G/965Q
@@ -237,7 +246,12 @@
 #define AGP_I965_MMADR			0x10
 #define AGP_I965_GMADR			0x18
 
-#define AGP_I965_GTT			0x80000
+#define AGP_I965_GTT			(512*1024)
+
+#define AGP_I965_PGTBL_SIZE_1MB		(3 << 1)
+#define AGP_I965_PGTBL_SIZE_2MB		(4 << 1)
+#define AGP_I965_PGTBL_SIZE_1_5MB	(5 << 1)
+
 
 /*
  * Config registers for G33
@@ -250,6 +264,21 @@
 #define AGP_G33_GCC1_GMS_STOLEN_256M	0x90
 
 /*
+ * Config registers for G4X
+ */
+#define AGP_G4X_MSAC			0x64 /* upper word */
+#define AGP_G4X_MSAC_MASK		0xff
+#define AGP_G4X_MSAC_APER_256M		0x02
+#define AGP_G4X_MSAC_APER_512M		0x04
+
+#define AGP_G4X_GTT			(2*1024*1024)
+
+#define AGP_G4X_GCC1_GMS_STOLEN_96M	0xa0
+#define AGP_G4X_GCC1_GMS_STOLEN_160M	0xb0
+#define AGP_G4X_GCC1_GMS_STOLEN_224M	0xc0
+#define AGP_G4X_GCC1_GMS_STOLEN_352M	0xd0
+
+/*
  * AMD64 GART registers
  */
 #define	AGP_AMD64_APCTRL		0x90
--- a/sys/dev/pci/pcidevs	Sat Nov 29 23:16:26 2008 +0000
+++ b/sys/dev/pci/pcidevs	Sat Nov 29 23:48:12 2008 +0000
@@ -1,4 +1,4 @@
-$NetBSD: pcidevs,v 1.966 2008/11/18 16:12:03 matt Exp $
+$NetBSD: pcidevs,v 1.967 2008/11/29 23:48:12 christos Exp $
 
 /*
  * Copyright (c) 1995, 1996 Christopher G. Demetriou
@@ -2521,12 +2521,16 @@
 product INTEL 82801IH_LPC	0x2912	82801IH LPC Interface Bridge
 product INTEL 82801IO_LPC	0x2914	82801IO LPC Interface Bridge
 product INTEL 82801IR_LPC	0x2916	82801IR LPC Interface Bridge
+product INTEL 82801IEM_LPC	0x2917	82801IEM LPC Interface Bridge
 product INTEL 82801IB_LPC	0x2918	82801IB LPC Interface Bridge
+product INTEL 82801IM_LPC	0x2919	82801IM LPC Interface Bridge
 product INTEL 82801I_SATA_1	0x2920	82801I SATA Controller w/ 4 ports
 product INTEL 82801I_SATA_2	0x2921	82801I SATA Controller w/ 2 ports
 product INTEL 82801I_SATA_AHCI6	0x2922	82801I AHCI SATA Controller w/ 6 ports
 product INTEL 82801I_SATA_AHCI4	0x2923	82801I AHCI SATA Controller w/ 4 ports
 product INTEL 82801I_SATA_3	0x2926	82801I SATA Controller w/ 2 ports
+product INTEL 82801I_SATA_4	0x2928	82801I Mobile AHCI SATA Controller with 2 ports
+product INTEL 82801I_SATA_5	0x2929	82801I Mobile AHCI SATA Controller with 4 ports
 product INTEL 82801I_SMB	0x2930	82801I SMBus Controller
 product INTEL 82801I_THERMAL	0x2932	82801I Thermal Controller
 product INTEL 82801I_USB_1	0x2934	82801I USB UHCI Controller
@@ -2578,6 +2582,15 @@
 product INTEL 82965PM_MEI	0x2a04	82965PM MEI Controller
 product INTEL 82965PM_IDE	0x2a06	82965PM IDE Interface
 product INTEL 82965PM_KT	0x2a07	82965PM Serial Interface
+product INTEL 82GM45_HB		0x2a40	82GM45 Host Bridge
+product INTEL 82GM45_IGD	0x2a42	82GM45 Integrated Graphics Device
+product INTEL 82GM45_IGD_1	0x2a43	82GM45 Integrated Graphics Device
+product INTEL 82IGD_E_HB	0x2e00	82IGD_E Host Bridge
+product INTEL 82IGD_E_IGD	0x2e02	82IGD_E Integrated Graphics
+product INTEL 82Q45_HB		0x2e10	82Q45 Host Bridge
+product INTEL 82Q45_IGD		0x2e12	82Q45 Integrated Graphics Device
+product INTEL 82G45_HB		0x2e20	82G45 Host Bridge
+product INTEL 82G45_IGD		0x2e22	82G45 Integrated Graphics Device
 product INTEL 31244		0x3200	31244 Serial ATA Controller
 product INTEL 82855PM_DDR	0x3340	82855PM MCH Host Controller
 product INTEL 82855PM_AGP	0x3341	82855PM Host-AGP Bridge