Sync with HEAD nick-nhusb
authorskrll <skrll@NetBSD.org>
Mon, 05 Dec 2016 10:54:48 +0000
branchnick-nhusb
changeset 278624 e375aab2fc60
parent 278623 be62781bf99a
child 278625 18d8d4e89399
Sync with HEAD
sys/altq/altq_jobs.c
sys/arch/alpha/alpha/machdep.c
sys/arch/alpha/alpha/prom.c
sys/arch/alpha/conf/GENERIC
sys/arch/alpha/include/isa_machdep.h
sys/arch/alpha/stand/common/booted_dev.c
sys/arch/alpha/stand/common/prom.c
sys/arch/amd64/amd64/cpufunc.S
sys/arch/amd64/amd64/locore.S
sys/arch/amd64/amd64/machdep.c
sys/arch/amd64/amd64/netbsd32_machdep.c
sys/arch/amd64/amd64/trap.c
sys/arch/amd64/amd64/vector.S
sys/arch/amd64/conf/ALL
sys/arch/amd64/conf/GENERIC
sys/arch/amd64/include/i82093reg.h
sys/arch/amd64/include/netbsd32_machdep.h
sys/arch/amd64/include/pmap.h
sys/arch/amd64/include/ptrace.h
sys/arch/amd64/include/vmparam.h
sys/arch/amiga/conf/WSCONS
sys/arch/amiga/dev/grf_et.c
sys/arch/amiga/dev/grf_ul.c
sys/arch/amiga/dev/mntva.c
sys/arch/amigappc/conf/GENERIC
sys/arch/amigappc/conf/files.amigappc
sys/arch/arc/include/isa_machdep.h
sys/arch/arm/arm/cpufunc.c
sys/arch/arm/arm32/bus_dma.c
sys/arch/arm/broadcom/bcm2835_vcaudio.c
sys/arch/arm/broadcom/bcm53xx_board.c
sys/arch/arm/cortex/a9_mpsubr.S
sys/arch/arm/cortex/a9wdt.c
sys/arch/arm/cortex/scu_reg.h
sys/arch/arm/imx/files.imx6
sys/arch/arm/imx/files.imx7
sys/arch/arm/imx/if_enet_imx6.c
sys/arch/arm/imx/imx6_ahcisata.c
sys/arch/arm/imx/imx6_board.c
sys/arch/arm/imx/imx6_ccm.c
sys/arch/arm/imx/imx6_ccmreg.h
sys/arch/arm/imx/imx6_ccmvar.h
sys/arch/arm/imx/imx6_pcie.c
sys/arch/arm/imx/imx6_pciereg.h
sys/arch/arm/imx/imx6_usdhc.c
sys/arch/arm/imx/imx6var.h
sys/arch/arm/imx/imx7_board.c
sys/arch/arm/imx/imx7_ccm.c
sys/arch/arm/imx/imx7_ccmreg.h
sys/arch/arm/imx/imx7_gpcreg.h
sys/arch/arm/imx/imx7_rdcreg.h
sys/arch/arm/imx/imx7_srcreg.h
sys/arch/arm/include/isa_machdep.h
sys/arch/arm/include/ptrace.h
sys/arch/arm/nvidia/tegra_cpufreq.c
sys/arch/arm/omap/am335x_prcm.c
sys/arch/arm/omap/am335x_prcm.h
sys/arch/arm/omap/files.omap2
sys/arch/arm/omap/omap2430_intr.h
sys/arch/arm/omap/omap2_gpio.c
sys/arch/arm/omap/omap2_gpmc.c
sys/arch/arm/omap/omap2_icu.c
sys/arch/arm/omap/omap2_nand.c
sys/arch/arm/omap/omap2_obio.c
sys/arch/arm/omap/omap2_reg.h
sys/arch/arm/omap/omap3_ehci.c
sys/arch/arm/omap/omap3_sdhc.c
sys/arch/arm/omap/omap3_sdmmcreg.h
sys/arch/arm/omap/omap3_uhhreg.h
sys/arch/arm/omap/sitara_cm.c
sys/arch/arm/omap/sitara_cmreg.h
sys/arch/arm/omap/ti_iic.c
sys/arch/arm/omap/ti_iicreg.h
sys/arch/arm/omap/tifb.c
sys/arch/arm/omap/tifbreg.h
sys/arch/arm/omap/tifbvar.h
sys/arch/arm/sa11x0/sa11x0_ost.c
sys/arch/arm/zynq/zynq7000_board.c
sys/arch/atari/atari/le_bus.c
sys/arch/atari/include/isa_machdep.h
sys/arch/atari/stand/ahdilabel/ahdilabel.c
sys/arch/bebox/conf/GENERIC
sys/arch/bebox/include/isa_machdep.h
sys/arch/bebox/pci/pci_machdep.c
sys/arch/cobalt/conf/GENERIC64
sys/arch/cobalt/conf/INSTALL64
sys/arch/cobalt/conf/RAMDISK64
sys/arch/dreamcast/dev/g2/g2rtc.c
sys/arch/emips/ebus/ace_ebus.c
sys/arch/emips/ebus/flash_ebus.c
sys/arch/evbarm/awin/awin_machdep.c
sys/arch/evbarm/beagle/beagle_machdep.c
sys/arch/evbarm/conf/ARMADILLO-IOT-G3
sys/arch/evbarm/conf/BEAGLEBOARDXM
sys/arch/evbarm/conf/CUBOX-I
sys/arch/evbarm/conf/DUOVERO
sys/arch/evbarm/conf/GENERIC.common
sys/arch/evbarm/conf/GUMSTIX
sys/arch/evbarm/conf/HPT5325
sys/arch/evbarm/conf/HUMMINGBOARD
sys/arch/evbarm/conf/MARVELL_NAS
sys/arch/evbarm/conf/MMNET_GENERIC
sys/arch/evbarm/conf/MPCSA_GENERIC
sys/arch/evbarm/conf/MV2120
sys/arch/evbarm/conf/NITROGEN6X
sys/arch/evbarm/conf/OPENBLOCKS_A6
sys/arch/evbarm/conf/OPENBLOCKS_AX3
sys/arch/evbarm/conf/OVERO
sys/arch/evbarm/conf/PEPPER
sys/arch/evbarm/conf/README.evbarm
sys/arch/evbarm/conf/RPI
sys/arch/evbarm/conf/SHEEVAPLUG
sys/arch/evbarm/conf/VTC100
sys/arch/evbarm/conf/mk.gumstix
sys/arch/evbarm/conf/std.imx7
sys/arch/evbarm/conf/std.nitrogen6
sys/arch/evbarm/conf/std.overo
sys/arch/evbarm/gumstix/gumstix_machdep.c
sys/arch/evbarm/gumstix/gumstix_start.S
sys/arch/evbarm/gumstix/gumstixreg.h
sys/arch/evbarm/gumstix/gxio.c
sys/arch/evbarm/imx7/imx7_machdep.c
sys/arch/evbarm/iq80310/iq80310reg.h
sys/arch/evbarm/nitrogen6/nitrogen6_iomux.c
sys/arch/evbarm/nitrogen6/nitrogen6_usb.c
sys/arch/evbarm/rockchip/rockchip_machdep.c
sys/arch/evbarm/vexpress/vexpress_machdep.c
sys/arch/evbarm64/conf/A64EMUL
sys/arch/evbmips/cavium/machdep.c
sys/arch/evbmips/conf/LINKITSMART7688
sys/arch/evbmips/conf/files.rasoc
sys/arch/evbmips/rasoc/autoconf.c
sys/arch/evbmips/rasoc/console.c
sys/arch/evbmips/rasoc/machdep.c
sys/arch/evbppc/conf/INSTALL.inc
sys/arch/evbppc/pmppc/pci/pci_machdep.c
sys/arch/hpcmips/include/isa_machdep.h
sys/arch/hppa/include/isa_machdep.h
sys/arch/hppa/include/ptrace.h
sys/arch/i386/conf/ALL
sys/arch/i386/conf/GENERIC
sys/arch/i386/conf/INSTALL_FLOPPY
sys/arch/i386/i386/autoconf.c
sys/arch/i386/i386/i386func.S
sys/arch/i386/i386/locore.S
sys/arch/i386/i386/machdep.c
sys/arch/i386/i386/process_machdep.c
sys/arch/i386/i386/vector.S
sys/arch/i386/include/i82093reg.h
sys/arch/i386/include/vmparam.h
sys/arch/i386/stand/lib/biosmem.S
sys/arch/i386/stand/lib/biosmemps2.S
sys/arch/i386/stand/lib/biosmemx.S
sys/arch/i386/stand/lib/exec.c
sys/arch/i386/stand/lib/multiboot.S
sys/arch/i386/stand/lib/startprog.S
sys/arch/ia64/ia64/core_machdep.c
sys/arch/ia64/include/isa_machdep.h
sys/arch/ibmnws/include/isa_machdep.h
sys/arch/ibmnws/pci/pci_machdep.c
sys/arch/iyonix/conf/GENERIC
sys/arch/landisk/conf/GENERIC
sys/arch/luna68k/conf/GENERIC
sys/arch/luna68k/conf/files.luna68k
sys/arch/luna68k/conf/majors.luna68k
sys/arch/luna68k/dev/xp.c
sys/arch/luna68k/include/Makefile
sys/arch/luna68k/include/xpio.h
sys/arch/luna68k/luna68k/mainbus.c
sys/arch/luna68k/stand/boot/parse.c
sys/arch/macppc/conf/GENERIC
sys/arch/macppc/pci/pci_machdep.c
sys/arch/mips/cavium/octeon_intr.c
sys/arch/mips/include/asm.h
sys/arch/mips/include/cpu.h
sys/arch/mips/include/isa_machdep.h
sys/arch/mips/include/locore.h
sys/arch/mips/include/vmparam.h
sys/arch/mips/mips/cache_r5k.c
sys/arch/mips/mips/cpu_exec.c
sys/arch/mips/mips/cpu_subr.c
sys/arch/mips/mips/fp.S
sys/arch/mips/mips/locore.S
sys/arch/mips/mips/mipsX_subr.S
sys/arch/mips/mips/mips_fixup.c
sys/arch/mips/mips/spl.S
sys/arch/mips/ralink/ralink_com.c
sys/arch/mips/ralink/ralink_eth.c
sys/arch/mips/ralink/ralink_gpio.c
sys/arch/mips/ralink/ralink_gpio.h
sys/arch/mips/ralink/ralink_intr.c
sys/arch/mips/ralink/ralink_mainbus.c
sys/arch/mips/ralink/ralink_reg.h
sys/arch/mips/ralink/ralink_var.h
sys/arch/mipsco/include/isa_machdep.h
sys/arch/mipsco/mipsco/mips_3x30.c
sys/arch/mvmeppc/include/isa_machdep.h
sys/arch/mvmeppc/pci/pci_machdep.c
sys/arch/newsmips/newsmips/news3400.c
sys/arch/ofppc/include/isa_machdep.h
sys/arch/ofppc/pci/ofwpci.c
sys/arch/pmax/conf/GENERIC
sys/arch/pmax/conf/GENERIC64_USB
sys/arch/pmax/conf/GENERIC_USB
sys/arch/pmax/conf/files.pmax
sys/arch/pmax/conf/majors.pmax
sys/arch/pmax/ibus/ibus_3max.c
sys/arch/pmax/ibus/ibus_pmax.c
sys/arch/pmax/include/bus.h
sys/arch/pmax/pmax/bus.c
sys/arch/pmax/tc/tcbus.c
sys/arch/powerpc/booke/e500_intr.c
sys/arch/powerpc/booke/pci/pq3pci.c
sys/arch/powerpc/ibm4xx/dev/ibm405gp.c
sys/arch/powerpc/include/booke/intr.h
sys/arch/powerpc/include/cpu.h
sys/arch/powerpc/include/intr.h
sys/arch/powerpc/include/pci_machdep.h
sys/arch/powerpc/marvell/pci_machdep.c
sys/arch/powerpc/pci/pci_machdep_common.c
sys/arch/powerpc/pic/intr.c
sys/arch/powerpc/powerpc/intr_stubs.c
sys/arch/prep/conf/GENERIC
sys/arch/prep/include/isa_machdep.h
sys/arch/prep/pci/pci_machdep.c
sys/arch/prep/pci/prep_pciconf_direct.c
sys/arch/sandpoint/include/isa_machdep.h
sys/arch/sandpoint/include/pci_machdep.h
sys/arch/sandpoint/pci/pci_machdep.c
sys/arch/sgimips/sgimips/bus.c
sys/arch/sgimips/sgimips/cpu.c
sys/arch/sgimips/sgimips/machdep.c
sys/arch/sh3/include/userret.h
sys/arch/sh3/sh3/exception_vector.S
sys/arch/sh3/sh3/process_machdep.c
sys/arch/sh3/sh3/sh3_machdep.c
sys/arch/shark/shark/sequoia.c
sys/arch/sparc/conf/GENERIC
sys/arch/sparc/conf/KRUPS
sys/arch/sparc/conf/Makefile.sparc
sys/arch/sparc/include/cpuconf.h
sys/arch/sparc/include/ptrace.h
sys/arch/sparc/stand/ofwboot/loadfile_machdep.c
sys/arch/sparc64/conf/GENERIC
sys/arch/sparc64/dev/auxio.c
sys/arch/sparc64/dev/ffb.c
sys/arch/sparc64/dev/ffb_mainbus.c
sys/arch/sparc64/dev/gfb.c
sys/arch/sparc64/dev/pyro.c
sys/arch/sparc64/dev/sbus.c
sys/arch/sparc64/dev/schizo.c
sys/arch/sparc64/include/bus_defs.h
sys/arch/sparc64/include/netbsd32_machdep.h
sys/arch/sparc64/include/pmap.h
sys/arch/sparc64/include/pte.h
sys/arch/sparc64/include/ptrace.h
sys/arch/sparc64/sparc64/machdep.c
sys/arch/sparc64/sparc64/netbsd32_machdep.c
sys/arch/sparc64/sparc64/pmap.c
sys/arch/x68k/x68k/machdep.c
sys/arch/x86/acpi/acpi_machdep.c
sys/arch/x86/acpi/acpi_wakeup.c
sys/arch/x86/include/cpufunc.h
sys/arch/x86/include/dbregs.h
sys/arch/x86/include/i82489var.h
sys/arch/x86/include/isa_machdep.h
sys/arch/x86/include/pmap.h
sys/arch/x86/isa/isa_machdep.c
sys/arch/x86/pci/if_vmx.c
sys/arch/x86/pci/if_vmxreg.h
sys/arch/x86/pci/pci_intr_machdep.c
sys/arch/x86/pci/pci_msi_machdep.c
sys/arch/x86/pci/pciide_machdep.c
sys/arch/x86/x86/cpu.c
sys/arch/x86/x86/cpu_ucode_intel.c
sys/arch/x86/x86/intr.c
sys/arch/x86/x86/lapic.c
sys/arch/x86/x86/pmap.c
sys/arch/x86/x86/pmap_tlb.c
sys/arch/x86/x86/vm_machdep.c
sys/arch/x86/x86/vmt.c
sys/arch/x86/x86/x86_machdep.c
sys/arch/xen/include/intr.h
sys/arch/xen/x86/cpu.c
sys/arch/xen/x86/intr.c
sys/arch/xen/x86/x86_xpmap.c
sys/arch/xen/x86/xen_pmap.c
sys/arch/xen/x86/xenfunc.c
sys/compat/common/Makefile
sys/compat/common/Makefile.sysio
sys/compat/common/Makefile.sysv
sys/compat/common/compat_mod.c
sys/compat/common/if_43.c
sys/compat/common/if_43.h
sys/compat/common/kern_time_30.c
sys/compat/common/rtsock_14.c
sys/compat/linux/common/linux_misc.c
sys/compat/linux32/common/linux32_wait.c
sys/compat/netbsd32/files.netbsd32
sys/compat/netbsd32/netbsd32.h
sys/compat/netbsd32/netbsd32_conv.h
sys/compat/netbsd32/netbsd32_fs.c
sys/compat/netbsd32/netbsd32_ioctl.c
sys/compat/netbsd32/netbsd32_ioctl.h
sys/compat/netbsd32/netbsd32_netbsd.c
sys/compat/netbsd32/netbsd32_nfssvc.c
sys/compat/netbsd32/netbsd32_ptrace.c
sys/compat/netbsd32/netbsd32_syscall.h
sys/compat/netbsd32/netbsd32_syscallargs.h
sys/compat/netbsd32/netbsd32_syscalls.c
sys/compat/netbsd32/netbsd32_syscalls_autoload.c
sys/compat/netbsd32/netbsd32_sysent.c
sys/compat/netbsd32/syscalls.master
sys/compat/osf1/osf1_misc.c
sys/compat/sunos/sunos_ioctl.c
sys/compat/svr4/svr4_misc.c
sys/compat/svr4_32/svr4_32_misc.c
sys/compat/ultrix/ultrix_ioctl.c
sys/conf/files
sys/conf/std
sys/dev/acpi/acpi_verbose.c
sys/dev/acpi/pckbc_acpi.c
sys/dev/ata/wd.c
sys/dev/ccd.c
sys/dev/clockctl.c
sys/dev/dev_verbose.c
sys/dev/devlist2h.awk
sys/dev/dksubr.c
sys/dev/fdt/fdt_gpio.c
sys/dev/fdt/fdt_pinctrl.c
sys/dev/hdaudio/Makefile.hdaudiodevs
sys/dev/hdaudio/hdafg.c
sys/dev/hil/devlist2h.awk
sys/dev/i2c/ds1307.c
sys/dev/i2c/ds1307reg.h
sys/dev/i2c/tps65217pmic.c
sys/dev/ic/aic7xxx_cam.h
sys/dev/ic/aic7xxx_osm.c
sys/dev/ic/ld_nvme.c
sys/dev/ic/nvme.c
sys/dev/ic/nvmereg.h
sys/dev/ic/nvmevar.h
sys/dev/ic/rt2860.c
sys/dev/ic/rt2860reg.h
sys/dev/ic/rtwphyio.c
sys/dev/ieee1394/firewire.c
sys/dev/ieee1394/firewirereg.h
sys/dev/ieee1394/fwdev.c
sys/dev/ieee1394/fwohci.c
sys/dev/if_ndis/if_ndis_pci.c
sys/dev/isa/com_isa.c
sys/dev/isa/files.isa
sys/dev/isa/isa_stub.c
sys/dev/ld.c
sys/dev/marvell/gt.c
sys/dev/marvell/if_mvxpe.c
sys/dev/marvell/marvellreg.h
sys/dev/marvell/mvspi.c
sys/dev/mii/atphy.c
sys/dev/mii/igphyreg.h
sys/dev/mii/ihphy.c
sys/dev/mii/ikphy.c
sys/dev/mii/ikphyreg.h
sys/dev/mii/inbmphyreg.h
sys/dev/mii/inphy.c
sys/dev/mii/makphy.c
sys/dev/mii/mii.h
sys/dev/mm.c
sys/dev/nand/nand.c
sys/dev/pad/pad.c
sys/dev/pci/Makefile.pcidevs
sys/dev/pci/ahcisata_pci.c
sys/dev/pci/bha_pci.c
sys/dev/pci/cxgb/cxgb_l2t.c
sys/dev/pci/ehci_pci.c
sys/dev/pci/files.pci
sys/dev/pci/ichsmb.c
sys/dev/pci/if_iwn.c
sys/dev/pci/if_msk.c
sys/dev/pci/if_vioif.c
sys/dev/pci/if_wm.c
sys/dev/pci/if_wmreg.h
sys/dev/pci/if_wmvar.h
sys/dev/pci/ixgbe/LICENSE
sys/dev/pci/ixgbe/README
sys/dev/pci/ixgbe/ix_txrx.c
sys/dev/pci/ixgbe/ixgbe.c
sys/dev/pci/ixgbe/ixgbe.h
sys/dev/pci/ixgbe/ixgbe_82598.c
sys/dev/pci/ixgbe/ixgbe_82598.h
sys/dev/pci/ixgbe/ixgbe_82599.c
sys/dev/pci/ixgbe/ixgbe_82599.h
sys/dev/pci/ixgbe/ixgbe_api.c
sys/dev/pci/ixgbe/ixgbe_api.h
sys/dev/pci/ixgbe/ixgbe_common.c
sys/dev/pci/ixgbe/ixgbe_common.h
sys/dev/pci/ixgbe/ixgbe_dcb.c
sys/dev/pci/ixgbe/ixgbe_dcb.h
sys/dev/pci/ixgbe/ixgbe_dcb_82598.c
sys/dev/pci/ixgbe/ixgbe_dcb_82598.h
sys/dev/pci/ixgbe/ixgbe_dcb_82599.c
sys/dev/pci/ixgbe/ixgbe_dcb_82599.h
sys/dev/pci/ixgbe/ixgbe_mbx.c
sys/dev/pci/ixgbe/ixgbe_mbx.h
sys/dev/pci/ixgbe/ixgbe_netbsd.c
sys/dev/pci/ixgbe/ixgbe_netbsd.h
sys/dev/pci/ixgbe/ixgbe_osdep.c
sys/dev/pci/ixgbe/ixgbe_osdep.h
sys/dev/pci/ixgbe/ixgbe_phy.c
sys/dev/pci/ixgbe/ixgbe_phy.h
sys/dev/pci/ixgbe/ixgbe_type.h
sys/dev/pci/ixgbe/ixgbe_vf.c
sys/dev/pci/ixgbe/ixgbe_vf.h
sys/dev/pci/ixgbe/ixgbe_x540.c
sys/dev/pci/ixgbe/ixgbe_x540.h
sys/dev/pci/ixgbe/ixgbe_x550.c
sys/dev/pci/ixgbe/ixgbe_x550.h
sys/dev/pci/ixgbe/ixv.c
sys/dev/pci/ixgbe/ixv.h
sys/dev/pci/ld_virtio.c
sys/dev/pci/nvme_pci.c
sys/dev/pci/pci_stub.c
sys/dev/pci/pci_subr.c
sys/dev/pci/pci_verbose.h
sys/dev/pci/pcidevs
sys/dev/pci/pcidevs.h
sys/dev/pci/pcidevs_data.h
sys/dev/pci/pciide_common.c
sys/dev/pci/pcireg.h
sys/dev/pci/pcivar.h
sys/dev/pci/piixpm.c
sys/dev/pci/pm3fb.c
sys/dev/pci/pm3reg.h
sys/dev/pci/siop_pci_common.c
sys/dev/pci/viornd.c
sys/dev/pci/vioscsi.c
sys/dev/pci/virtio.c
sys/dev/pci/voyager.c
sys/dev/pci/xhci_pci.c
sys/dev/pcmcia/if_tr_pcmcia.c
sys/dev/raidframe/rf_map.c
sys/dev/scsipi/atapi_wdc.c
sys/dev/scsipi/atapiconf.c
sys/dev/scsipi/cd.c
sys/dev/scsipi/ch.c
sys/dev/scsipi/if_se.c
sys/dev/scsipi/scsi_base.c
sys/dev/scsipi/scsi_disk.h
sys/dev/scsipi/scsiconf.c
sys/dev/scsipi/scsipi_base.c
sys/dev/scsipi/scsipi_base.h
sys/dev/scsipi/scsipi_ioctl.c
sys/dev/scsipi/scsipiconf.c
sys/dev/scsipi/scsipiconf.h
sys/dev/scsipi/sd.c
sys/dev/scsipi/ses.c
sys/dev/scsipi/ss.c
sys/dev/scsipi/ss_mustek.c
sys/dev/scsipi/ss_scanjet.c
sys/dev/scsipi/st.c
sys/dev/scsipi/uk.c
sys/dev/spi/mcp3k.c
sys/dev/sun/cgthree.c
sys/dev/tc/tcdevs.h
sys/dev/tc/tcdevs_data.h
sys/dev/tc/tcu.c
sys/dev/usb/Makefile.usbdevs
sys/dev/usb/TODO.usbmp
sys/dev/usb/auvitek_i2c.c
sys/dev/usb/emdtv.c
sys/dev/usb/ezload.c
sys/dev/usb/files.usb
sys/dev/usb/hid.c
sys/dev/usb/if_athn_usb.c
sys/dev/usb/if_atu.c
sys/dev/usb/if_aue.c
sys/dev/usb/if_axe.c
sys/dev/usb/if_axen.c
sys/dev/usb/if_axereg.h
sys/dev/usb/if_cue.c
sys/dev/usb/if_kue.c
sys/dev/usb/if_otus.c
sys/dev/usb/if_rum.c
sys/dev/usb/if_run.c
sys/dev/usb/if_udav.c
sys/dev/usb/if_upgt.c
sys/dev/usb/if_upl.c
sys/dev/usb/if_ural.c
sys/dev/usb/if_url.c
sys/dev/usb/if_urndis.c
sys/dev/usb/if_urndisreg.h
sys/dev/usb/if_urtw.c
sys/dev/usb/if_urtwn.c
sys/dev/usb/if_urtwn_data.h
sys/dev/usb/if_urtwnreg.h
sys/dev/usb/if_urtwnvar.h
sys/dev/usb/if_zyd.c
sys/dev/usb/ohci.c
sys/dev/usb/stuirda.c
sys/dev/usb/uark.c
sys/dev/usb/uatp.c
sys/dev/usb/uberry.c
sys/dev/usb/ubsa.c
sys/dev/usb/ubt.c
sys/dev/usb/uchcom.c
sys/dev/usb/ucom.c
sys/dev/usb/ucycom.c
sys/dev/usb/udl.c
sys/dev/usb/udl.h
sys/dev/usb/udsbr.c
sys/dev/usb/uftdi.c
sys/dev/usb/ugensa.c
sys/dev/usb/uhci.c
sys/dev/usb/uhidev.c
sys/dev/usb/uhmodem.c
sys/dev/usb/uhso.c
sys/dev/usb/uhub.c
sys/dev/usb/uipad.c
sys/dev/usb/uipaq.c
sys/dev/usb/uirda.c
sys/dev/usb/uirdavar.h
sys/dev/usb/ukbd.c
sys/dev/usb/ukyopon.c
sys/dev/usb/ulpt.c
sys/dev/usb/umass.c
sys/dev/usb/umass_isdata.c
sys/dev/usb/umass_scsipi.c
sys/dev/usb/umct.c
sys/dev/usb/umidi.c
sys/dev/usb/umidi_quirks.c
sys/dev/usb/umodem_common.c
sys/dev/usb/uplcom.c
sys/dev/usb/urio.c
sys/dev/usb/usb_quirks.c
sys/dev/usb/usb_subr.c
sys/dev/usb/usbdevs
sys/dev/usb/usbdevs.h
sys/dev/usb/usbdevs_data.h
sys/dev/usb/usbdi.c
sys/dev/usb/uscanner.c
sys/dev/usb/uslsa.c
sys/dev/usb/usscanner.c
sys/dev/usb/ustir.c
sys/dev/usb/uthum.c
sys/dev/usb/utoppy.c
sys/dev/usb/uvisor.c
sys/dev/usb/uvscom.c
sys/dev/usb/uyurex.c
sys/dev/wsfont/Go_Mono_12x23.h
sys/dev/wsfont/files.wsfont
sys/dev/wsfont/wsfont.c
sys/dev/wsfont/wsfont.h
sys/external/bsd/acpica/conf/files.acpica
sys/external/bsd/acpica/dist/changes.txt
sys/external/bsd/acpica/dist/common/acfileio.c
sys/external/bsd/acpica/dist/common/acgetline.c
sys/external/bsd/acpica/dist/common/adisasm.c
sys/external/bsd/acpica/dist/common/ahtable.c
sys/external/bsd/acpica/dist/common/cmfsize.c
sys/external/bsd/acpica/dist/common/dmtable.c
sys/external/bsd/acpica/dist/common/dmtables.c
sys/external/bsd/acpica/dist/common/dmtbdump.c
sys/external/bsd/acpica/dist/common/dmtbinfo.c
sys/external/bsd/acpica/dist/common/getopt.c
sys/external/bsd/acpica/dist/compiler/aslcompiler.h
sys/external/bsd/acpica/dist/compiler/aslcstyle.y
sys/external/bsd/acpica/dist/compiler/aslhelp.c
sys/external/bsd/acpica/dist/compiler/aslhelpers.y
sys/external/bsd/acpica/dist/compiler/aslkeywords.y
sys/external/bsd/acpica/dist/compiler/aslmain.c
sys/external/bsd/acpica/dist/compiler/aslmaputils.c
sys/external/bsd/acpica/dist/compiler/asloperands.c
sys/external/bsd/acpica/dist/compiler/aslopt.c
sys/external/bsd/acpica/dist/compiler/asloptions.c
sys/external/bsd/acpica/dist/compiler/aslparser.y
sys/external/bsd/acpica/dist/compiler/aslprimaries.y
sys/external/bsd/acpica/dist/compiler/aslresources.y
sys/external/bsd/acpica/dist/compiler/aslrules.y
sys/external/bsd/acpica/dist/compiler/aslstubs.c
sys/external/bsd/acpica/dist/compiler/asltokens.y
sys/external/bsd/acpica/dist/compiler/asltypes.y
sys/external/bsd/acpica/dist/compiler/aslutils.c
sys/external/bsd/acpica/dist/compiler/aslxref.c
sys/external/bsd/acpica/dist/compiler/dtcompiler.h
sys/external/bsd/acpica/dist/compiler/dtfield.c
sys/external/bsd/acpica/dist/compiler/dtparser.y
sys/external/bsd/acpica/dist/compiler/dttable.c
sys/external/bsd/acpica/dist/compiler/dttemplate.h
sys/external/bsd/acpica/dist/compiler/dtutils.c
sys/external/bsd/acpica/dist/compiler/prparser.y
sys/external/bsd/acpica/dist/debugger/dbconvert.c
sys/external/bsd/acpica/dist/debugger/dbexec.c
sys/external/bsd/acpica/dist/debugger/dbfileio.c
sys/external/bsd/acpica/dist/debugger/dbinput.c
sys/external/bsd/acpica/dist/debugger/dbmethod.c
sys/external/bsd/acpica/dist/disassembler/dmbuffer.c
sys/external/bsd/acpica/dist/disassembler/dmcstyle.c
sys/external/bsd/acpica/dist/disassembler/dmopcode.c
sys/external/bsd/acpica/dist/disassembler/dmresrcl.c
sys/external/bsd/acpica/dist/disassembler/dmresrcl2.c
sys/external/bsd/acpica/dist/dispatcher/dsmethod.c
sys/external/bsd/acpica/dist/dispatcher/dswexec.c
sys/external/bsd/acpica/dist/dispatcher/dswload2.c
sys/external/bsd/acpica/dist/events/evgpe.c
sys/external/bsd/acpica/dist/events/evgpeinit.c
sys/external/bsd/acpica/dist/events/evrgnini.c
sys/external/bsd/acpica/dist/events/evxfgpe.c
sys/external/bsd/acpica/dist/executer/exconcat.c
sys/external/bsd/acpica/dist/executer/exconfig.c
sys/external/bsd/acpica/dist/executer/exconvrt.c
sys/external/bsd/acpica/dist/executer/exmisc.c
sys/external/bsd/acpica/dist/executer/exoparg1.c
sys/external/bsd/acpica/dist/executer/exresop.c
sys/external/bsd/acpica/dist/executer/extrace.c
sys/external/bsd/acpica/dist/executer/exutils.c
sys/external/bsd/acpica/dist/generate/unix/acpibin/Makefile
sys/external/bsd/acpica/dist/generate/unix/acpidump/Makefile
sys/external/bsd/acpica/dist/generate/unix/acpiexamples/Makefile
sys/external/bsd/acpica/dist/generate/unix/acpiexec/Makefile
sys/external/bsd/acpica/dist/generate/unix/acpihelp/Makefile
sys/external/bsd/acpica/dist/generate/unix/acpinames/Makefile
sys/external/bsd/acpica/dist/generate/unix/acpisrc/Makefile
sys/external/bsd/acpica/dist/generate/unix/acpixtract/Makefile
sys/external/bsd/acpica/dist/generate/unix/iasl/Makefile
sys/external/bsd/acpica/dist/hardware/hwgpe.c
sys/external/bsd/acpica/dist/include/acapps.h
sys/external/bsd/acpica/dist/include/acclib.h
sys/external/bsd/acpica/dist/include/acconfig.h
sys/external/bsd/acpica/dist/include/acdebug.h
sys/external/bsd/acpica/dist/include/acdisasm.h
sys/external/bsd/acpica/dist/include/acevents.h
sys/external/bsd/acpica/dist/include/acglobal.h
sys/external/bsd/acpica/dist/include/aclocal.h
sys/external/bsd/acpica/dist/include/acnamesp.h
sys/external/bsd/acpica/dist/include/acparser.h
sys/external/bsd/acpica/dist/include/acpiosxf.h
sys/external/bsd/acpica/dist/include/acpixf.h
sys/external/bsd/acpica/dist/include/actables.h
sys/external/bsd/acpica/dist/include/actbl.h
sys/external/bsd/acpica/dist/include/actypes.h
sys/external/bsd/acpica/dist/include/acutils.h
sys/external/bsd/acpica/dist/include/platform/accygwin.h
sys/external/bsd/acpica/dist/include/platform/acdragonfly.h
sys/external/bsd/acpica/dist/include/platform/acefi.h
sys/external/bsd/acpica/dist/include/platform/acefiex.h
sys/external/bsd/acpica/dist/include/platform/acenv.h
sys/external/bsd/acpica/dist/include/platform/acenvex.h
sys/external/bsd/acpica/dist/include/platform/acfreebsd.h
sys/external/bsd/acpica/dist/include/platform/acgcc.h
sys/external/bsd/acpica/dist/include/platform/acgccex.h
sys/external/bsd/acpica/dist/include/platform/achaiku.h
sys/external/bsd/acpica/dist/include/platform/acintel.h
sys/external/bsd/acpica/dist/include/platform/aclinux.h
sys/external/bsd/acpica/dist/include/platform/aclinuxex.h
sys/external/bsd/acpica/dist/include/platform/acmacosx.h
sys/external/bsd/acpica/dist/include/platform/acmsvc.h
sys/external/bsd/acpica/dist/include/platform/acmsvcex.h
sys/external/bsd/acpica/dist/include/platform/acnetbsd.h
sys/external/bsd/acpica/dist/include/platform/acos2.h
sys/external/bsd/acpica/dist/include/platform/acqnx.h
sys/external/bsd/acpica/dist/include/platform/acwin.h
sys/external/bsd/acpica/dist/include/platform/acwin64.h
sys/external/bsd/acpica/dist/include/platform/acwinex.h
sys/external/bsd/acpica/dist/namespace/nsconvert.c
sys/external/bsd/acpica/dist/namespace/nsload.c
sys/external/bsd/acpica/dist/namespace/nsparse.c
sys/external/bsd/acpica/dist/namespace/nsutils.c
sys/external/bsd/acpica/dist/os_specific/service_layers/osefitbl.c
sys/external/bsd/acpica/dist/os_specific/service_layers/osefixf.c
sys/external/bsd/acpica/dist/os_specific/service_layers/oslibcfs.c
sys/external/bsd/acpica/dist/os_specific/service_layers/osunixxf.c
sys/external/bsd/acpica/dist/os_specific/service_layers/oswintbl.c
sys/external/bsd/acpica/dist/os_specific/service_layers/oswinxf.c
sys/external/bsd/acpica/dist/parser/psparse.c
sys/external/bsd/acpica/dist/parser/psxface.c
sys/external/bsd/acpica/dist/tables/tbdata.c
sys/external/bsd/acpica/dist/tables/tbfadt.c
sys/external/bsd/acpica/dist/tables/tbfind.c
sys/external/bsd/acpica/dist/tables/tbinstal.c
sys/external/bsd/acpica/dist/tables/tbutils.c
sys/external/bsd/acpica/dist/tables/tbxface.c
sys/external/bsd/acpica/dist/tables/tbxfload.c
sys/external/bsd/acpica/dist/tables/tbxfroot.c
sys/external/bsd/acpica/dist/tools/acpibin/abcompare.c
sys/external/bsd/acpica/dist/tools/acpibin/abmain.c
sys/external/bsd/acpica/dist/tools/acpibin/acpibin.h
sys/external/bsd/acpica/dist/tools/acpidump/acpidump.h
sys/external/bsd/acpica/dist/tools/acpidump/apdump.c
sys/external/bsd/acpica/dist/tools/acpidump/apfiles.c
sys/external/bsd/acpica/dist/tools/acpidump/apmain.c
sys/external/bsd/acpica/dist/tools/acpiexec/aecommon.h
sys/external/bsd/acpica/dist/tools/acpiexec/aeexec.c
sys/external/bsd/acpica/dist/tools/acpiexec/aehandlers.c
sys/external/bsd/acpica/dist/tools/acpiexec/aeinitfile.c
sys/external/bsd/acpica/dist/tools/acpiexec/aemain.c
sys/external/bsd/acpica/dist/tools/acpihelp/acpihelp.h
sys/external/bsd/acpica/dist/tools/acpihelp/ahamlops.c
sys/external/bsd/acpica/dist/tools/acpihelp/ahdecode.c
sys/external/bsd/acpica/dist/tools/acpihelp/ahgrammar.c
sys/external/bsd/acpica/dist/tools/acpihelp/ahmain.c
sys/external/bsd/acpica/dist/tools/acpinames/anmain.c
sys/external/bsd/acpica/dist/tools/acpisrc/acpisrc.h
sys/external/bsd/acpica/dist/tools/acpisrc/asfile.c
sys/external/bsd/acpica/dist/tools/acpisrc/asmain.c
sys/external/bsd/acpica/dist/tools/acpisrc/astable.c
sys/external/bsd/acpica/dist/utilities/utaddress.c
sys/external/bsd/acpica/dist/utilities/utbuffer.c
sys/external/bsd/acpica/dist/utilities/utdebug.c
sys/external/bsd/acpica/dist/utilities/uthex.c
sys/external/bsd/acpica/dist/utilities/utinit.c
sys/external/bsd/acpica/dist/utilities/utnonansi.c
sys/external/bsd/acpica/dist/utilities/utosi.c
sys/external/bsd/acpica/dist/utilities/utpredef.c
sys/external/bsd/acpica/dist/utilities/utprint.c
sys/external/bsd/acpica/dist/utilities/utstrtoul64.c
sys/external/bsd/acpica/dist/utilities/uttrack.c
sys/external/bsd/acpica/dist/utilities/utxface.c
sys/external/bsd/acpica/dist/utilities/utxfinit.c
sys/external/bsd/drm2/dist/drm/drm_gem.c
sys/external/bsd/drm2/dist/drm/nouveau/core/engine/disp/nouveau_engine_disp_dport.c
sys/external/bsd/drm2/drm/drm_vma_manager.c
sys/external/bsd/dwc2/dwc2.c
sys/external/bsd/ipf/netinet/ip_ftp_pxy.c
sys/external/bsd/ipf/netinet/ip_nat.c
sys/external/bsd/ipf/netinet/ip_nat6.c
sys/external/isc/atheros_hal/dist/ar5416/ar5416_attach.c
sys/fs/nfs/client/nfs.h
sys/fs/nfs/client/nfs_clbio.c
sys/fs/nfs/client/nfs_clcomsubs.c
sys/fs/nfs/client/nfs_clkdtrace.c
sys/fs/nfs/client/nfs_clmodule.c
sys/fs/nfs/client/nfs_clnode.c
sys/fs/nfs/client/nfs_clport.c
sys/fs/nfs/client/nfs_clrpcops.c
sys/fs/nfs/client/nfs_clstate.c
sys/fs/nfs/client/nfs_clsubs.c
sys/fs/nfs/client/nfs_clvfsops.c
sys/fs/nfs/client/nfs_clvnops.c
sys/fs/nfs/client/nfs_kdtrace.h
sys/fs/nfs/client/nfsmount.h
sys/fs/nfs/client/nfsnode.h
sys/fs/nfs/common/bootp_subr.c
sys/fs/nfs/common/krpc_subr.c
sys/fs/nfs/common/nfs.h
sys/fs/nfs/common/nfs_commonacl.c
sys/fs/nfs/common/nfs_commonkrpc.c
sys/fs/nfs/common/nfs_commonport.c
sys/fs/nfs/common/nfs_commonsubs.c
sys/fs/nfs/common/nfs_diskless.c
sys/fs/nfs/common/nfs_fha.c
sys/fs/nfs/common/nfs_fha.h
sys/fs/nfs/common/nfs_lock.c
sys/fs/nfs/common/nfs_module.c
sys/fs/nfs/common/nfs_nfssvc.c
sys/fs/nfs/common/nfs_var.h
sys/fs/nfs/common/nfsclstate.h
sys/fs/nfs/common/nfsdport.h
sys/fs/nfs/common/nfsm_subs.h
sys/fs/nfs/common/nfsport.h
sys/fs/nfs/common/nfsproto.h
sys/fs/nfs/common/nfsrvcache.h
sys/fs/nfs/common/nfsrvstate.h
sys/fs/nfs/common/nfssvc.h
sys/fs/nfs/files.newnfs
sys/fs/nfs/nlm/nlm_advlock.c
sys/fs/nfs/nlm/nlm_prot_impl.c
sys/fs/nfs/server/nfs_fha_new.c
sys/fs/nfs/server/nfs_nfsdcache.c
sys/fs/nfs/server/nfs_nfsdkrpc.c
sys/fs/nfs/server/nfs_nfsdmodule.c
sys/fs/nfs/server/nfs_nfsdport.c
sys/fs/nfs/server/nfs_nfsdserv.c
sys/fs/nfs/server/nfs_nfsdsocket.c
sys/fs/nfs/server/nfs_nfsdstate.c
sys/fs/nfs/server/nfs_nfsdsubs.c
sys/kern/bufq_disksort.c
sys/kern/bufq_fcfs.c
sys/kern/bufq_priocscan.c
sys/kern/bufq_readprio.c
sys/kern/files.kern
sys/kern/init_main.c
sys/kern/init_sysent.c
sys/kern/kern_exec.c
sys/kern/kern_exit.c
sys/kern/kern_fork.c
sys/kern/kern_proc.c
sys/kern/kern_sig.c
sys/kern/kern_stub.c
sys/kern/kern_time.c
sys/kern/makesyscalls.sh
sys/kern/subr_bufq.c
sys/kern/subr_psref.c
sys/kern/subr_tftproot.c
sys/kern/subr_xcall.c
sys/kern/sys_process.c
sys/kern/sys_ptrace.c
sys/kern/sys_ptrace_common.c
sys/kern/syscalls.c
sys/kern/syscalls.master
sys/kern/syscalls_autoload.c
sys/kern/uipc_sem.c
sys/kern/uipc_syscalls.c
sys/kern/uipc_usrreq.c
sys/kern/vfs_bio.c
sys/kern/vfs_mount.c
sys/kern/vfs_subr.c
sys/kern/vfs_vnode.c
sys/kern/vfs_wapbl.c
sys/lib/libsa/loadfile.h
sys/lib/libsa/loadfile_elf32.c
sys/miscfs/procfs/files.procfs
sys/miscfs/procfs/procfs_status.c
sys/miscfs/procfs/procfs_vfsops.c
sys/modules/Makefile
sys/modules/bufq_disksort/Makefile
sys/modules/bufq_fcfs/Makefile
sys/modules/bufq_priocscan/Makefile
sys/modules/bufq_readprio/Makefile
sys/modules/compat/Makefile
sys/modules/compat_netbsd32_ptrace/Makefile
sys/modules/ptrace/Makefile
sys/modules/ptrace_common/Makefile
sys/modules/sysv_ipc/Makefile
sys/net/if.c
sys/net/if.h
sys/net/if_ethersubr.c
sys/net/if_llatbl.c
sys/net/if_loop.c
sys/net/if_pppoe.c
sys/net/if_spppsubr.c
sys/net/if_spppvar.h
sys/net/if_vlan.c
sys/net/link_proto.c
sys/net/npf/npf_inet.c
sys/net/radix.c
sys/net/radix.h
sys/net/route.c
sys/net/route.h
sys/net/rtbl.c
sys/net/rtsock.c
sys/net80211/ieee80211_crypto_wep.c
sys/netinet/if_arp.c
sys/netinet/if_inarp.h
sys/netinet/in.c
sys/netinet/in_var.h
sys/netinet/ip_carp.c
sys/netinet/ip_flow.c
sys/netinet/ip_icmp.c
sys/netinet/ip_input.c
sys/netinet/tcp_input.c
sys/netinet/tcp_subr.c
sys/netinet/tcp_usrreq.c
sys/netinet/udp_usrreq.c
sys/netinet6/dccp6_usrreq.c
sys/netinet6/frag6.c
sys/netinet6/icmp6.c
sys/netinet6/in6.c
sys/netinet6/in6_ifattach.c
sys/netinet6/in6_pcb.c
sys/netinet6/in6_src.c
sys/netinet6/ip6_flow.c
sys/netinet6/ip6_input.c
sys/netinet6/ip6_output.c
sys/netinet6/ip6_var.h
sys/netinet6/mld6.c
sys/netinet6/nd6.c
sys/netinet6/nd6_nbr.c
sys/netinet6/nd6_rtr.c
sys/netinet6/raw_ip6.c
sys/netinet6/sctp6_usrreq.c
sys/netinet6/udp6_output.c
sys/netinet6/udp6_usrreq.c
sys/netmpls/mpls.h
sys/nfs/nfs_boot.c
sys/nfs/nfs_export.c
sys/rump/include/opt/vlan.h
sys/rump/include/rump/rump_syscalls.h
sys/rump/librump/rumpkern/rump_syscalls.c
sys/rump/librump/rumpnet/net_stub.c
sys/rump/librump/rumpvfs/rump_vfs.c
sys/rump/net/Makefile.rumpnetcomp
sys/rump/net/lib/libsockin/sockin.c
sys/rump/net/lib/libvlan/Makefile
sys/rump/net/lib/libvlan/VLAN.ioconf
sys/rump/net/lib/libvlan/vlan_component.c
sys/sys/bufq.h
sys/sys/bufq_impl.h
sys/sys/disk.h
sys/sys/fstypes.h
sys/sys/module.h
sys/sys/param.h
sys/sys/proc.h
sys/sys/pslist.h
sys/sys/ptrace.h
sys/sys/syscall.h
sys/sys/syscallargs.h
sys/sys/vnode.h
sys/sys/vnode_impl.h
sys/sys/wait.h
sys/sys/wapbl.h
sys/ufs/ffs/ffs_alloc.c
sys/ufs/ffs/ffs_inode.c
sys/ufs/ffs/ffs_snapshot.c
sys/ufs/ffs/ffs_vfsops.c
sys/ufs/ffs/ffs_wapbl.c
sys/ufs/lfs/lfs_pages.c
sys/ufs/lfs/ulfs_extattr.c
sys/ufs/lfs/ulfs_quota2.c
sys/ufs/ufs/ufs_extattr.c
sys/ufs/ufs/ufs_extern.h
sys/ufs/ufs/ufs_inode.c
sys/ufs/ufs/ufs_quota2.c
sys/ufs/ufs/ufs_rename.c
sys/ufs/ufs/ufs_vnops.c
sys/ufs/ufs/ufs_wapbl.h
sys/uvm/files.uvm
sys/uvm/pmap/pmap.c
sys/uvm/pmap/pmap_segtab.c
sys/uvm/pmap/pmap_tlb.c
sys/uvm/uvm_map.c
sys/uvm/uvm_stat.c
--- a/sys/altq/altq_jobs.c	Sun Nov 06 11:50:54 2016 +0000
+++ b/sys/altq/altq_jobs.c	Mon Dec 05 10:54:48 2016 +0000
@@ -1,4 +1,4 @@
-/*	$NetBSD: altq_jobs.c,v 1.7.2.2 2016/04/22 15:44:08 skrll Exp $	*/
+/*	$NetBSD: altq_jobs.c,v 1.7.2.3 2016/12/05 10:54:48 skrll Exp $	*/
 /*	$KAME: altq_jobs.c,v 1.11 2005/04/13 03:44:25 suz Exp $	*/
 /*
  * Copyright (c) 2001, the Rector and Board of Visitors of the
@@ -37,29 +37,29 @@
  * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
  * THE POSSIBILITY OF SUCH DAMAGE.
  */
-/*                                                                     
- * JoBS - altq prototype implementation                                
- *                                                                     
+/*
+ * JoBS - altq prototype implementation
+ *
  * Author: Nicolas Christin <nicolas@cs.virginia.edu>
  *
- * JoBS algorithms originally devised and proposed by		       
+ * JoBS algorithms originally devised and proposed by
  * Nicolas Christin and Jorg Liebeherr.
- * Grateful acknowledgments to Tarek Abdelzaher for his help and       
+ * Grateful acknowledgments to Tarek Abdelzaher for his help and
  * comments, and to Kenjiro Cho for some helpful advice.
  * Contributed by the Multimedia Networks Group at the University
- * of Virginia. 
+ * of Virginia.
  *
- * Papers and additional info can be found at 
+ * Papers and additional info can be found at
  * http://qosbox.cs.virginia.edu
- *                                                                      
- */ 							               
+ *
+ */
 
 /*
  * JoBS queue
  */
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: altq_jobs.c,v 1.7.2.2 2016/04/22 15:44:08 skrll Exp $");
+__KERNEL_RCSID(0, "$NetBSD: altq_jobs.c,v 1.7.2.3 2016/12/05 10:54:48 skrll Exp $");
 
 #ifdef _KERNEL_OPT
 #include "opt_altq.h"
@@ -315,25 +315,25 @@
 	if (adc == -1) {
 		cl->concerned_adc = 0;
 		adc = ALTQ_INFINITY;
-	} else 
+	} else
 		cl->concerned_adc = 1;
 
 	if (alc == -1) {
 		cl->concerned_alc = 0;
 		alc = ALTQ_INFINITY;
-	} else 
+	} else
 		cl->concerned_alc = 1;
 
 	if (rdc == -1) {
 		rdc = 0;
 		cl->concerned_rdc = 0;
-	} else 
+	} else
 		cl->concerned_rdc = 1;
 
 	if (rlc == -1) {
 		rlc = 0;
 		cl->concerned_rlc = 0;
-	} else 
+	} else
 		cl->concerned_rlc = 1;
 
 	if (arc == -1) {
@@ -522,7 +522,7 @@
 				PKTCNTR_RESET(&scan->cl_rout);
 				PKTCNTR_RESET(&scan->cl_rout_th);
 				PKTCNTR_RESET(&scan->cl_arrival);
-				PKTCNTR_RESET(&scan->cl_dropcnt);	
+				PKTCNTR_RESET(&scan->cl_dropcnt);
 				scan->cl_lastdel = 0;
 				scan->current_loss = 0;
 				scan->service_rate = 0;
@@ -556,7 +556,7 @@
 				PKTCNTR_RESET(&scan->cl_rout);
 				PKTCNTR_RESET(&scan->cl_rout_th);
 				PKTCNTR_RESET(&scan->cl_arrival);
-				PKTCNTR_RESET(&scan->cl_dropcnt);	
+				PKTCNTR_RESET(&scan->cl_dropcnt);
 				scan->current_loss = 0;
 				scan->service_rate = 0;
 				scan->idletime = now;
@@ -978,7 +978,7 @@
 	TSENTRY *pushed;
 	pushed = malloc(sizeof(TSENTRY), M_DEVBUF, M_WAITOK);
 	if (pushed == NULL)
-		return (0);	
+		return (0);
 
 	pushed->timestamp = arv;
 	TAILQ_INSERT_TAIL(cl->arv_tm, pushed, ts_list);
@@ -1161,7 +1161,7 @@
 
 	prop_control = (upper_bound*upper_bound*min_share)
 	    /(max_prod*(max_avg_pkt_size << 2));
-  
+
 	prop_control = bps_to_internal(ticks_to_secs(prop_control)); /* in BT-1 */
 
 	credit = 0;
@@ -1237,7 +1237,7 @@
 		cl = jif->jif_classes[i];
 		class_exists = (cl != NULL);
 		is_backlogged = (class_exists && !qempty(cl->cl_q));
- 
+
 		if (is_backlogged && cl->concerned_rdc) {
 			available = result[i]
 			    + cl->service_rate-cl->min_rate_adc;
@@ -1547,7 +1547,7 @@
 update_error(struct jobs_if *jif)
 {
 	int i;
-	int active_classes, backlogged_classes;
+	int active_classes;
 	u_int64_t mean_weighted_delay;
 	u_int64_t delays[JOBS_MAXPRI];
 	int64_t* error;
@@ -1562,7 +1562,6 @@
 
 	mean_weighted_delay = 0;
 	active_classes = 0;
-	backlogged_classes = 0;
 
 	for (i = 0; i <= jif->jif_maxpri; i++) {
 		cl = jif->jif_classes[i];
@@ -1570,7 +1569,6 @@
 		is_backlogged = (class_exists && !qempty(cl->cl_q));
 
 		if (is_backlogged) {
-			backlogged_classes++;
 			if (cl->concerned_rdc) {
 				delays[i] = proj_delay(jif, i);
 				mean_weighted_delay += cl->delay_prod_others*delays[i];
@@ -1623,7 +1621,7 @@
 		cl = jif->jif_classes[i];
 		class_exists = (cl != NULL);
 		is_backlogged = (class_exists && !qempty(cl->cl_q));
-		if (is_backlogged && cl->concerned_adc) { 
+		if (is_backlogged && cl->concerned_adc) {
 			remaining_time = cl->cl_adc - proj_delay(jif, i);
 			if (remaining_time > 0 ) {
 				/* min rate needed for ADC */
@@ -1685,7 +1683,7 @@
 {
 	int64_t mean;
 	int64_t* loss_error;
-	int i, active_classes, backlogged_classes;
+	int i, active_classes;
 	int class_exists, is_backlogged;
 	int class_dropped;
 	int64_t max_error;
@@ -1704,14 +1702,12 @@
 	max_error = 0;
 	mean = 0;
 	active_classes = 0;
-	backlogged_classes = 0;
 
 	for (i = 0; i <= jif->jif_maxpri; i++) {
 		cl = jif->jif_classes[i];
 		class_exists = (cl != NULL);
 		is_backlogged = (class_exists && !qempty(cl->cl_q));
 		if (is_backlogged) {
-			backlogged_classes ++;
 			if (cl->concerned_rlc) {
 				mean += cl->loss_prod_others
 				    * cl->current_loss;
--- a/sys/arch/alpha/alpha/machdep.c	Sun Nov 06 11:50:54 2016 +0000
+++ b/sys/arch/alpha/alpha/machdep.c	Mon Dec 05 10:54:48 2016 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: machdep.c,v 1.346 2014/10/17 18:14:42 uebayasi Exp $ */
+/* $NetBSD: machdep.c,v 1.346.2.1 2016/12/05 10:54:48 skrll Exp $ */
 
 /*-
  * Copyright (c) 1998, 1999, 2000 The NetBSD Foundation, Inc.
@@ -68,7 +68,7 @@
 
 #include <sys/cdefs.h>			/* RCS ID & Copyright macro defns */
 
-__KERNEL_RCSID(0, "$NetBSD: machdep.c,v 1.346 2014/10/17 18:14:42 uebayasi Exp $");
+__KERNEL_RCSID(0, "$NetBSD: machdep.c,v 1.346.2.1 2016/12/05 10:54:48 skrll Exp $");
 
 #include <sys/param.h>
 #include <sys/systm.h>
@@ -173,7 +173,7 @@
 
 /* For built-in TCDS */
 #if defined(DEC_3000_300) || defined(DEC_3000_500)
-uint8_t	dec_3000_scsiid[2], dec_3000_scsifast[2];
+uint8_t	dec_3000_scsiid[3], dec_3000_scsifast[3];
 #endif
 
 struct platform platform;
--- a/sys/arch/alpha/alpha/prom.c	Sun Nov 06 11:50:54 2016 +0000
+++ b/sys/arch/alpha/alpha/prom.c	Mon Dec 05 10:54:48 2016 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: prom.c,v 1.48 2012/02/06 02:14:12 matt Exp $ */
+/* $NetBSD: prom.c,v 1.48.24.1 2016/12/05 10:54:48 skrll Exp $ */
 
 /*
  * Copyright (c) 1992, 1994, 1995, 1996 Carnegie Mellon University
@@ -27,7 +27,7 @@
 
 #include <sys/cdefs.h>			/* RCS ID & Copyright macro defns */
 
-__KERNEL_RCSID(0, "$NetBSD: prom.c,v 1.48 2012/02/06 02:14:12 matt Exp $");
+__KERNEL_RCSID(0, "$NetBSD: prom.c,v 1.48.24.1 2016/12/05 10:54:48 skrll Exp $");
 
 #include "opt_multiprocessor.h"
 
@@ -95,7 +95,7 @@
 
 	init_prom_interface(hwrpb);
 
-	prom_getenv(PROM_E_TTY_DEV, buf, 4);
+	prom_getenv(PROM_E_TTY_DEV, buf, sizeof(buf));
 	alpha_console = buf[0] - '0';
 
 	/* XXX fake out the console routines, for now */
@@ -238,14 +238,14 @@
 
 	prom_enter();
 	ret.bits = prom_getenv_disp(id, to, len);
+	if (ret.u.status & 0x4)
+		ret.u.retval = 0;
+	len = min(len - 1, ret.u.retval);
 	memcpy(buf, to, len);
+	buf[len] = '\0';
 	prom_leave();
 
-	if (ret.u.status & 0x4)
-		ret.u.retval = 0;
-	buf[ret.u.retval] = '\0';
-
-	return (ret.bits);
+	return len;
 }
 
 void
--- a/sys/arch/alpha/conf/GENERIC	Sun Nov 06 11:50:54 2016 +0000
+++ b/sys/arch/alpha/conf/GENERIC	Mon Dec 05 10:54:48 2016 +0000
@@ -1,4 +1,4 @@
-# $NetBSD: GENERIC,v 1.362.2.5 2016/04/22 15:44:08 skrll Exp $
+# $NetBSD: GENERIC,v 1.362.2.6 2016/12/05 10:54:48 skrll Exp $
 #
 # This machine description file is used to generate the default NetBSD
 # kernel.
@@ -19,7 +19,7 @@
 
 options 	INCLUDE_CONFIG_FILE	# embed config file in kernel binary
 
-ident		"GENERIC-$Revision: 1.362.2.5 $"
+ident		"GENERIC-$Revision: 1.362.2.6 $"
 
 maxusers 32
 
@@ -262,6 +262,8 @@
 #sfbp*	at	tc? slot ? offset ?
 px*	at	tc? slot ? offset ?
 pxg*	at	tc? slot ? offset ?
+tcu*	at	tc? slot ? offset ?
+slhci*	at	tcu?
 
 # TURBOchannel serial attachments
 zstty0	at	zsc0 channel ?			# serial port on B channels
@@ -361,6 +363,7 @@
 pcn*	at	pci? dev ? function ?		# AMD PCnet-PCI Ethernet
 pcscp*	at	pci? dev ? function ?		# AMD Am53c974 PCscsi-PCI
 pm2fb*	at	pci? dev ? function ?		# 3Dlabs Permedia 2 Graphics
+pm3fb*	at	pci? dev ? function ?		# 3Dlabs Permedia 3 Graphics
 ppb*	at	pci? dev ? function ?		# PCI-PCI Bridges
 puc*	at 	pci? dev ? function ?		# PCI "universal" comm. cards
 radeonfb* at	pci? dev ? function ?		# ATI/AMD Radeon Graphics
@@ -400,6 +403,9 @@
 # XXX dpti.c wants a processor type that is not assigned for x86-64
 #dpti*	at iop? tid 0			# DPT/Adaptec control interface
 
+# GPIO devices
+gpio*	at gpiobus?
+
 # MII/PHY support
 brgphy* at mii? phy ?			# Broadcom BCM5400-family PHYs
 exphy*	at mii? phy ?			# 3Com internal PHYs
@@ -772,6 +778,7 @@
 pseudo-device	putter			# for puffs and pud
 
 #options	FILEASSOC		# fileassoc(9) - required for Veriexec
+					# and PAX_SEGVGUARD
 
 # Veriexec
 #
--- a/sys/arch/alpha/include/isa_machdep.h	Sun Nov 06 11:50:54 2016 +0000
+++ b/sys/arch/alpha/include/isa_machdep.h	Mon Dec 05 10:54:48 2016 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: isa_machdep.h,v 1.14 2012/02/06 02:14:13 matt Exp $ */
+/* $NetBSD: isa_machdep.h,v 1.14.24.1 2016/12/05 10:54:48 skrll Exp $ */
 
 /*-
  * Copyright (c) 2000 The NetBSD Foundation, Inc.
@@ -90,6 +90,8 @@
     (*(c)->ic_intr_evcnt)((c)->ic_v, (i))
 #define	isa_intr_establish(c, i, t, l, f, a)				\
     (*(c)->ic_intr_establish)((c)->ic_v, (i), (t), (l), (f), (a))
+#define	isa_intr_establish_xname(c, i, t, l, f, a, x)			\
+    (*(c)->ic_intr_establish)((c)->ic_v, (i), (t), (l), (f), (a))
 #define	isa_intr_disestablish(c, h)					\
     (*(c)->ic_intr_disestablish)((c)->ic_v, (h))
 #define	isa_intr_alloc(c, m, t, i)					\
--- a/sys/arch/alpha/stand/common/booted_dev.c	Sun Nov 06 11:50:54 2016 +0000
+++ b/sys/arch/alpha/stand/common/booted_dev.c	Mon Dec 05 10:54:48 2016 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: booted_dev.c,v 1.3 1999/11/13 21:38:20 thorpej Exp $ */
+/* $NetBSD: booted_dev.c,v 1.3.198.1 2016/12/05 10:54:49 skrll Exp $ */
 
 /*
  * Copyright (c) 1999 Christopher G. Demetriou.  All rights reserved.
@@ -53,9 +53,8 @@
 	 * We don't know what device names look like yet,
 	 * so we can't change them.
 	 */
-	ret.bits = prom_getenv(PROM_E_BOOTED_DEV, booted_dev_name,
+	devlen = prom_getenv(PROM_E_BOOTED_DEV, booted_dev_name,
 	    sizeof(booted_dev_name));
-	devlen = ret.u.retval;
 
 	ret.bits = prom_open(booted_dev_name, devlen);
 
--- a/sys/arch/alpha/stand/common/prom.c	Sun Nov 06 11:50:54 2016 +0000
+++ b/sys/arch/alpha/stand/common/prom.c	Mon Dec 05 10:54:48 2016 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: prom.c,v 1.14 2009/03/18 10:22:22 cegger Exp $ */
+/* $NetBSD: prom.c,v 1.14.40.1 2016/12/05 10:54:49 skrll Exp $ */
 
 /*  
  * Mach Operating System
@@ -57,7 +57,7 @@
 	prom_dispatch_v.routine = c->crb_v_dispatch->entry_va;
 
 	/* Look for console tty. */
-	prom_getenv(PROM_E_TTY_DEV, buf, 4);
+	prom_getenv(PROM_E_TTY_DEV, buf, sizeof(buf));
 	console = buf[0] - '0';
 }
 
--- a/sys/arch/amd64/amd64/cpufunc.S	Sun Nov 06 11:50:54 2016 +0000
+++ b/sys/arch/amd64/amd64/cpufunc.S	Mon Dec 05 10:54:48 2016 +0000
@@ -1,4 +1,4 @@
-/*	$NetBSD: cpufunc.S,v 1.25 2014/02/12 23:24:09 dsl Exp $	*/
+/*	$NetBSD: cpufunc.S,v 1.25.6.1 2016/12/05 10:54:49 skrll Exp $	*/
 
 /*-
  * Copyright (c) 1998, 2007, 2008 The NetBSD Foundation, Inc.
@@ -158,12 +158,52 @@
 	movq	%rax, %cr3
 	ret
 
+ENTRY(ldr0)
+	movq	%rdi, %dr0
+	ret
+
+ENTRY(rdr0)
+	movq	%dr0, %rax
+	ret
+
+ENTRY(ldr1)
+	movq	%rdi, %dr1
+	ret
+
+ENTRY(rdr1)
+	movq	%dr1, %rax
+	ret
+
+ENTRY(ldr2)
+	movq	%rdi, %dr2
+	ret
+
+ENTRY(rdr2)
+	movq	%dr2, %rax
+	ret
+
+ENTRY(ldr3)
+	movq	%rdi, %dr3
+	ret
+
+ENTRY(rdr3)
+	movq	%dr3, %rax
+	ret
+
 ENTRY(ldr6)
 	movq	%rdi, %dr6
 	ret
 
 ENTRY(rdr6)
-	movq	%dr6, %rdi
+	movq	%dr6, %rax
+	ret
+
+ENTRY(ldr7)
+	movq	%rdi, %dr7
+	ret
+
+ENTRY(rdr7)
+	movq	%dr7, %rax
 	ret
 
 ENTRY(x86_disable_intr)
--- a/sys/arch/amd64/amd64/locore.S	Sun Nov 06 11:50:54 2016 +0000
+++ b/sys/arch/amd64/amd64/locore.S	Mon Dec 05 10:54:48 2016 +0000
@@ -1,4 +1,4 @@
-/*	$NetBSD: locore.S,v 1.77.2.5 2016/10/05 20:55:23 skrll Exp $	*/
+/*	$NetBSD: locore.S,v 1.77.2.6 2016/12/05 10:54:49 skrll Exp $	*/
 
 /*
  * Copyright-o-rama!
@@ -313,21 +313,6 @@
  */
 	.data
 
-#if NLAPIC > 0
-	.align	PAGE_SIZE
-	.globl	_C_LABEL(local_apic)
-	.globl	_C_LABEL(lapic_tpr)
-
-	.type	_C_LABEL(local_apic), @object
-LABEL(local_apic)
-	.space	LAPIC_TPRI
-END(local_apic)
-	.type	_C_LABEL(lapic_tpr), @object
-LABEL(lapic_tpr)
-	.space	PAGE_SIZE-LAPIC_TPRI
-END(lapic_tpr)
-#endif /* NLAPIC > 0 */
-
 	.globl	_C_LABEL(tablesize)
 	.globl	_C_LABEL(nox_flag)
 	.globl	_C_LABEL(cputype)
@@ -892,10 +877,9 @@
 	/*
 	 * Xen info:
 	 * - %rsi -> start_info struct
-	 * - %rsp -> stack, *theoretically* the last used page
-	 *	by Xen bootstrap
+	 * - %rsp -> stack, *theoretically* the last used page by Xen bootstrap
 	 */
-	movq	%rsi, %rbx
+	movq	%rsi,%rbx
 
 	/* Clear BSS. */
 	xorq	%rax,%rax
@@ -905,7 +889,7 @@
 	rep
 	stosb
 
-	/* Copy start_info to a safe place */
+	/* Copy start_info to a safe place. */
 	movq	%rbx,%rsi
 	movq	$_C_LABEL(start_info_union),%rdi
 	movq	$64,%rcx
@@ -929,45 +913,40 @@
 	 */
 
 	/*
-	 * We want our own page tables, let's rebuild them
-	 * We will reclaim xen space afterward INCLUDING stack
-	 * so let's change it to a temporary one
+	 * We want our own page tables, and will rebuild them. We will reclaim
+	 * the Xen space later, INCLUDING the stack. So we need to switch to a
+	 * temporary one now.
 	 */
-
-	movq	$tmpstk, %rax
-	subq	$8, %rax
-	movq	%rax, %rsp
+	movq	$tmpstk,%rax
+	subq	$8,%rax
+	movq	%rax,%rsp
 
 	xorl	%eax,%eax
 	cpuid
 	movl	%eax,_C_LABEL(cpuid_level)
 
-	movq	$cpu_info_primary, %rdi
-	movq	%rdi, CPU_INFO_SELF(%rdi) /* ci->ci_self = ci */
-	movq	$1, %rsi
+	movq	$cpu_info_primary,%rdi
+	movq	%rdi,CPU_INFO_SELF(%rdi) /* ci->ci_self = ci */
+	movq	$1,%rsi
 	call	cpu_init_msrs	/* cpu_init_msrs(ci, true); */
 
-	call	xen_pmap_bootstrap
+	call	xen_locore
 
 	/*
-	 * First avail returned by xen_pmap_bootstrap in %rax
+	 * The first VA available is returned by xen_locore in %rax. We
+	 * use it as the UAREA, and set up the stack here.
 	 */
-	movq	%rax, %rsi
+	movq	%rax,%rsi
 	movq	%rsi,(_C_LABEL(lwp0)+L_PCB)	/* XXX L_PCB != uarea */
-
-	/*
-	 * Set new stack and clear segments
-	 */
 	leaq	(USPACE-FRAMESIZE)(%rsi),%rsp
 	xorq	%rbp,%rbp
 
+	/* Clear segment registers. */
 	xorw	%ax,%ax
 	movw	%ax,%gs
 	movw	%ax,%fs
 
-	/*
-	 * Set first_avail after proc0
-	 */
+	/* Set first_avail after the UAREA. */
 	movq	%rsi,%rdi
 	addq	$USPACE,%rdi
 	subq	$KERNBASE,%rdi	/* init_x86_64 wants a physical address */
--- a/sys/arch/amd64/amd64/machdep.c	Sun Nov 06 11:50:54 2016 +0000
+++ b/sys/arch/amd64/amd64/machdep.c	Mon Dec 05 10:54:48 2016 +0000
@@ -1,4 +1,4 @@
-/*	$NetBSD: machdep.c,v 1.211.4.7 2016/10/05 20:55:23 skrll Exp $	*/
+/*	$NetBSD: machdep.c,v 1.211.4.8 2016/12/05 10:54:49 skrll Exp $	*/
 
 /*-
  * Copyright (c) 1996, 1997, 1998, 2000, 2006, 2007, 2008, 2011
@@ -111,7 +111,7 @@
  */
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: machdep.c,v 1.211.4.7 2016/10/05 20:55:23 skrll Exp $");
+__KERNEL_RCSID(0, "$NetBSD: machdep.c,v 1.211.4.8 2016/12/05 10:54:49 skrll Exp $");
 
 /* #define XENDEBUG_LOW  */
 
@@ -377,12 +377,14 @@
 	/*
 	 * Create the module map.
 	 *
-	 * XXX: the module map is taken as what is left of the bootstrap memory
-	 * created in locore.S, which is not big enough if we want to load many
-	 * modules dynamically. We really should be using kernel_map instead.
+	 * The kernel uses RIP-relative addressing with a maximum offset of
+	 * 2GB. The problem is, kernel_map is too far away in memory from
+	 * the kernel .text. So we cannot use it, and have to create a
+	 * special module_map.
 	 *
-	 * But the modules must be located above the kernel image, and that
-	 * wouldn't be guaranteed if we were using kernel_map.
+	 * The module map is taken as what is left of the bootstrap memory
+	 * created in locore.S. This memory is right above the kernel
+	 * image, so this is the best place to put our modules.
 	 */
 	uvm_map_setup(&module_map_store, module_start, module_end, 0);
 	module_map_store.pmap = pmap_kernel();
@@ -1540,7 +1542,9 @@
 	int x;
 #ifndef XEN
 	int ist;
-#endif /* !XEN */
+#endif
+
+	KASSERT(first_avail % PAGE_SIZE == 0);
 
 #ifdef XEN
 	KASSERT(HYPERVISOR_shared_info != NULL);
@@ -1603,6 +1607,15 @@
 	    pmap_pa_start, avail_start, avail_end));
 #endif	/* !XEN */
 
+	/* End of the virtual space we have created so far. */
+	kern_end = KERNBASE + first_avail;
+
+#ifndef XEN
+	/* The area for the module map. */
+	module_start = kern_end;
+	module_end = KERNBASE + NKL2_KIMG_ENTRIES * NBPD_L2;
+#endif
+
 	/*
 	 * Call pmap initialization to make new kernel address space.
 	 * We must do this before loading pages into the VM system.
@@ -1613,7 +1626,6 @@
 	/* Internalize the physical pages into the VM system. */
 	init_x86_vm(first_avail);
 #else	/* XEN */
-	kern_end = KERNBASE + first_avail;
 	physmem = xen_start_info.nr_pages;
 
 	uvm_page_physload(atop(avail_start),
--- a/sys/arch/amd64/amd64/netbsd32_machdep.c	Sun Nov 06 11:50:54 2016 +0000
+++ b/sys/arch/amd64/amd64/netbsd32_machdep.c	Mon Dec 05 10:54:48 2016 +0000
@@ -1,4 +1,4 @@
-/*	$NetBSD: netbsd32_machdep.c,v 1.92.6.3 2016/10/05 20:55:23 skrll Exp $	*/
+/*	$NetBSD: netbsd32_machdep.c,v 1.92.6.4 2016/12/05 10:54:49 skrll Exp $	*/
 
 /*
  * Copyright (c) 2001 Wasabi Systems, Inc.
@@ -36,7 +36,7 @@
  */
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: netbsd32_machdep.c,v 1.92.6.3 2016/10/05 20:55:23 skrll Exp $");
+__KERNEL_RCSID(0, "$NetBSD: netbsd32_machdep.c,v 1.92.6.4 2016/12/05 10:54:49 skrll Exp $");
 
 #ifdef _KERNEL_OPT
 #include "opt_compat_netbsd.h"
@@ -487,12 +487,12 @@
 {
 	struct trapframe *tf = l->l_md.md_regs;
 
-	regs->r_gs = LSEL(LUCODE32_SEL, SEL_UPL);
-	regs->r_fs = LSEL(LUCODE32_SEL, SEL_UPL);
-	regs->r_es = LSEL(LUCODE32_SEL, SEL_UPL);
-	regs->r_ds = LSEL(LUCODE32_SEL, SEL_UPL);
+	/* XXX avoid sign extension problems with unknown upper bits? */
+	regs->r_gs = tf->tf_gs & 0xffff;
+	regs->r_fs = tf->tf_fs & 0xffff;
+	regs->r_es = tf->tf_es & 0xffff;
+	regs->r_ds = tf->tf_ds & 0xffff;
 	regs->r_eflags = tf->tf_rflags;
-	/* XXX avoid sign extension problems with unknown upper bits? */
 	regs->r_edi = tf->tf_rdi & 0xffffffff;
 	regs->r_esi = tf->tf_rsi & 0xffffffff;
 	regs->r_ebp = tf->tf_rbp & 0xffffffff;
@@ -501,9 +501,9 @@
 	regs->r_ecx = tf->tf_rcx & 0xffffffff;
 	regs->r_eax = tf->tf_rax & 0xffffffff;
 	regs->r_eip = tf->tf_rip & 0xffffffff;
-	regs->r_cs = tf->tf_cs;
+	regs->r_cs = tf->tf_cs & 0xffff;
 	regs->r_esp = tf->tf_rsp & 0xffffffff;
-	regs->r_ss = tf->tf_ss;
+	regs->r_ss = tf->tf_ss & 0xffff;
 
 	return (0);
 }
@@ -511,22 +511,52 @@
 int
 netbsd32_process_read_fpregs(struct lwp *l, struct fpreg32 *regs, size_t *sz)
 {
-	struct fpreg regs64;
-	int error;
-	size_t fp_size;
+
+	__CTASSERT(sizeof *regs == sizeof (struct save87));
+	process_read_fpregs_s87(l, (struct save87 *)regs);
+	return 0;
+}
+
+int
+netbsd32_process_write_regs(struct lwp *l, const struct reg32 *regs)
+{
+	struct trapframe *tf = l->l_md.md_regs;
 
 	/*
-	 * All that stuff makes no sense in i386 code :(
+	 * Check for security violations. Taken from i386/process_machdep.c.
 	 */
+	if (((regs->r_eflags ^ tf->tf_rflags) & PSL_USERSTATIC) != 0 ||
+	    !VALID_USER_CSEL32(regs->r_cs))
+		return EINVAL;
 
-	fp_size = sizeof regs64;
-	error = process_read_fpregs(l, &regs64, &fp_size);
-	if (error)
-		return error;
+	tf->tf_rax = regs->r_eax;
+	tf->tf_rcx = regs->r_ecx;
+	tf->tf_rdx = regs->r_edx;
+	tf->tf_rbx = regs->r_ebx;
+	tf->tf_rsp = regs->r_esp;
+	tf->tf_rbp = regs->r_ebp;
+	tf->tf_rsi = regs->r_esi;
+	tf->tf_rdi = regs->r_edi;
+	tf->tf_rip = regs->r_eip;
+	tf->tf_rflags = regs->r_eflags;
+	tf->tf_cs = regs->r_cs;
+	tf->tf_ss = regs->r_ss;
+	tf->tf_ds = regs->r_ds;
+	tf->tf_es = regs->r_es;
+	tf->tf_fs = regs->r_fs;
+	tf->tf_gs = regs->r_gs;
+
+	return 0;
+}
+
+int
+netbsd32_process_write_fpregs(struct lwp *l, const struct fpreg32 *regs,
+    size_t sz)
+{
+
 	__CTASSERT(sizeof *regs == sizeof (struct save87));
-	process_xmm_to_s87(&regs64.fxstate, (struct save87 *)regs);
-
-	return (0);
+	process_write_fpregs_s87(l, (const struct save87 *)regs);
+	return 0;
 }
 
 int
--- a/sys/arch/amd64/amd64/trap.c	Sun Nov 06 11:50:54 2016 +0000
+++ b/sys/arch/amd64/amd64/trap.c	Mon Dec 05 10:54:48 2016 +0000
@@ -1,4 +1,4 @@
-/*	$NetBSD: trap.c,v 1.79.2.3 2016/10/05 20:55:23 skrll Exp $	*/
+/*	$NetBSD: trap.c,v 1.79.2.4 2016/12/05 10:54:49 skrll Exp $	*/
 
 /*-
  * Copyright (c) 1998, 2000 The NetBSD Foundation, Inc.
@@ -68,7 +68,7 @@
  */
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: trap.c,v 1.79.2.3 2016/10/05 20:55:23 skrll Exp $");
+__KERNEL_RCSID(0, "$NetBSD: trap.c,v 1.79.2.4 2016/12/05 10:54:49 skrll Exp $");
 
 #include "opt_ddb.h"
 #include "opt_kgdb.h"
@@ -662,9 +662,10 @@
 		}
 
 #ifdef TRAP_SIGDEBUG
-		printf("pid %d.%d (%s): signal %d at rip %lx addr %lx "
-		    "error %d\n", p->p_pid, l->l_lid, p->p_comm, ksi.ksi_signo,
-		    frame->tf_rip, va, error);
+		printf("pid %d.%d (%s): signal %d at rip %#lx addr %#lx "
+		    "error %d trap %d cr2 %p\n", p->p_pid, l->l_lid, p->p_comm,
+		    ksi.ksi_signo, frame->tf_rip, va, error, ksi.ksi_trap,
+		    ksi.ksi_addr);
 		frame_dump(frame);
 #endif
 		(*p->p_emul->e_trapsignal)(l, &ksi);
--- a/sys/arch/amd64/amd64/vector.S	Sun Nov 06 11:50:54 2016 +0000
+++ b/sys/arch/amd64/amd64/vector.S	Mon Dec 05 10:54:48 2016 +0000
@@ -1,4 +1,4 @@
-/*	$NetBSD: vector.S,v 1.44.10.2 2016/10/05 20:55:23 skrll Exp $	*/
+/*	$NetBSD: vector.S,v 1.44.10.3 2016/12/05 10:54:49 skrll Exp $	*/
 
 /*-
  * Copyright (c) 1998, 2007, 2008 The NetBSD Foundation, Inc.
@@ -123,7 +123,8 @@
 	pushq	$0
 	pushq	$T_ASTFLT
 	INTRENTRY
-	movl	$0,_C_LABEL(local_apic)+LAPIC_EOI
+	movq	_C_LABEL(local_apic_va),%rbx
+	movl	$0,LAPIC_EOI(%rbx)
 	movl	CPUVAR(ILEVEL),%ebx
 	cmpl	$IPL_HIGH,%ebx
 	jae	2f
@@ -149,7 +150,8 @@
 	INTRENTRY
 	movl	$0xf,%eax
 	movq	%rax,%cr8
-	movl	$0,_C_LABEL(local_apic)+LAPIC_EOI
+	movq	_C_LABEL(local_apic_va),%rbx
+	movl	$0,LAPIC_EOI(%rbx)
 	sti
 	call	_C_LABEL(ddb_ipi)
 	xorl	%eax,%eax
@@ -174,7 +176,8 @@
 	pushq	$0
 	pushq	$T_ASTFLT
 	INTRENTRY
-	movl	$0,_C_LABEL(local_apic)+LAPIC_EOI
+	movq	_C_LABEL(local_apic_va),%rbx
+	movl	$0,LAPIC_EOI(%rbx)
 	movl	CPUVAR(ILEVEL),%ebx
 	cmpl	$IPL_CLOCK,%ebx
 	jae	2f
@@ -203,7 +206,8 @@
 	pushq	$0
 	pushq	$T_ASTFLT
 	INTRENTRY
-	movl	$0,_C_LABEL(local_apic)+LAPIC_EOI
+	movq	_C_LABEL(local_apic_va),%rax
+	movl	$0,LAPIC_EOI(%rax)
 	callq	_C_LABEL(pmap_tlb_intr)
 	INTRFASTEXIT
 IDTVEC_END(intr_lapic_tlb)
--- a/sys/arch/amd64/conf/ALL	Sun Nov 06 11:50:54 2016 +0000
+++ b/sys/arch/amd64/conf/ALL	Mon Dec 05 10:54:48 2016 +0000
@@ -1,4 +1,4 @@
-# $NetBSD: ALL,v 1.23.2.6 2016/10/05 20:55:23 skrll Exp $
+# $NetBSD: ALL,v 1.23.2.7 2016/12/05 10:54:49 skrll Exp $
 # From NetBSD: GENERIC,v 1.787 2006/10/01 18:37:54 bouyer Exp
 #
 # ALL machine description file
@@ -17,7 +17,7 @@
 
 options 	INCLUDE_CONFIG_FILE	# embed config file in kernel binary
 
-#ident 		"ALL-$Revision: 1.23.2.6 $"
+#ident 		"ALL-$Revision: 1.23.2.7 $"
 
 maxusers	64		# estimated number of users
 
@@ -1634,6 +1634,7 @@
 pseudo-device	nandemulator
 
 options 	FILEASSOC		# fileassoc(9) - required for Veriexec
+					# and PAX_SEGVGUARD
 
 # Veriexec
 pseudo-device	veriexec
@@ -1983,6 +1984,7 @@
 options IEDEBUG
 options IEEE80211_DEBUG_REFCNT
 options IFAREF_DEBUG
+options IFA_STATS
 options IFMEDIA_DEBUG
 options IHA_DEBUG_STATE
 options INTRDEBUG
--- a/sys/arch/amd64/conf/GENERIC	Sun Nov 06 11:50:54 2016 +0000
+++ b/sys/arch/amd64/conf/GENERIC	Mon Dec 05 10:54:48 2016 +0000
@@ -1,4 +1,4 @@
-# $NetBSD: GENERIC,v 1.404.2.10 2016/10/05 20:55:23 skrll Exp $
+# $NetBSD: GENERIC,v 1.404.2.11 2016/12/05 10:54:49 skrll Exp $
 #
 # GENERIC machine description file
 #
@@ -22,7 +22,7 @@
 
 options 	INCLUDE_CONFIG_FILE	# embed config file in kernel binary
 
-#ident 		"GENERIC-$Revision: 1.404.2.10 $"
+#ident 		"GENERIC-$Revision: 1.404.2.11 $"
 
 maxusers	64		# estimated number of users
 
@@ -110,6 +110,15 @@
 options 	KDTRACE_HOOKS	# kernel DTrace hooks
 
 # Compatibility options
+# (note that really old compat (< 1.6) is only useful for 32-bit binaries)
+#options	EXEC_AOUT	# required by binaries from before 1.5
+#options 	COMPAT_NOMID	# NetBSD 0.8, 386BSD, and BSDI
+#options 	COMPAT_09	# NetBSD 0.9,
+#options 	COMPAT_10	# NetBSD 1.0,
+#options 	COMPAT_11	# NetBSD 1.1,
+#options 	COMPAT_12	# NetBSD 1.2 (and 386BSD and BSDI),
+#options 	COMPAT_13	# NetBSD 1.3 (and 386BSD and BSDI),
+#options 	COMPAT_14	# NetBSD 1.4,
 options 	COMPAT_15	# NetBSD 1.5,
 options 	COMPAT_16	# NetBSD 1.6,
 options 	COMPAT_20	# NetBSD 2.0,
@@ -128,16 +137,6 @@
 options 	EXEC_ELF32
 options 	COMPAT_BSDPTY	# /dev/[pt]ty?? ptys.
 
-# The following options are for running i386 binaries for pre-1.6
-#options	EXEC_AOUT
-#options 	COMPAT_NOMID	# NetBSD 0.8, 386BSD, and BSDI
-#options 	COMPAT_09	# NetBSD 0.9,
-#options 	COMPAT_10	# NetBSD 1.0,
-#options 	COMPAT_11	# NetBSD 1.1,
-#options 	COMPAT_12	# NetBSD 1.2 (and 386BSD and BSDI),
-#options 	COMPAT_13	# NetBSD 1.3 (and 386BSD and BSDI),
-#options 	COMPAT_14	# NetBSD 1.4,
-
 # Wedge support
 options 	DKWEDGE_AUTODISCOVER	# Automatically add dk(4) instances
 options 	DKWEDGE_METHOD_GPT	# Supports GPT partitions as wedges
@@ -752,8 +751,8 @@
 gsip*	at pci? dev ? function ?	# NS83820 Gigabit Ethernet
 ipw*	at pci? dev ? function ?	# Intel PRO/Wireless 2100
 iwi*	at pci? dev ? function ?	# Intel PRO/Wireless 2200BG
+iwm*	at pci? dev ? function ?	# Intel Centrino 7260
 iwn*	at pci? dev ? function ?	# Intel PRO/Wireless 4965AGN
-iwm*	at pci? dev ? function ?	# Intel Centrino 7260
 ixg*	at pci? dev ? function ?	# Intel 8259x 10 gigabit
 ixv*	at pci? dev ? function ?	# Intel 8259x 10G virtual function
 jme*	at pci? dev ? function ?	# JMicron JMC2[56]0 ethernet
@@ -1308,7 +1307,8 @@
 # userland interface to drivers, including autoconf and properties retrieval
 pseudo-device	drvctl
 
-options 	FILEASSOC		# fileassoc(9) - required for Veriexec
+options 	FILEASSOC		# fileassoc(9) - needed by Veriexec
+					# and PAX_SEGVGUARD
 
 # Veriexec
 #
--- a/sys/arch/amd64/include/i82093reg.h	Sun Nov 06 11:50:54 2016 +0000
+++ b/sys/arch/amd64/include/i82093reg.h	Mon Dec 05 10:54:48 2016 +0000
@@ -1,4 +1,4 @@
-/*	 $NetBSD: i82093reg.h,v 1.5.60.1 2016/10/05 20:55:23 skrll Exp $ */
+/*	 $NetBSD: i82093reg.h,v 1.5.60.2 2016/12/05 10:54:49 skrll Exp $ */
 
 #include <x86/i82093reg.h>
 
@@ -9,7 +9,8 @@
 #endif
 
 #define ioapic_asm_ack(num) \
-	movl	$0,_C_LABEL(local_apic)+LAPIC_EOI
+	movq	_C_LABEL(local_apic_va),%rax	; \
+	movl	$0,LAPIC_EOI(%rax)
 
 #ifdef MULTIPROCESSOR
 
--- a/sys/arch/amd64/include/netbsd32_machdep.h	Sun Nov 06 11:50:54 2016 +0000
+++ b/sys/arch/amd64/include/netbsd32_machdep.h	Mon Dec 05 10:54:48 2016 +0000
@@ -1,4 +1,4 @@
-/*	$NetBSD: netbsd32_machdep.h,v 1.19 2014/02/07 22:40:22 dsl Exp $	*/
+/*	$NetBSD: netbsd32_machdep.h,v 1.19.6.1 2016/12/05 10:54:49 skrll Exp $	*/
 
 #ifndef _MACHINE_NETBSD32_H_
 #define _MACHINE_NETBSD32_H_
@@ -138,4 +138,7 @@
 int netbsd32_process_read_regs(struct lwp *, struct reg32 *);
 int netbsd32_process_read_fpregs(struct lwp *, struct fpreg32 *, size_t *);
 
+int netbsd32_process_write_regs(struct lwp *, const struct reg32 *);
+int netbsd32_process_write_fpregs(struct lwp *, const struct fpreg32 *, size_t);
+
 #endif /* _MACHINE_NETBSD32_H_ */
--- a/sys/arch/amd64/include/pmap.h	Sun Nov 06 11:50:54 2016 +0000
+++ b/sys/arch/amd64/include/pmap.h	Mon Dec 05 10:54:48 2016 +0000
@@ -1,4 +1,4 @@
-/*	$NetBSD: pmap.h,v 1.34.16.3 2016/10/05 20:55:23 skrll Exp $	*/
+/*	$NetBSD: pmap.h,v 1.34.16.4 2016/12/05 10:54:49 skrll Exp $	*/
 
 /*
  * Copyright (c) 1997 Charles D. Cranor and Washington University.
@@ -128,17 +128,6 @@
  */
 
 /*
- * The first generation of Hammer processors can use 48 bits of
- * virtual memory, and 40 bits of physical memory. This will be
- * more for later generations. These defines can be changed to
- * variable names containing the # of bits, extracted from an
- * extended cpuid instruction (variables are harder to use during
- * bootstrap, though)
- */
-#define VIRT_BITS	48
-#define PHYS_BITS	40
-
-/*
  * Mask to get rid of the sign-extended part of addresses.
  */
 #define VA_SIGN_MASK		0xffff000000000000
@@ -150,10 +139,10 @@
 
 #define L4_SLOT_PTE		255
 #ifndef XEN
-#define L4_SLOT_KERN		256
+#define L4_SLOT_KERN		256 /* pl4_i(VM_MIN_KERNEL_ADDRESS) */
 #else
 /* Xen use slots 256-272, let's move farther */
-#define L4_SLOT_KERN		320
+#define L4_SLOT_KERN		320 /* pl4_i(VM_MIN_KERNEL_ADDRESS) */
 #endif
 #define L4_SLOT_KERNBASE	511 /* pl4_i(KERNBASE) */
 
--- a/sys/arch/amd64/include/ptrace.h	Sun Nov 06 11:50:54 2016 +0000
+++ b/sys/arch/amd64/include/ptrace.h	Mon Dec 05 10:54:48 2016 +0000
@@ -1,4 +1,4 @@
-/*	$NetBSD: ptrace.h,v 1.3.100.2 2015/12/27 12:09:28 skrll Exp $	*/
+/*	$NetBSD: ptrace.h,v 1.3.100.3 2016/12/05 10:54:49 skrll Exp $	*/
 
 /*
  * Copyright (c) 1993 Christopher G. Demetriou
@@ -68,6 +68,9 @@
 #define process_read_regs32	netbsd32_process_read_regs
 #define process_read_fpregs32	netbsd32_process_read_fpregs
 
+#define process_write_regs32	netbsd32_process_write_regs
+#define process_write_fpregs32	netbsd32_process_write_fpregs
+
 #define process_reg32		struct reg32
 #define process_fpreg32		struct fpreg32
 #endif	/* COMPAT_NETBSD32 */
--- a/sys/arch/amd64/include/vmparam.h	Sun Nov 06 11:50:54 2016 +0000
+++ b/sys/arch/amd64/include/vmparam.h	Mon Dec 05 10:54:48 2016 +0000
@@ -1,4 +1,4 @@
-/*	$NetBSD: vmparam.h,v 1.36.4.1 2016/10/05 20:55:23 skrll Exp $	*/
+/*	$NetBSD: vmparam.h,v 1.36.4.2 2016/12/05 10:54:49 skrll Exp $	*/
 
 /*-
  * Copyright (c) 1990 The Regents of the University of California.
@@ -114,7 +114,7 @@
 
 /* user/kernel map constants */
 #define VM_MIN_ADDRESS		0
-#define VM_MAXUSER_ADDRESS	0x00007f8000000000
+#define VM_MAXUSER_ADDRESS	(0x00007f8000000000 - PAGE_SIZE)
 #define VM_MAX_ADDRESS		0x00007fbfdfeff000
 #ifndef XEN
 #define VM_MIN_KERNEL_ADDRESS	0xffff800000000000
--- a/sys/arch/amiga/conf/WSCONS	Sun Nov 06 11:50:54 2016 +0000
+++ b/sys/arch/amiga/conf/WSCONS	Mon Dec 05 10:54:48 2016 +0000
@@ -1,4 +1,4 @@
-# $NetBSD: WSCONS,v 1.67.6.2 2016/10/05 20:55:23 skrll Exp $
+# $NetBSD: WSCONS,v 1.67.6.3 2016/12/05 10:54:49 skrll Exp $
 
 # GENERIC with wscons(4)
 #
@@ -28,12 +28,10 @@
 no grfrt0	at zbus0
 no grfrh0	at zbus0
 no grful0	at zbus0
-no grfet*	at zbus0
 no grf0		at grfcc0
 no grf1		at grfrt0
 no grf2		at grfrh0
 no grf4		at grful0
-no grf6		at grfet?
 
 # Disable ite(4) for all grf(4) drivers.
 no ite0		at grf0
--- a/sys/arch/amiga/dev/grf_et.c	Sun Nov 06 11:50:54 2016 +0000
+++ b/sys/arch/amiga/dev/grf_et.c	Mon Dec 05 10:54:48 2016 +0000
@@ -1,4 +1,4 @@
-/*	$NetBSD: grf_et.c,v 1.32 2014/01/22 00:25:16 christos Exp $ */
+/*	$NetBSD: grf_et.c,v 1.32.6.1 2016/12/05 10:54:49 skrll Exp $ */
 
 /*
  * Copyright (c) 1997 Klaus Burkert
@@ -37,10 +37,11 @@
 #include "opt_amigacons.h"
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: grf_et.c,v 1.32 2014/01/22 00:25:16 christos Exp $");
+__KERNEL_RCSID(0, "$NetBSD: grf_et.c,v 1.32.6.1 2016/12/05 10:54:49 skrll Exp $");
 
 #include "grfet.h"
 #include "ite.h"
+#include "wsdisplay.h"
 #if NGRFET > 0
 
 /*
@@ -72,6 +73,12 @@
 
 #include <machine/cpu.h>
 #include <dev/cons.h>
+#if NWSDISPLAY > 0
+#include <dev/wscons/wsconsio.h>
+#include <dev/wscons/wsdisplayvar.h>
+#include <dev/rasops/rasops.h>
+#include <dev/wscons/wsdisplay_vconsvar.h>
+#endif
 #ifdef TSENGCONSOLE
 #include <amiga/dev/itevar.h>
 #endif
@@ -81,34 +88,50 @@
 #include <amiga/dev/grf_etreg.h>
 #include <amiga/dev/zbusvar.h>
 
-int	et_mondefok(struct grfvideo_mode *gv);
-void	et_boardinit(struct grf_softc *gp);
-static void et_CompFQ(u_int fq, u_char *num, u_char *denom);
-int	et_getvmode(struct grf_softc *gp, struct grfvideo_mode *vm);
-int	et_setvmode(struct grf_softc *gp, unsigned int mode);
-int	et_toggle(struct grf_softc *gp, unsigned short);
-int	et_getcmap(struct grf_softc *gfp, struct grf_colormap *cmap);
-int	et_putcmap(struct grf_softc *gfp, struct grf_colormap *cmap);
+int	et_mondefok(struct grfvideo_mode *);
+void	et_boardinit(struct grf_softc *);
+static void et_CompFQ(u_int fq, u_char *, u_char *);
+int	et_getvmode(struct grf_softc *, struct grfvideo_mode *);
+int	et_setvmode(struct grf_softc *, unsigned int);
+int	et_toggle(struct grf_softc *, unsigned short);
+int	et_getcmap(struct grf_softc *, struct grf_colormap *);
+int	et_putcmap(struct grf_softc *, struct grf_colormap *);
 #ifndef TSENGCONSOLE
-void	et_off(struct grf_softc *gp);
+void	et_off(struct grf_softc *);
 #endif
-void	et_inittextmode(struct grf_softc *gp);
-int	et_ioctl(register struct grf_softc *gp, u_long cmd, void *data);
-int	et_getmousepos(struct grf_softc *gp, struct grf_position *data);
-void	et_writesprpos(volatile char *ba, short x, short y);
-int	et_setmousepos(struct grf_softc *gp, struct grf_position *data);
-static int et_setspriteinfo(struct grf_softc *gp, struct grf_spriteinfo *data);
-int	et_getspriteinfo(struct grf_softc *gp, struct grf_spriteinfo *data);
-static int et_getspritemax(struct grf_softc *gp, struct grf_position *data);
-int	et_setmonitor(struct grf_softc *gp, struct grfvideo_mode *gv);
-int	et_blank(struct grf_softc *gp, int *on);
-static int et_getControllerType(struct grf_softc *gp);
-static int et_getDACType(struct grf_softc *gp);
+void	et_inittextmode(struct grf_softc *);
+int	et_ioctl(register struct grf_softc *, u_long cmd, void *);
+int	et_getmousepos(struct grf_softc *, struct grf_position *);
+void	et_writesprpos(volatile char *ba, short, short);
+int	et_setmousepos(struct grf_softc *, struct grf_position *);
+static int et_setspriteinfo(struct grf_softc *, struct grf_spriteinfo *);
+int	et_getspriteinfo(struct grf_softc *, struct grf_spriteinfo *);
+static int et_getspritemax(struct grf_softc *, struct grf_position *);
+int	et_setmonitor(struct grf_softc *, struct grfvideo_mode *);
+int	et_blank(struct grf_softc *, int);
+int	et_isblank(struct grf_softc *);
+static int et_getControllerType(struct grf_softc *);
+static int et_getDACType(struct grf_softc *);
 
 int	grfetmatch(device_t, cfdata_t, void *);
 void	grfetattach(device_t, device_t, void *);
 int	grfetprint(void *, const char *);
-void	et_memset(volatile unsigned char *d, unsigned char c, int l);
+void	et_memset(volatile unsigned char *, unsigned char, int);
+
+#if NWSDISPLAY > 0
+/* wsdisplay acessops, emulops */
+static int	et_wsioctl(void *, void *, u_long, void *, int, struct lwp *);
+static int	et_get_fbinfo(struct grf_softc *, struct wsdisplayio_fbinfo *);
+
+static void	et_wscursor(void *, int, int, int);
+static void	et_wsputchar(void *, int, int, u_int, long);
+static void	et_wscopycols(void *, int, int, int, int);
+static void	et_wserasecols(void *, int, int, int, long);
+static void	et_wscopyrows(void *, int, int, int);
+static void	et_wseraserows(void *, int, int, long);
+static int	et_wsallocattr(void *, int, int, int, long *);
+static int	et_wsmapchar(void *, int, unsigned int *);
+#endif  /* NWSDISPLAY > 0 */
 
 /*
  * Graphics display definitions.
@@ -179,6 +202,41 @@
 static unsigned char et_imageptr[8 * 64], et_maskptr[8 * 64];
 static unsigned char et_sprred[2], et_sprgreen[2], et_sprblue[2];
 
+#if NWSDISPLAY > 0
+static struct wsdisplay_accessops et_accessops = {
+	.ioctl		= et_wsioctl,
+	.mmap		= grf_wsmmap
+};
+
+static struct wsdisplay_emulops et_textops = {
+	.cursor		= et_wscursor,
+	.mapchar	= et_wsmapchar,
+	.putchar	= et_wsputchar,
+	.copycols	= et_wscopycols,
+	.erasecols	= et_wserasecols,
+	.copyrows	= et_wscopyrows,
+	.eraserows	= et_wseraserows,
+	.allocattr	= et_wsallocattr
+};
+
+static struct wsscreen_descr et_defaultscreen = {
+	.name		= "default",
+	.textops	= &et_textops,
+	.fontwidth	= 8,
+	.fontheight	= TSENGFONTY,
+	.capabilities	= WSSCREEN_HILIT | WSSCREEN_BLINK |
+			  WSSCREEN_REVERSE | WSSCREEN_UNDERLINE
+};
+
+static const struct wsscreen_descr *et_screens[] = {
+	&et_defaultscreen,
+};
+
+static struct wsscreen_list et_screenlist = {
+	sizeof(et_screens) / sizeof(struct wsscreen_descr *), et_screens
+};
+#endif  /* NWSDISPLAY > 0 */
+
 /* standard driver stuff */
 CFATTACH_DECL_NEW(grfet, sizeof(struct grf_softc),
     grfetmatch, grfetattach, NULL, NULL);
@@ -312,9 +370,16 @@
 		et_boardinit(gp);
 
 #ifdef TSENGCONSOLE
+#if NWSDISPLAY > 0
+		gp->g_accessops = &et_accessops;
+		gp->g_emulops = &et_textops;
+		gp->g_defaultscr = &et_defaultscreen;
+		gp->g_scrlist = &et_screenlist;
+#else
 #if NITE > 0
 		grfet_iteinit(gp);
 #endif
+#endif  /* NWSDISPLAY > 0 */
 		(void) et_load_mon(gp, &etconsole_mode);
 #endif
 	}
@@ -621,10 +686,21 @@
 
 
 int
-et_blank(struct grf_softc *gp, int *on)
+et_blank(struct grf_softc *gp, int on)
 {
-	WSeq(gp->g_regkva, SEQ_ID_CLOCKING_MODE, *on > 0 ? 0x01 : 0x21);
-	return(0);
+
+	WSeq(gp->g_regkva, SEQ_ID_CLOCKING_MODE, on > 0 ? 0x01 : 0x21);
+	return 0;
+}
+
+
+int
+et_isblank(struct grf_softc *gp)
+{
+	int r;
+
+	r = RSeq(gp->g_regkva, SEQ_ID_CLOCKING_MODE);
+	return (r & 0x20) != 0;
 }
 
 
@@ -715,7 +791,7 @@
 		return (et_setmonitor(gp, (struct grfvideo_mode *) data));
 
 	    case GRFIOCBLANK:
-		return (et_blank(gp, (int *)data));
+		return (et_blank(gp, *(int *)data));
 	}
 	return (EPASSTHROUGH);
 }
@@ -1598,4 +1674,343 @@
 	return (SIERRA11483);
 }
 
+
+#if NWSDISPLAY > 0
+static void
+et_wscursor(void *c, int on, int row, int col) 
+{
+	struct rasops_info *ri;
+	struct vcons_screen *scr;
+	struct grf_softc *gp;
+	volatile void *ba;
+	int offs;
+
+	ri = c;
+	scr = ri->ri_hw;
+	gp = scr->scr_cookie;
+	ba = gp->g_regkva;
+
+	if ((ri->ri_flg & RI_CURSOR) && !on) {
+		/* cursor was visible, but we want to remove it */
+		/*WCrt(ba, CRT_ID_CURSOR_START, | 0x20);*/
+		ri->ri_flg &= ~RI_CURSOR;
+	}
+
+	ri->ri_crow = row;
+	ri->ri_ccol = col;
+
+	if (on) {
+		/* move cursor to new location */
+		if (!(ri->ri_flg & RI_CURSOR)) {
+			/*WCrt(ba, CRT_ID_CURSOR_START, | 0x20);*/
+			ri->ri_flg |= RI_CURSOR;
+		}
+		offs = gp->g_rowoffset[row] + col;
+		WCrt(ba, CRT_ID_CURSOR_LOC_LOW, offs & 0xff);
+		WCrt(ba, CRT_ID_CURSOR_LOC_HIGH, (offs >> 8) & 0xff);
+		WCrt(ba, CRT_ID_EXT_START, (offs >> (16-2)) & 0x0c);
+	}
+}
+
+static void
+et_wsputchar(void *c, int row, int col, u_int ch, long attr)
+{
+	struct rasops_info *ri;
+	struct vcons_screen *scr;
+	struct grf_softc *gp;
+	volatile unsigned char *ba, *cp;
+
+	ri = c;
+	scr = ri->ri_hw;
+	gp = scr->scr_cookie;
+	ba = gp->g_regkva;
+	cp = gp->g_fbkva;
+
+	cp += gp->g_rowoffset[row] + col;
+	SetTextPlane(ba, 0x00);
+	*cp = ch;
+	SetTextPlane(ba, 0x01);
+	*cp = attr;
+}
+
+static void     
+et_wscopycols(void *c, int row, int srccol, int dstcol, int ncols) 
+{
+	volatile unsigned char *ba, *dst, *src;
+	struct rasops_info *ri;
+	struct vcons_screen *scr;
+	struct grf_softc *gp;
+	int i;
+
+	KASSERT(ncols > 0);
+	ri = c;
+	scr = ri->ri_hw;
+	gp = scr->scr_cookie;
+	ba = gp->g_regkva;
+	src = gp->g_fbkva;
+
+	src += gp->g_rowoffset[row];
+	dst = src;
+	src += srccol;
+	dst += dstcol;
+	if (srccol < dstcol) {
+		/* need to copy backwards */
+		src += ncols;
+		dst += ncols;
+		SetTextPlane(ba, 0x00);
+		for (i = 0; i < ncols; i++)
+			*(--dst) = *(--src);
+		src += ncols;
+		dst += ncols;
+		SetTextPlane(ba, 0x01);
+		for (i = 0; i < ncols; i++)
+			*(--dst) = *(--src);
+	} else {
+		SetTextPlane(ba, 0x00);
+		for (i = 0; i < ncols; i++)
+			*dst++ = *src++;
+		src -= ncols;
+		dst -= ncols;
+		SetTextPlane(ba, 0x01);
+		for (i = 0; i < ncols; i++)
+			*dst++ = *src++;
+	}
+}
+
+static void     
+et_wserasecols(void *c, int row, int startcol, int ncols, long fillattr)
+{
+	volatile unsigned char *ba, *cp;
+	struct rasops_info *ri;
+	struct vcons_screen *scr;
+	struct grf_softc *gp;
+	int i;
+
+	ri = c;
+	scr = ri->ri_hw;
+	gp = scr->scr_cookie;
+	ba = gp->g_regkva;
+	cp = gp->g_fbkva;
+
+	cp += gp->g_rowoffset[row] + startcol;
+	SetTextPlane(ba, 0x00);
+	for (i = 0; i < ncols; i++)
+		*cp++ = 0x20;
+	cp -= ncols;
+	SetTextPlane(ba, 0x01);
+	for (i = 0; i < ncols; i++)
+		*cp++ = 0x07;
+}
+
+static void     
+et_wscopyrows(void *c, int srcrow, int dstrow, int nrows) 
+{
+	volatile unsigned char *ba, *dst, *src;
+	struct rasops_info *ri;
+	struct vcons_screen *scr;
+	struct grf_softc *gp;
+	int i, n;
+
+	KASSERT(nrows > 0);
+	ri = c;
+	scr = ri->ri_hw;
+	gp = scr->scr_cookie;
+	ba = gp->g_regkva;
+	src = dst = gp->g_fbkva;
+	n = ri->ri_cols * nrows;
+
+	if (srcrow < dstrow) {
+		/* need to copy backwards */
+		src += gp->g_rowoffset[srcrow + nrows];
+		dst += gp->g_rowoffset[dstrow + nrows];
+		SetTextPlane(ba, 0x00);
+		for (i = 0; i < n; i++)
+			*(--dst) = *(--src);
+		src += n;
+		dst += n;
+		SetTextPlane(ba, 0x01);
+		for (i = 0; i < n; i++)
+			*(--dst) = *(--src);
+	} else {
+		src += gp->g_rowoffset[srcrow];
+		dst += gp->g_rowoffset[dstrow];
+		SetTextPlane(ba, 0x00);
+		for (i = 0; i < n; i++)
+			*dst++ = *src++;
+		src -= n;
+		dst -= n;
+		SetTextPlane(ba, 0x01);
+		for (i = 0; i < n; i++)
+			*dst++ = *src++;
+	}
+}
+
+static void     
+et_wseraserows(void *c, int row, int nrows, long fillattr) 
+{
+	volatile unsigned char *ba, *cp;
+	struct rasops_info *ri;
+	struct vcons_screen *scr;
+	struct grf_softc *gp;
+	int i, n;
+
+	ri = c;
+	scr = ri->ri_hw;
+	gp = scr->scr_cookie;
+	ba = gp->g_regkva;
+	cp = gp->g_fbkva;
+
+	cp += gp->g_rowoffset[row];
+	n = ri->ri_cols * nrows;
+	SetTextPlane(ba, 0x00);
+	for (i = 0; i < n; i++)
+		*cp++ = 0x20;
+	cp -= n;
+	SetTextPlane(ba, 0x01);
+	for (i = 0; i < n; i++)
+		*cp++ = 0x07;
+}
+
+static int
+et_wsallocattr(void *c, int fg, int bg, int flg, long *attr)
+{
+
+	/* XXX color support? */
+	*attr = (flg & WSATTR_REVERSE) ? 0x70 : 0x07;
+	if (flg & WSATTR_UNDERLINE)	*attr = 0x01;
+	if (flg & WSATTR_HILIT)		*attr |= 0x08;
+	if (flg & WSATTR_BLINK)		*attr |= 0x80;
+	return 0;
+}
+
+/* our font does not support unicode extensions */
+static int      
+et_wsmapchar(void *c, int ch, unsigned int *cp)
+{
+
+	if (ch > 0 && ch < 256) {
+		*cp = ch;
+		return 5;
+	}
+	*cp = ' ';
+	return 0;
+}
+
+static int
+et_wsioctl(void *v, void *vs, u_long cmd, void *data, int flag, struct lwp *l)
+{
+	struct vcons_data *vd;
+	struct grf_softc *gp;
+
+	vd = v;
+	gp = vd->cookie;
+
+	switch (cmd) {
+	case WSDISPLAYIO_GETCMAP:
+		/* Note: wsdisplay_cmap and grf_colormap have same format */
+		if (gp->g_display.gd_planes == 8)
+			return et_getcmap(gp, (struct grf_colormap *)data);
+		return EINVAL;
+
+	case WSDISPLAYIO_PUTCMAP:
+		/* Note: wsdisplay_cmap and grf_colormap have same format */
+		if (gp->g_display.gd_planes == 8)
+			return et_putcmap(gp, (struct grf_colormap *)data);
+		return EINVAL;
+
+	case WSDISPLAYIO_GVIDEO:
+		if (et_isblank(gp))
+			*(u_int *)data = WSDISPLAYIO_VIDEO_OFF;
+		else
+			*(u_int *)data = WSDISPLAYIO_VIDEO_ON;
+		return 0;
+
+	case WSDISPLAYIO_SVIDEO:
+		return et_blank(gp, *(u_int *)data == WSDISPLAYIO_VIDEO_ON);
+
+	case WSDISPLAYIO_SMODE:
+		if ((*(int *)data) != gp->g_wsmode) {
+			if (*(int *)data == WSDISPLAYIO_MODE_EMUL) {
+				/* load console text mode, redraw screen */
+				(void)et_load_mon(gp, &etconsole_mode);
+				if (vd->active != NULL)
+					vcons_redraw_screen(vd->active);
+			} else {
+				/* switch to current graphics mode */
+				if (!et_load_mon(gp,
+				    (struct grfettext_mode *)monitor_current))
+					return EINVAL;
+			}
+			gp->g_wsmode = *(int *)data;
+		} 
+		return 0;
+
+	case WSDISPLAYIO_GET_FBINFO:
+		return et_get_fbinfo(gp, data);
+	}
+
+	/* handle this command hw-independant in grf(4) */
+	return grf_wsioctl(v, vs, cmd, data, flag, l);
+}
+
+/*
+ * Fill the wsdisplayio_fbinfo structure with information from the current
+ * graphics mode. Even when text mode is active.
+ */
+static int
+et_get_fbinfo(struct grf_softc *gp, struct wsdisplayio_fbinfo *fbi)
+{
+	struct grfvideo_mode *md;
+	uint32_t rbits, gbits, bbits;
+
+	md = monitor_current;
+
+	switch (md->depth) {
+	case 8:
+		fbi->fbi_bitsperpixel = 8;
+		rbits = gbits = bbits = 6;  /* keep gcc happy */
+		break;
+	case 15:
+		fbi->fbi_bitsperpixel = 16;
+		rbits = gbits = bbits = 5;
+		break;
+	case 16:
+		fbi->fbi_bitsperpixel = 16;
+		rbits = bbits = 5;
+		gbits = 6;
+		break;
+	case 24:
+		fbi->fbi_bitsperpixel = 24;
+		rbits = gbits = bbits = 8;
+		break;
+	default:
+		return EINVAL;
+	}
+
+	fbi->fbi_stride = (fbi->fbi_bitsperpixel / 8) * md->disp_width;
+	fbi->fbi_width = md->disp_width;
+	fbi->fbi_height = md->disp_height;
+
+	if (md->depth > 8) {
+		fbi->fbi_pixeltype = WSFB_RGB;
+		fbi->fbi_subtype.fbi_rgbmasks.red_offset = bbits + gbits;
+		fbi->fbi_subtype.fbi_rgbmasks.red_size = rbits;
+		fbi->fbi_subtype.fbi_rgbmasks.green_offset = bbits;
+		fbi->fbi_subtype.fbi_rgbmasks.green_size = gbits;
+		fbi->fbi_subtype.fbi_rgbmasks.blue_offset = 0;
+		fbi->fbi_subtype.fbi_rgbmasks.blue_size = bbits;
+		fbi->fbi_subtype.fbi_rgbmasks.alpha_offset = 0;
+		fbi->fbi_subtype.fbi_rgbmasks.alpha_size = 0;
+	} else {
+		fbi->fbi_pixeltype = WSFB_CI;
+		fbi->fbi_subtype.fbi_cmapinfo.cmap_entries = 1 << md->depth;
+	}
+
+	fbi->fbi_flags = 0;
+	fbi->fbi_fbsize = fbi->fbi_stride * fbi->fbi_height;
+	fbi->fbi_fboffset = 0;
+	return 0;
+}
+#endif	/* NWSDISPLAY > 0 */
+
 #endif /* NGRFET */
--- a/sys/arch/amiga/dev/grf_ul.c	Sun Nov 06 11:50:54 2016 +0000
+++ b/sys/arch/amiga/dev/grf_ul.c	Mon Dec 05 10:54:48 2016 +0000
@@ -1,4 +1,4 @@
-/*	$NetBSD: grf_ul.c,v 1.50 2014/01/22 00:25:16 christos Exp $ */
+/*	$NetBSD: grf_ul.c,v 1.50.6.1 2016/12/05 10:54:49 skrll Exp $ */
 #define UL_DEBUG
 
 /*-
@@ -33,7 +33,7 @@
 #include "opt_amigacons.h"
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: grf_ul.c,v 1.50 2014/01/22 00:25:16 christos Exp $");
+__KERNEL_RCSID(0, "$NetBSD: grf_ul.c,v 1.50.6.1 2016/12/05 10:54:49 skrll Exp $");
 
 #include "grful.h"
 #include "ite.h"
@@ -522,7 +522,7 @@
 		gup->gus_isr.isr_intr = ulisr;
 		gup->gus_isr.isr_arg = (void *)gp;
 		/*
-		 * To make sure ints are always catched, first add new isr
+		 * To make sure ints are always caught, first add new isr
 		 * then remove old:
 		 */
 		add_isr(&gup->gus_isr);
--- a/sys/arch/amiga/dev/mntva.c	Sun Nov 06 11:50:54 2016 +0000
+++ b/sys/arch/amiga/dev/mntva.c	Mon Dec 05 10:54:48 2016 +0000
@@ -1,4 +1,4 @@
-/*	$NetBSD: mntva.c,v 1.1.2.2 2016/10/05 20:55:24 skrll Exp $	*/
+/*	$NetBSD: mntva.c,v 1.1.2.3 2016/12/05 10:54:49 skrll Exp $	*/
 
 /*
  * Copyright (c) 2012, 2016 The NetBSD Foundation, Inc.		
@@ -31,7 +31,7 @@
  */
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: mntva.c,v 1.1.2.2 2016/10/05 20:55:24 skrll Exp $");
+__KERNEL_RCSID(0, "$NetBSD: mntva.c,v 1.1.2.3 2016/12/05 10:54:49 skrll Exp $");
 
 #include <sys/param.h>
 #include <sys/systm.h>
@@ -593,6 +593,7 @@
 void 
 mntvacnprobe(struct consdev *cd)
 {
+#ifdef MNTVA_CONSOLE
 	/* 
 	 * This isn't exactly true, but cons.h does not define anything
 	 * that would fit our case exactly.
@@ -600,6 +601,7 @@
 	cd->cn_pri = CN_INTERNAL;
 
 	cd->cn_dev = NODEV; /* Filled later by wscons. */
+#endif /* MNTVA_CONSOLE */
 }
 
 /* ARGSUSED */
--- a/sys/arch/amigappc/conf/GENERIC	Sun Nov 06 11:50:54 2016 +0000
+++ b/sys/arch/amigappc/conf/GENERIC	Mon Dec 05 10:54:48 2016 +0000
@@ -1,4 +1,4 @@
-# $NetBSD: GENERIC,v 1.24.2.1 2015/09/22 12:05:36 skrll Exp $
+# $NetBSD: GENERIC,v 1.24.2.2 2016/12/05 10:54:49 skrll Exp $
 #
 # GENERIC machine description file
 # 
@@ -22,7 +22,7 @@
 
 options 	INCLUDE_CONFIG_FILE     # embed config file in kernel binary
 
-#ident          "GENERIC-$Revision: 1.24.2.1 $"
+#ident          "GENERIC-$Revision: 1.24.2.2 $"
 
 maxusers	8
 
@@ -270,6 +270,10 @@
 ite6		at grf6			# terminal emulators for grfs
 ite7		at grf7			# terminal emulators for grfs
 
+# Needs wscons
+#mntva*          at zbus?                # MNTMN VA2000
+#options         MNTVA_CONSOLE
+
 #
 # Zorro-II, Zorro-III devices (sans graphics)
 #
--- a/sys/arch/amigappc/conf/files.amigappc	Sun Nov 06 11:50:54 2016 +0000
+++ b/sys/arch/amigappc/conf/files.amigappc	Mon Dec 05 10:54:48 2016 +0000
@@ -1,4 +1,4 @@
-#	$NetBSD: files.amigappc,v 1.28 2014/01/22 00:24:39 christos Exp $
+#	$NetBSD: files.amigappc,v 1.28.6.1 2016/12/05 10:54:49 skrll Exp $
 
 # maxpartitions must be first item in files.${ARCH}.newconf
 maxpartitions 16			# NOTE THAT AMIGA IS SPECIAL!
@@ -20,6 +20,8 @@
 defflag	opt_amigacons.h		CV3DONZORRO2
 defflag	opt_amigacons.h		SERCONSOLE
 
+defflag	opt_mntva.h		MNTVA_CONSOLE
+
 defflag	opt_kfont.h		KFONT_CONS_ISO8859_1
 defflag	opt_kfont.h		KFONT_CONS_ISO8859_2
 
@@ -205,6 +207,11 @@
 file	arch/amiga/dev/grf_cv.c		grfcv needs-flag
 file	arch/amiga/dev/ite_cv.c		grfcv & ite
 
+# MNT VA2000
+device	mntva: wsemuldisplaydev, rasops16, rasops32, vcons, videomode
+attach	mntva at zbus
+file	arch/amiga/dev/mntva.c		mntva needs-flag
+
 # Tseng grf (ite6 grf6)
 device	grfet: grfbus
 attach	grfet at zbus
--- a/sys/arch/arc/include/isa_machdep.h	Sun Nov 06 11:50:54 2016 +0000
+++ b/sys/arch/arc/include/isa_machdep.h	Mon Dec 05 10:54:48 2016 +0000
@@ -1,4 +1,4 @@
-/*	$NetBSD: isa_machdep.h,v 1.16 2012/10/27 17:17:35 chs Exp $	*/
+/*	$NetBSD: isa_machdep.h,v 1.16.14.1 2016/12/05 10:54:49 skrll Exp $	*/
 /*      $OpenBSD: isa_machdep.h,v 1.5 1997/04/19 17:20:00 pefo Exp $  */
 
 /*
@@ -72,6 +72,8 @@
     (*(c)->ic_intr_evcnt)((c)->ic_data, (i))
 #define isa_intr_establish(c, i, t, l, f, a)                         \
     (*(c)->ic_intr_establish)((c)->ic_data, (i), (t), (l), (f), (a))
+#define isa_intr_establish_xname(c, i, t, l, f, a, x)			\
+    (*(c)->ic_intr_establish)((c)->ic_data, (i), (t), (l), (f), (a))
 #define isa_intr_disestablish(c, h)                                     \
     (*(c)->ic_intr_disestablish)((c)->ic_data, (h))
 
--- a/sys/arch/arm/arm/cpufunc.c	Sun Nov 06 11:50:54 2016 +0000
+++ b/sys/arch/arm/arm/cpufunc.c	Mon Dec 05 10:54:48 2016 +0000
@@ -1,4 +1,4 @@
-/*	$NetBSD: cpufunc.c,v 1.150.4.6 2016/07/09 20:24:49 skrll Exp $	*/
+/*	$NetBSD: cpufunc.c,v 1.150.4.7 2016/12/05 10:54:49 skrll Exp $	*/
 
 /*
  * arm7tdmi support code Copyright (c) 2001 John Fremlin
@@ -49,7 +49,7 @@
  */
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: cpufunc.c,v 1.150.4.6 2016/07/09 20:24:49 skrll Exp $");
+__KERNEL_RCSID(0, "$NetBSD: cpufunc.c,v 1.150.4.7 2016/12/05 10:54:49 skrll Exp $");
 
 #include "opt_compat_netbsd.h"
 #include "opt_cpuoptions.h"
@@ -2158,13 +2158,13 @@
 	    cputype == CPU_ID_ARM_88SV581X_V6 ||
 	    cputype == CPU_ID_ARM_88SV581X_V7) &&
 	    (armreg_pfr0_read() & ARM_PFR0_THUMBEE_MASK)) {
-			cpufuncs = pj4bv7_cpufuncs;
+		cpufuncs = pj4bv7_cpufuncs;
 #if defined(CPU_ARMV6) || defined(CPU_PRE_ARMV6)
-			cpu_armv7_p = true;
+		cpu_armv7_p = true;
 #endif
-			get_cachetype_cp15();
-			pmap_pte_init_armv7();
-			return 0;
+		get_cachetype_cp15();
+		pmap_pte_init_armv7();
+		return 0;
 	}
 #endif /* CPU_PJ4B */
 
--- a/sys/arch/arm/arm32/bus_dma.c	Sun Nov 06 11:50:54 2016 +0000
+++ b/sys/arch/arm/arm32/bus_dma.c	Mon Dec 05 10:54:48 2016 +0000
@@ -1,4 +1,4 @@
-/*	$NetBSD: bus_dma.c,v 1.89.2.3 2015/12/27 12:09:30 skrll Exp $	*/
+/*	$NetBSD: bus_dma.c,v 1.89.2.4 2016/12/05 10:54:49 skrll Exp $	*/
 
 /*-
  * Copyright (c) 1996, 1997, 1998 The NetBSD Foundation, Inc.
@@ -35,7 +35,7 @@
 #include "opt_arm_bus_space.h"
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: bus_dma.c,v 1.89.2.3 2015/12/27 12:09:30 skrll Exp $");
+__KERNEL_RCSID(0, "$NetBSD: bus_dma.c,v 1.89.2.4 2016/12/05 10:54:49 skrll Exp $");
 
 #include <sys/param.h>
 #include <sys/systm.h>
@@ -1086,9 +1086,13 @@
 #else
 	const int post_ops = 0;
 #endif
-	if (!bouncing && pre_ops == 0 && post_ops == BUS_DMASYNC_POSTWRITE) {
-		STAT_INCR(sync_postwrite);
-		return;
+	if (!bouncing) {
+		if (pre_ops == 0 && post_ops == BUS_DMASYNC_POSTWRITE) {
+			STAT_INCR(sync_postwrite);
+			return;
+		} else if (pre_ops == 0 && post_ops == 0) {
+			return;
+		}
 	}
 	KASSERTMSG(bouncing || pre_ops != 0 || (post_ops & BUS_DMASYNC_POSTREAD),
 	    "pre_ops %#x post_ops %#x", pre_ops, post_ops);
--- a/sys/arch/arm/broadcom/bcm2835_vcaudio.c	Sun Nov 06 11:50:54 2016 +0000
+++ b/sys/arch/arm/broadcom/bcm2835_vcaudio.c	Mon Dec 05 10:54:48 2016 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: bcm2835_vcaudio.c,v 1.7.2.2 2015/09/22 12:05:37 skrll Exp $ */
+/* $NetBSD: bcm2835_vcaudio.c,v 1.7.2.3 2016/12/05 10:54:49 skrll Exp $ */
 
 /*-
  * Copyright (c) 2013 Jared D. McNeill <jmcneill@invisible.ca>
@@ -31,7 +31,7 @@
  */
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: bcm2835_vcaudio.c,v 1.7.2.2 2015/09/22 12:05:37 skrll Exp $");
+__KERNEL_RCSID(0, "$NetBSD: bcm2835_vcaudio.c,v 1.7.2.3 2016/12/05 10:54:49 skrll Exp $");
 
 #include <sys/param.h>
 #include <sys/types.h>
@@ -436,7 +436,7 @@
 				sched = true;
 			}
 
-			if (sched) {
+			if (sched && sc->sc_pint) {
 				intr(intrarg);
 				sc->sc_abytes += sc->sc_pblksize;
 				cv_signal(&sc->sc_datacv);
--- a/sys/arch/arm/broadcom/bcm53xx_board.c	Sun Nov 06 11:50:54 2016 +0000
+++ b/sys/arch/arm/broadcom/bcm53xx_board.c	Mon Dec 05 10:54:48 2016 +0000
@@ -1,4 +1,4 @@
-/*	$NetBSD: bcm53xx_board.c,v 1.22 2014/09/14 21:06:37 skrll Exp $	*/
+/*	$NetBSD: bcm53xx_board.c,v 1.22.2.1 2016/12/05 10:54:49 skrll Exp $	*/
 /*-
  * Copyright (c) 2012 The NetBSD Foundation, Inc.
  * All rights reserved.
@@ -35,7 +35,7 @@
 
 #include <sys/cdefs.h>
 
-__KERNEL_RCSID(1, "$NetBSD: bcm53xx_board.c,v 1.22 2014/09/14 21:06:37 skrll Exp $");
+__KERNEL_RCSID(1, "$NetBSD: bcm53xx_board.c,v 1.22.2.1 2016/12/05 10:54:49 skrll Exp $");
 
 #include <sys/param.h>
 #include <sys/bus.h>
@@ -604,7 +604,7 @@
 		 * XXX KLUDGE ALERT XXX
 		 * The iot mainbus supplies is completely wrong since it scales
 		 * addresses by 2.  The simplest remedy is to replace with our
-		 * bus space used for the armcore regisers (which armperiph uses). 
+		 * bus space used for the armcore registers (which armperiph uses). 
 		 */
 		struct mainbus_attach_args * const mb = aux;
 		mb->mb_iot = bcm53xx_armcore_bst;
--- a/sys/arch/arm/cortex/a9_mpsubr.S	Sun Nov 06 11:50:54 2016 +0000
+++ b/sys/arch/arm/cortex/a9_mpsubr.S	Mon Dec 05 10:54:48 2016 +0000
@@ -1,4 +1,4 @@
-/*	$NetBSD: a9_mpsubr.S,v 1.24.2.4 2015/12/27 12:09:30 skrll Exp $	*/
+/*	$NetBSD: a9_mpsubr.S,v 1.24.2.5 2016/12/05 10:54:50 skrll Exp $	*/
 /*-
  * Copyright (c) 2012 The NetBSD Foundation, Inc.
  * All rights reserved.
@@ -507,10 +507,12 @@
 #if defined(MULTIPROCESSOR) || defined(CPU_CORTEXA5) || defined(CPU_CORTEXA7) || defined(CPU_CORTEXA9) || defined(CPU_CORTEXA15) || defined(CPU_CORTEXA17)
 #if defined(CPU_CORTEXA5) || defined(CPU_CORTEXA7) || defined(CPU_CORTEXA9) || defined(CPU_CORTEXA15) || defined(CPU_CORTEXA17)
 	//
-	// Step 4a, set ACTLR.SMP=1
+	// Step 4a, set ACTLR.SMP=1, if ACTLR.SMP=0
+	// i.e. OMAP4430 was enabled yet.
 	//
 	mrc	p15, 0, r0, c1, c0, 1		// ACTLR read
-	orr	r0, r0, #CORTEXA9_AUXCTL_SMP	// enable SMP
+	tst	r0, #CORTEXA9_AUXCTL_SMP
+	orreq	r0, r0, #CORTEXA9_AUXCTL_SMP	// enable SMP
 
 #if defined(CPU_CORTEXA15)
 	// The A15 requires snoop-delayed exclusive handling to be set
@@ -524,16 +526,16 @@
 	//
 	// Step 4a (continued on A5/A9), ACTLR.FW=1)
 	//
-	orr	r0, r0, #CORTEXA9_AUXCTL_FW	// enable cache/tlb/coherency
+	orreq	r0, r0, #CORTEXA9_AUXCTL_FW	// enable cache/tlb/coherency
 #endif	/* A5 || A9 */
 #if defined(CPU_CORTEXA9)
 	//
 	// Step 4b (continued on A9), ACTLR.L2PE=1)
 	//
-	orr	r0, r0, #CORTEXA9_AUXCTL_L2PE	// enable L2 cache prefetch
+	orreq	r0, r0, #CORTEXA9_AUXCTL_L2PE	// enable L2 cache prefetch
 #endif
 
-	mcr	p15, 0, r0, c1, c0, 1		// ACTLR write
+	mcreq	p15, 0, r0, c1, c0, 1		// ACTLR write
 	isb
 	dsb
 #endif	/* A5 || A7 || A9 || A15 || A17 */
--- a/sys/arch/arm/cortex/a9wdt.c	Sun Nov 06 11:50:54 2016 +0000
+++ b/sys/arch/arm/cortex/a9wdt.c	Mon Dec 05 10:54:48 2016 +0000
@@ -1,4 +1,4 @@
-/*	$NetBSD: a9wdt.c,v 1.2.4.1 2015/04/06 15:17:52 skrll Exp $	*/
+/*	$NetBSD: a9wdt.c,v 1.2.4.2 2016/12/05 10:54:50 skrll Exp $	*/
 
 /*-
  * Copyright (c) 2012 The NetBSD Foundation, Inc.
@@ -30,7 +30,7 @@
  */
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: a9wdt.c,v 1.2.4.1 2015/04/06 15:17:52 skrll Exp $");
+__KERNEL_RCSID(0, "$NetBSD: a9wdt.c,v 1.2.4.2 2016/12/05 10:54:50 skrll Exp $");
 
 #include <sys/param.h>
 #include <sys/bus.h>
@@ -253,4 +253,8 @@
 			aprint_error_dev(self,
 			    "failed to start kernel tickler: %d\n", error);
  	}
+
+	if (sysmon_wdog_register(&sc->sc_smw) != 0)
+		aprint_error("%s: unable to register with sysmon\n",
+		    device_xname(sc->sc_dev));
 }
--- a/sys/arch/arm/cortex/scu_reg.h	Sun Nov 06 11:50:54 2016 +0000
+++ b/sys/arch/arm/cortex/scu_reg.h	Mon Dec 05 10:54:48 2016 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: scu_reg.h,v 1.1 2012/09/01 00:03:14 matt Exp $ */
+/* $NetBSD: scu_reg.h,v 1.1.22.1 2016/12/05 10:54:50 skrll Exp $ */
 /*-
  * Copyright (c) 2012 The NetBSD Foundation, Inc.
  * All rights reserved.
@@ -36,6 +36,8 @@
  * Used by Cortex-A5 and Cortex-A9
  */
 
+#define	SCU_SIZE		0x100
+
 #define	SCU_CTL			0x00	// SCU Control Register
 #define	SCU_CFG			0x04	// SCU Configuration Register
 #define	SCU_CPU_PWR_STS		0x08	// SCU CPU Power Status
--- a/sys/arch/arm/imx/files.imx6	Sun Nov 06 11:50:54 2016 +0000
+++ b/sys/arch/arm/imx/files.imx6	Mon Dec 05 10:54:48 2016 +0000
@@ -1,4 +1,4 @@
-#	$NetBSD: files.imx6,v 1.4.2.3 2016/05/29 08:44:16 skrll Exp $
+#	$NetBSD: files.imx6,v 1.4.2.4 2016/12/05 10:54:50 skrll Exp $
 #
 # Configuration info for the Freescale i.MX6
 #
@@ -26,6 +26,11 @@
 attach	axi at mainbus
 file	arch/arm/imx/imx6_axi.c			axi
 
+# iMX6 PCIe
+device	imxpcie: pcibus
+attach	imxpcie at axi
+file	arch/arm/imx/imx6_pcie.c		imxpcie
+
 # iMX6 Clock Control Module
 device	imxccm
 attach	imxccm at axi
@@ -101,4 +106,3 @@
 attach	imxsnvs at axi
 file	arch/arm/imx/imxsnvs.c			imxsnvs
 file	arch/arm/imx/imx6_snvs.c		imxsnvs
-
--- a/sys/arch/arm/imx/files.imx7	Sun Nov 06 11:50:54 2016 +0000
+++ b/sys/arch/arm/imx/files.imx7	Mon Dec 05 10:54:48 2016 +0000
@@ -1,4 +1,4 @@
-#	$NetBSD: files.imx7,v 1.1.2.2 2016/05/29 08:44:16 skrll Exp $
+#	$NetBSD: files.imx7,v 1.1.2.3 2016/12/05 10:54:50 skrll Exp $
 #
 # Configuration info for the Freescale i.MX7
 #
@@ -7,6 +7,7 @@
 include "arch/arm/cortex/files.cortex"
 
 defparam opt_imx.h				MEMSIZE
+defparam opt_imx.h				MEMSIZE_RESERVED
 defflag opt_imx.h				IMX7
 
 file	arch/arm/arm32/arm32_boot.c
--- a/sys/arch/arm/imx/if_enet_imx6.c	Sun Nov 06 11:50:54 2016 +0000
+++ b/sys/arch/arm/imx/if_enet_imx6.c	Mon Dec 05 10:54:48 2016 +0000
@@ -1,4 +1,4 @@
-/*	$NetBSD: if_enet_imx6.c,v 1.1.2.2 2016/05/29 08:44:16 skrll Exp $	*/
+/*	$NetBSD: if_enet_imx6.c,v 1.1.2.3 2016/12/05 10:54:50 skrll Exp $	*/
 
 /*
  * Copyright (c) 2014 Ryo Shimizu <ryo@nerv.org>
@@ -27,7 +27,7 @@
  */
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: if_enet_imx6.c,v 1.1.2.2 2016/05/29 08:44:16 skrll Exp $");
+__KERNEL_RCSID(0, "$NetBSD: if_enet_imx6.c,v 1.1.2.3 2016/12/05 10:54:50 skrll Exp $");
 
 #include "locators.h"
 #include "imxccm.h"
@@ -93,7 +93,8 @@
 
 #if NIMXCCM > 0
 	/* PLL power up */
-	if (imx6_pll_power(CCM_ANALOG_PLL_ENET, 1) != 0) {
+	if (imx6_pll_power(CCM_ANALOG_PLL_ENET, 1,
+		CCM_ANALOG_PLL_ENET_ENABLE) != 0) {
 		aprint_error_dev(sc->sc_dev,
 		    "couldn't enable CCM_ANALOG_PLL_ENET\n");
 		return;
--- a/sys/arch/arm/imx/imx6_ahcisata.c	Sun Nov 06 11:50:54 2016 +0000
+++ b/sys/arch/arm/imx/imx6_ahcisata.c	Mon Dec 05 10:54:48 2016 +0000
@@ -1,4 +1,4 @@
-/*	$NetBSD: imx6_ahcisata.c,v 1.2.2.1 2016/03/19 11:29:56 skrll Exp $	*/
+/*	$NetBSD: imx6_ahcisata.c,v 1.2.2.2 2016/12/05 10:54:50 skrll Exp $	*/
 
 /*
  * Copyright (c) 2014 Ryo Shimizu <ryo@nerv.org>
@@ -27,7 +27,7 @@
  */
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: imx6_ahcisata.c,v 1.2.2.1 2016/03/19 11:29:56 skrll Exp $");
+__KERNEL_RCSID(0, "$NetBSD: imx6_ahcisata.c,v 1.2.2.2 2016/12/05 10:54:50 skrll Exp $");
 
 #include "locators.h"
 #include "opt_imx.h"
@@ -266,7 +266,8 @@
 	imx6_ccm_write(CCM_CCGR5, v | CCM_CCGR5_100M_CLK_ENABLE(3));
 
 	/* PLL power up */
-	if (imx6_pll_power(CCM_ANALOG_PLL_ENET, 1) != 0) {
+	if (imx6_pll_power(CCM_ANALOG_PLL_ENET, 1,
+		CCM_ANALOG_PLL_ENET_ENABLE_100M) != 0) {
 		aprint_error_dev(sc->sc_dev,
 		    "couldn't enable CCM_ANALOG_PLL_ENET\n");
 		return -1;
--- a/sys/arch/arm/imx/imx6_board.c	Sun Nov 06 11:50:54 2016 +0000
+++ b/sys/arch/arm/imx/imx6_board.c	Mon Dec 05 10:54:48 2016 +0000
@@ -1,4 +1,4 @@
-/*	$NetBSD: imx6_board.c,v 1.2.2.3 2016/03/19 11:29:56 skrll Exp $	*/
+/*	$NetBSD: imx6_board.c,v 1.2.2.4 2016/12/05 10:54:50 skrll Exp $	*/
 
 /*
  * Copyright (c) 2012  Genetec Corporation.  All rights reserved.
@@ -27,7 +27,7 @@
  */
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(1, "$NetBSD: imx6_board.c,v 1.2.2.3 2016/03/19 11:29:56 skrll Exp $");
+__KERNEL_RCSID(1, "$NetBSD: imx6_board.c,v 1.2.2.4 2016/12/05 10:54:50 skrll Exp $");
 
 #include "opt_imx.h"
 #include "arml2cc.h"
@@ -36,6 +36,7 @@
 #include <sys/bus.h>
 #include <sys/cpu.h>
 #include <sys/device.h>
+#include <sys/gpio.h>
 
 #include <arm/locore.h>
 #include <arm/cortex/a9tmr_var.h>
@@ -47,6 +48,7 @@
 #include <arm/imx/imx6_mmdcreg.h>
 #include <arm/imx/imx6_ccmreg.h>
 #include <arm/imx/imxwdogreg.h>
+#include <arm/imx/imxgpiovar.h>
 
 bus_space_tag_t imx6_ioreg_bst = &armv7_generic_bs_tag;
 bus_space_handle_t imx6_ioreg_bsh;
@@ -205,7 +207,7 @@
 		 * XXX KLUDGE ALERT XXX
 		 * The iot mainbus supplies is completely wrong since it scales
 		 * addresses by 2.  The simpliest remedy is to replace with our
-		 * bus space used for the armcore regisers (which armperiph uses).
+		 * bus space used for the armcore registers (which armperiph uses).
 		 */
 		struct mainbus_attach_args * const mb = aux;
 		mb->mb_iot = imx6_armcore_bst;
@@ -230,3 +232,50 @@
 	a9tmr_init_cpu_clock(ci);
 }
 #endif
+
+void
+imx6_set_gpio(device_t self, const char *name, int32_t *gpio,
+    int32_t *active, u_int dir)
+{
+	prop_dictionary_t dict;
+	const char *pin_data;
+	int grp, pin;
+
+	*gpio = -1;
+	*active = -1;
+
+	dict = device_properties(self);
+	if (!prop_dictionary_get_cstring_nocopy(dict, name, &pin_data))
+		return;
+
+	/*
+	 * "!1,6" -> gpio = GPIO_NO(1,6),  active = GPIO_PIN_LOW
+	 * "3,31" -> gpio = GPIO_NO(3,31), active = GPIO_PIN_HIGH
+	 * "!"    -> always not detected
+	 * none   -> always detected
+	 */
+	if (*pin_data == '!') {
+		*active = GPIO_PIN_LOW;
+		pin_data++;
+	} else
+		*active = GPIO_PIN_HIGH;
+
+	if (*pin_data == '\0')
+		return;
+
+	for (grp = 0; (*pin_data >= '0') && (*pin_data <= '9'); pin_data++)
+		grp = grp * 10 + *pin_data - '0';
+
+	KASSERT(*pin_data == ',');
+	pin_data++;
+
+	for (pin = 0; (*pin_data >= '0') && (*pin_data <= '9'); pin_data++)
+		pin = pin * 10 + *pin_data - '0';
+
+	KASSERT(*pin_data == '\0');
+
+	*gpio = GPIO_NO(grp, pin);
+#if NIMXGPIO > 0
+	gpio_set_direction(*gpio, dir);
+#endif
+}
--- a/sys/arch/arm/imx/imx6_ccm.c	Sun Nov 06 11:50:54 2016 +0000
+++ b/sys/arch/arm/imx/imx6_ccm.c	Mon Dec 05 10:54:48 2016 +0000
@@ -1,4 +1,4 @@
-/*	$NetBSD: imx6_ccm.c,v 1.3.2.1 2015/04/06 15:17:52 skrll Exp $	*/
+/*	$NetBSD: imx6_ccm.c,v 1.3.2.2 2016/12/05 10:54:50 skrll Exp $	*/
 
 /*
  * Copyright (c) 2010-2012, 2014  Genetec Corporation.  All rights reserved.
@@ -31,7 +31,7 @@
  */
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: imx6_ccm.c,v 1.3.2.1 2015/04/06 15:17:52 skrll Exp $");
+__KERNEL_RCSID(0, "$NetBSD: imx6_ccm.c,v 1.3.2.2 2016/12/05 10:54:50 skrll Exp $");
 
 #include "opt_imx.h"
 #include "opt_imx6clk.h"
@@ -851,7 +851,7 @@
 }
 
 int
-imx6_pll_power(uint32_t pllreg, int on)
+imx6_pll_power(uint32_t pllreg, int on, uint32_t en)
 {
 	uint32_t v;
 	int timeout;
@@ -861,10 +861,10 @@
 	case CCM_ANALOG_PLL_USB2:
 		v = imx6_ccm_read(pllreg);
 		if (on) {
-			v |= CCM_ANALOG_PLL_USBn_ENABLE;
+			v |= en;
 			v &= ~CCM_ANALOG_PLL_USBn_BYPASS;
 		} else {
-			v &= ~CCM_ANALOG_PLL_USBn_ENABLE;
+			v &= ~en;
 		}
 		imx6_ccm_write(pllreg, v);
 		return 0;
@@ -885,11 +885,13 @@
 		if (timeout <= 0)
 			break;
 
+		v |= CCM_ANALOG_PLL_ENET_ENABLE;
 		if (on) {
 			v &= ~CCM_ANALOG_PLL_ENET_BYPASS;
-			v |= CCM_ANALOG_PLL_ENET_ENABLE;
+			imx6_ccm_write(pllreg, v);
+			v |= en;
 		} else {
-			v &= ~CCM_ANALOG_PLL_ENET_ENABLE;
+			v &= ~en;
 		}
 		imx6_ccm_write(pllreg, v);
 		return 0;
--- a/sys/arch/arm/imx/imx6_ccmreg.h	Sun Nov 06 11:50:54 2016 +0000
+++ b/sys/arch/arm/imx/imx6_ccmreg.h	Mon Dec 05 10:54:48 2016 +0000
@@ -1,4 +1,4 @@
-/*	$NetBSD: imx6_ccmreg.h,v 1.2.2.1 2015/04/06 15:17:52 skrll Exp $	*/
+/*	$NetBSD: imx6_ccmreg.h,v 1.2.2.2 2016/12/05 10:54:50 skrll Exp $	*/
 
 /*
  * Copyright (c) 2014 Ryo Shimizu <ryo@nerv.org>
@@ -79,7 +79,7 @@
 #define  CCM_CBCMR_VPU_AXI_CLK_SEL		__BITS(15, 14)
 #define  CCM_CBCMR_PERIPH_CLK2_SEL		__BITS(13, 12)
 #define  CCM_CBCMR_VDOAXI_CLK_SEL		__BIT(11)
-#define  CCM_CBCMR_PCIE_AXI_CLK_SE		__BIT(10)
+#define  CCM_CBCMR_PCIE_AXI_CLK_SEL		__BIT(10)
 #define  CCM_CBCMR_GPU3D_SHADER_CLK_SEL		__BITS(9, 8)
 #define  CCM_CBCMR_GPU3D_CORE_CLK_SEL		__BITS(5, 4)
 #define  CCM_CBCMR_GPU3D_AXI_CLK_SEL		__BIT(1)
@@ -140,6 +140,37 @@
 #define  CCM_CSCDR3_IPU1_HSP_PODF		__BITS(13, 11)
 #define  CCM_CSCDR3_IPU1_HSP_CLK_SEL		__BITS(10, 9)
 
+#define CCM_CCGR2						0x00000070
+#define  CCM_CCGR2_IPSYNC_VDOA_IPG_CLK_ENABLE(n)		__SHIFTIN(n, __BITS(27, 26))
+#define  CCM_CCGR2_IPSYNC_IP2APB_TZASC2_IPG_CLK_ENABLE(n)       __SHIFTIN(n, __BITS(25, 24))
+#define  CCM_CCGR2_IPSYNC_IP2APB_TZASC1_IPG_CLK_ENABLE(n)       __SHIFTIN(n, __BITS(23, 22))
+#define  CCM_CCGR2_IPMUX3_CLK_ENABLE(n)				__SHIFTIN(n, __BITS(21, 20))
+#define  CCM_CCGR2_IPMUX2_CLK_ENABLE(n)				__SHIFTIN(n, __BITS(19, 18))
+#define  CCM_CCGR2_IPMUX1_CLK_ENABLE(n)				__SHIFTIN(n, __BITS(17, 16))
+#define  CCM_CCGR2_IOMUX_IPT_CLK_IO_CLK_ENABLE(n)		__SHIFTIN(n, __BITS(15, 14))
+#define  CCM_CCGR2_IIM_CLK_ENABLE(n)				__SHIFTIN(n, __BITS(13, 12))
+#define  CCM_CCGR2_I2C3_SERIAL_CLK_ENABLE(n)			__SHIFTIN(n, __BITS(11, 10))
+#define  CCM_CCGR2_I2C2_SERIAL_CLK_ENABLE(n)			__SHIFTIN(n, __BITS(9, 8))
+#define  CCM_CCGR2_I2C1_SERIAL_CLK_ENABLE(n)			__SHIFTIN(n, __BITS(7, 6))
+#define  CCM_CCGR2_HDMI_TX_ISFRCLK_ENABLE(n)			__SHIFTIN(n, __BITS(5, 4))
+#define  CCM_CCGR2_HDMI_TX_IAHBCLK_ENABLE(n)			__SHIFTIN(n, __BITS(1, 0))
+#define CCM_CCGR4	0x00000078
+#define  CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_CLK_ENABLE(N)		__SHIFTIN(n, __BITS(31, 30))
+#define  CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_CLK_ENABLE(n) 	__SHIFTIN(n, __BITS(29, 28))
+#define  CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_CLK_ENABLE(n)		__SHIFTIN(n, __BITS(27, 26))
+#define  CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_CLK_ENABLE(n)		__SHIFTIN(n, __BITS(25, 24))
+#define  CCM_CCGR4_PWM4_CLK_ENABLE(n)					__SHIFTIN(n, __BITS(23, 22))
+#define  CCM_CCGR4_PWM3_CLK_ENABLE(n)					__SHIFTIN(n, __BITS(21, 20))
+#define  CCM_CCGR4_PWM2_CLK_ENABLE(n)					__SHIFTIN(n, __BITS(19, 18))
+#define  CCM_CCGR4_PWM1_CLK_ENABLE(n)					__SHIFTIN(n, __BITS(17, 16))
+#define  CCM_CCGR4_PL301_MX6QPER2_MAINCLK_ENABLE(n)			__SHIFTIN(n, __BITS(15, 14))
+#define  CCM_CCGR4_PL301_MX6QPER1_BCHCLK_ENABLE(n)			__SHIFTIN(n, __BITS(13, 12))
+#define  CCM_CCGR4_CG5_ENABLE(n)					__SHIFTIN(n, __BITS(11, 10))
+#define  CCM_CCGR4_PL301_MX6QFAST1_S133CLK_ENABLE(n)			__SHIFTIN(n, __BITS(9, 8))
+#define  CCM_CCGR4_CG3_ENABLE(n)					__SHIFTIN(n, __BITS(7, 6))
+#define  CCM_CCGR4_CG2_ENABLE(n)					__SHIFTIN(n, __BITS(5, 4))
+#define  CCM_CCGR4_CG1_ENABLE(n)					__SHIFTIN(n, __BITS(3, 2))
+#define  CCM_CCGR4_125M_ROOT_ENABLE(n)					__SHIFTIN(n, __BITS(1, 0))
 #define CCM_CCGR5				0x0000007c
 #define  CCM_CCGR5_UART_SERIAL_CLK_ENABLE(n)	__SHIFTIN(n, __BITS(27, 26))
 #define  CCM_CCGR5_UART_CLK_ENABLE(n)		__SHIFTIN(n, __BITS(25, 24))
@@ -186,6 +217,7 @@
 #define CCM_ANALOG_PLL_SYS_SET			0x00004034
 #define CCM_ANALOG_PLL_SYS_CLR			0x00004038
 #define CCM_ANALOG_PLL_SYS_TOG			0x0000403c
+#define  CCM_ANALOG_PLL_SYS_ENABLE		__BIT(13)
 #define  CCM_ANALOG_PLL_SYS_DIV_SELECT		__BIT(0)
 #define CCM_ANALOG_PLL_SYS_SS			0x00004040
 #define CCM_ANALOG_PLL_SYS_NUM			0x00004050
@@ -256,7 +288,18 @@
 #define CCM_ANALOG_MISC0			0x00004150
 #define CCM_ANALOG_MISC0_SET			0x00004154
 #define CCM_ANALOG_MISC0_CLR			0x00004158
-#define CCM_ANALOG_MISC0_TOG			0x0000415C
+#define CCM_ANALOG_MISC0_TOG			0x0000415c
+#define CCM_ANALOG_MISC1			0x00004160
+#define CCM_ANALOG_MISC1_SET			0x00004164
+#define CCM_ANALOG_MISC1_CLR			0x00004168
+#define CCM_ANALOG_MISC1_TOG			0x0000416c
+#define  CCM_ANALOG_MISC1_LVDS_CLK1_SRC		__BITS(4, 0)
+#define  CCM_ANALOG_MISC1_LVDS_CLK1_SRC_PCIE	__SHIFTIN(0xa, CCM_ANALOG_MISC1_LVDS_CLK1_SRC)
+#define  CCM_ANALOG_MISC1_LVDS_CLK1_SRC_SATA	__SHIFTIN(0xb, CCM_ANALOG_MISC1_LVDS_CLK1_SRC)
+#define  CCM_ANALOG_MISC1_LVDS_CLK1_OBEN	__BIT(10)
+#define  CCM_ANALOG_MISC1_LVDS_CLK2_OBEN	__BIT(11)
+#define  CCM_ANALOG_MISC1_LVDS_CLK1_IBEN	__BIT(12)
+#define  CCM_ANALOG_MISC1_LVDS_CLK2_IBEN	__BIT(13)
 #define CCM_ANALOG_MISC2			0x00004170
 #define CCM_ANALOG_MISC2_SET			0x00004174
 #define CCM_ANALOG_MISC2_CLR			0x00004178
--- a/sys/arch/arm/imx/imx6_ccmvar.h	Sun Nov 06 11:50:54 2016 +0000
+++ b/sys/arch/arm/imx/imx6_ccmvar.h	Mon Dec 05 10:54:48 2016 +0000
@@ -1,4 +1,4 @@
-/*	$NetBSD: imx6_ccmvar.h,v 1.2.2.1 2015/04/06 15:17:52 skrll Exp $	*/
+/*	$NetBSD: imx6_ccmvar.h,v 1.2.2.2 2016/12/05 10:54:50 skrll Exp $	*/
 /*
  * Copyright (c) 2012  Genetec Corporation.  All rights reserved.
  * Written by Hashimoto Kenichi for Genetec Corporation.
@@ -75,7 +75,7 @@
 
 uint32_t imx6_get_clock(enum imx6_clock);
 int imx6_set_clock(enum imx6_clock, uint32_t);
-int imx6_pll_power(uint32_t, int);
+int imx6_pll_power(uint32_t, int, uint32_t);
 
 uint32_t imx6_ccm_read(uint32_t);
 void imx6_ccm_write(uint32_t, uint32_t);
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/sys/arch/arm/imx/imx6_pcie.c	Mon Dec 05 10:54:48 2016 +0000
@@ -0,0 +1,941 @@
+/*	$NetBSD: imx6_pcie.c,v 1.2.2.2 2016/12/05 10:54:50 skrll Exp $	*/
+
+/*
+ * Copyright (c) 2016  Genetec Corporation.  All rights reserved.
+ * Written by Hashimoto Kenichi for Genetec Corporation.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY GENETEC CORPORATION ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL GENETEC CORPORATION
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ * i.MX6 On-Chip PCI Express Controller
+ */
+
+#include <sys/cdefs.h>
+__KERNEL_RCSID(0, "$NetBSD: imx6_pcie.c,v 1.2.2.2 2016/12/05 10:54:50 skrll Exp $");
+
+#include "opt_pci.h"
+
+#include "pci.h"
+#include "imxgpio.h"
+#include "locators.h"
+
+#include <sys/bus.h>
+#include <sys/device.h>
+#include <sys/intr.h>
+#include <sys/systm.h>
+#include <sys/param.h>
+#include <sys/kernel.h>
+#include <sys/extent.h>
+#include <sys/queue.h>
+#include <sys/mutex.h>
+#include <sys/kmem.h>
+#include <sys/gpio.h>
+
+#include <machine/frame.h>
+#include <arm/cpufunc.h>
+
+#include <dev/pci/pcireg.h>
+#include <dev/pci/pcivar.h>
+#include <dev/pci/pciconf.h>
+
+#include <arm/imx/imxgpioreg.h>
+#include <arm/imx/imxgpiovar.h>
+#include <arm/imx/imx6var.h>
+#include <arm/imx/imx6_reg.h>
+#include <arm/imx/imx6_pciereg.h>
+#include <arm/imx/imx6_iomuxreg.h>
+#include <arm/imx/imx6_ccmreg.h>
+#include <arm/imx/imx6_ccmvar.h>
+
+static int imx6pcie_match(device_t, cfdata_t, void *);
+static void imx6pcie_attach(device_t, device_t, void *);
+
+#define IMX6_PCIE_MEM_BASE	0x01000000
+#define IMX6_PCIE_MEM_SIZE	0x00f00000 /* 15MB */
+#define IMX6_PCIE_ROOT_BASE	0x01f00000
+#define IMX6_PCIE_ROOT_SIZE	0x00080000 /* 512KB */
+#define IMX6_PCIE_IO_BASE	0x01f80000
+#define IMX6_PCIE_IO_SIZE	0x00010000 /* 64KB */
+
+struct imx6pcie_ih {
+	int (*ih_handler)(void *);
+	void *ih_arg;
+	int ih_ipl;
+	TAILQ_ENTRY(imx6pcie_ih) ih_entry;
+};
+
+struct imx6pcie_softc {
+	device_t sc_dev;
+
+	bus_space_tag_t sc_iot;
+	bus_space_handle_t sc_ioh;
+	bus_space_handle_t sc_root_ioh;
+	bus_dma_tag_t sc_dmat;
+
+	struct arm32_pci_chipset sc_pc;
+
+	TAILQ_HEAD(, imx6pcie_ih) sc_intrs;
+
+	void *sc_ih;
+	kmutex_t sc_lock;
+	u_int sc_intrgen;
+
+	int32_t sc_gpio_reset;
+	int32_t sc_gpio_reset_active;
+	int32_t sc_gpio_pwren;
+	int32_t sc_gpio_pwren_active;
+};
+
+#define PCIE_CONF_LOCK(s)	(s) = disable_interrupts(I32_bit)
+#define PCIE_CONF_UNLOCK(s)	restore_interrupts((s))
+
+#define PCIE_READ(sc, reg)					\
+	bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, reg)
+#define PCIE_WRITE(sc, reg, val)				\
+	bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, reg, val)
+
+static int imx6pcie_intr(void *);
+static void imx6pcie_init(pci_chipset_tag_t, void *);
+static void imx6pcie_setup(struct imx6pcie_softc * const);
+
+static void imx6pcie_attach_hook(device_t, device_t,
+				       struct pcibus_attach_args *);
+static int imx6pcie_bus_maxdevs(void *, int);
+static pcitag_t imx6pcie_make_tag(void *, int, int, int);
+static void imx6pcie_decompose_tag(void *, pcitag_t, int *, int *, int *);
+static pcireg_t imx6pcie_conf_read(void *, pcitag_t, int);
+static void imx6pcie_conf_write(void *, pcitag_t, int, pcireg_t);
+#ifdef __HAVE_PCI_CONF_HOOK
+static int imx6pcie_conf_hook(void *, int, int, int, pcireg_t);
+#endif
+static void imx6pcie_conf_interrupt(void *, int, int, int, int, int *);
+
+static int imx6pcie_intr_map(const struct pci_attach_args *,
+				    pci_intr_handle_t *);
+static const char *imx6pcie_intr_string(void *, pci_intr_handle_t,
+					  char *, size_t);
+const struct evcnt *imx6pcie_intr_evcnt(void *, pci_intr_handle_t);
+static void * imx6pcie_intr_establish(void *, pci_intr_handle_t,
+					 int, int (*)(void *), void *);
+static void imx6pcie_intr_disestablish(void *, void *);
+
+CFATTACH_DECL_NEW(imxpcie, sizeof(struct imx6pcie_softc),
+    imx6pcie_match, imx6pcie_attach, NULL, NULL);
+
+static void
+imx6pcie_clock_enable(struct imx6pcie_softc *sc)
+{
+	uint32_t v;
+
+	v = imx6_ccm_read(CCM_ANALOG_MISC1);
+	v &= ~CCM_ANALOG_MISC1_LVDS_CLK1_IBEN;
+	v &= ~CCM_ANALOG_MISC1_LVDS_CLK1_SRC;
+	v |= CCM_ANALOG_MISC1_LVDS_CLK1_OBEN;
+	v |= CCM_ANALOG_MISC1_LVDS_CLK1_SRC_SATA;
+	imx6_ccm_write(CCM_ANALOG_MISC1, v);
+
+	/* select PCIe clock source from axi */
+	v = imx6_ccm_read(CCM_CBCMR);
+	v &= ~CCM_CBCMR_PCIE_AXI_CLK_SEL;
+	imx6_ccm_write(CCM_CBCMR, v);
+
+	/* AHCISATA clock enable */
+	v = imx6_ccm_read(CCM_CCGR5);
+	v |= CCM_CCGR5_100M_CLK_ENABLE(3);
+	imx6_ccm_write(CCM_CCGR5, v);
+
+	/* PCIe clock enable */
+	v = imx6_ccm_read(CCM_CCGR4);
+	v |= CCM_CCGR4_125M_ROOT_ENABLE(3);
+	imx6_ccm_write(CCM_CCGR4, v);
+
+	/* PLL power up */
+	if (imx6_pll_power(CCM_ANALOG_PLL_ENET, 1,
+		CCM_ANALOG_PLL_ENET_ENABLE_125M |
+		CCM_ANALOG_PLL_ENET_ENABLE_100M) != 0) {
+		aprint_error_dev(sc->sc_dev,
+		    "couldn't enable CCM_ANALOG_PLL_ENET\n");
+		return;
+	}
+}
+
+static int
+imx6pcie_init_phy(struct imx6pcie_softc *sc)
+{
+	uint32_t v;
+
+	/* initialize IOMUX */
+	v = iomux_read(IOMUX_GPR12);
+	v &= ~IOMUX_GPR12_APP_LTSSM_ENABLE;
+	iomux_write(IOMUX_GPR12, v);
+
+	v &= ~IOMUX_GPR12_DEVICE_TYPE;
+	v |= IOMUX_GPR12_DEVICE_TYPE_PCIE_RC;
+	iomux_write(IOMUX_GPR12, v);
+
+	v &= ~IOMUX_GPR12_LOS_LEVEL;
+	v |= __SHIFTIN(9, IOMUX_GPR12_LOS_LEVEL);
+	iomux_write(IOMUX_GPR12, v);
+
+	v = 0;
+	v |= __SHIFTIN(0x7f, IOMUX_GPR8_PCS_TX_SWING_LOW);
+	v |= __SHIFTIN(0x7f, IOMUX_GPR8_PCS_TX_SWING_FULL);
+	v |= __SHIFTIN(20, IOMUX_GPR8_PCS_TX_DEEMPH_GEN2_6DB);
+	v |= __SHIFTIN(0, IOMUX_GPR8_PCS_TX_DEEMPH_GEN2_3P5DB);
+	v |= __SHIFTIN(0, IOMUX_GPR8_PCS_TX_DEEMPH_GEN1);
+	iomux_write(IOMUX_GPR8, v);
+
+	return 0;
+}
+
+static int
+imx6pcie_phy_wait_ack(struct imx6pcie_softc *sc, int ack)
+{
+	uint32_t v;
+	int timeout;
+
+	for (timeout = 10; timeout > 0; --timeout) {
+		v = PCIE_READ(sc, PCIE_PL_PHY_STATUS);
+		if (!!(v & PCIE_PL_PHY_STATUS_ACK) == !!ack)
+			return 0;
+		delay(1);
+	}
+
+	return -1;
+}
+
+static int
+imx6pcie_phy_addr(struct imx6pcie_softc *sc, uint32_t addr)
+{
+	uint32_t v;
+
+	v = __SHIFTIN(addr, PCIE_PL_PHY_CTRL_DATA);
+	PCIE_WRITE(sc, PCIE_PL_PHY_CTRL, v);
+
+	v |= PCIE_PL_PHY_CTRL_CAP_ADR;
+	PCIE_WRITE(sc, PCIE_PL_PHY_CTRL, v);
+
+	if (imx6pcie_phy_wait_ack(sc, 1))
+		return -1;
+
+	v = __SHIFTIN(addr, PCIE_PL_PHY_CTRL_DATA);
+	PCIE_WRITE(sc, PCIE_PL_PHY_CTRL, v);
+
+	if (imx6pcie_phy_wait_ack(sc, 0))
+		return -1;
+
+	return 0;
+}
+
+static int
+imx6pcie_phy_write(struct imx6pcie_softc *sc, uint32_t addr, uint16_t data)
+{
+	/* write address */
+	if (imx6pcie_phy_addr(sc, addr) != 0)
+		return -1;
+
+	/* store data */
+	PCIE_WRITE(sc, PCIE_PL_PHY_CTRL, __SHIFTIN(data, PCIE_PL_PHY_CTRL_DATA));
+
+	/* assert CAP_DAT and wait ack */
+	PCIE_WRITE(sc, PCIE_PL_PHY_CTRL, __SHIFTIN(data, PCIE_PL_PHY_CTRL_DATA) | PCIE_PL_PHY_CTRL_CAP_DAT);
+	if (imx6pcie_phy_wait_ack(sc, 1))
+		return -1;
+
+	/* deassert CAP_DAT and wait ack */
+	PCIE_WRITE(sc, PCIE_PL_PHY_CTRL, __SHIFTIN(data, PCIE_PL_PHY_CTRL_DATA));
+	if (imx6pcie_phy_wait_ack(sc, 0))
+		return -1;
+
+	/* assert WR and wait ack */
+	PCIE_WRITE(sc, PCIE_PL_PHY_CTRL, PCIE_PL_PHY_CTRL_WR);
+	if (imx6pcie_phy_wait_ack(sc, 1))
+		return -1;
+
+	/* deassert WR and wait ack */
+	PCIE_WRITE(sc, PCIE_PL_PHY_CTRL, __SHIFTIN(data, PCIE_PL_PHY_CTRL_DATA));
+	if (imx6pcie_phy_wait_ack(sc, 0))
+		return -1;
+
+	/* done */
+	PCIE_WRITE(sc, PCIE_PL_PHY_CTRL, 0);
+
+	return 0;
+}
+
+static int
+imx6pcie_phy_read(struct imx6pcie_softc *sc, uint32_t addr)
+{
+	uint32_t v;
+
+	/* write address */
+	if (imx6pcie_phy_addr(sc, addr) != 0)
+		return -1;
+
+	/* assert RD */
+	PCIE_WRITE(sc, PCIE_PL_PHY_CTRL, PCIE_PL_PHY_CTRL_RD);
+	if (imx6pcie_phy_wait_ack(sc, 1))
+		return -1;
+
+	/* read data */
+	v = __SHIFTOUT(PCIE_READ(sc, PCIE_PL_PHY_STATUS),
+	    PCIE_PL_PHY_STATUS_DATA);
+
+	/* deassert RD */
+	PCIE_WRITE(sc, PCIE_PL_PHY_CTRL, 0);
+	if (imx6pcie_phy_wait_ack(sc, 0))
+		return -1;
+
+	return v;
+}
+
+static int
+imx6pcie_assert_core_reset(struct imx6pcie_softc *sc)
+{
+	uint32_t gpr1;
+	uint32_t gpr12;
+
+	gpr1 = iomux_read(IOMUX_GPR1);
+	gpr12 = iomux_read(IOMUX_GPR12);
+
+	/* already enabled by bootloader */
+	if ((gpr1 & IOMUX_GPR1_REF_SSP_EN) &&
+	    (gpr12 & IOMUX_GPR12_APP_LTSSM_ENABLE)) {
+		uint32_t v = PCIE_READ(sc, PCIE_PL_PFLR);
+		v &= ~PCIE_PL_PFLR_LINK_STATE;
+		v |= PCIE_PL_PFLR_FORCE_LINK;
+		PCIE_WRITE(sc, PCIE_PL_PFLR, v);
+
+		gpr12 &= ~IOMUX_GPR12_APP_LTSSM_ENABLE;
+		iomux_write(IOMUX_GPR12, gpr12);
+	}
+
+#if defined(IMX6DQP)
+	gpr1 |= IOMUX_GPR1_PCIE_SW_RST;
+	iomux_write(IOMUX_GPR1, gpr1);
+#endif
+
+	gpr1 |= IOMUX_GPR1_TEST_POWERDOWN;
+	iomux_write(IOMUX_GPR1, gpr1);
+	gpr1 &= ~IOMUX_GPR1_REF_SSP_EN;
+	iomux_write(IOMUX_GPR1, gpr1);
+
+	return 0;
+}
+
+static int
+imx6pcie_deassert_core_reset(struct imx6pcie_softc *sc)
+{
+	uint32_t v;
+
+	/* Power ON */
+#if NIMXGPIO > 0
+	if (sc->sc_gpio_pwren >= 0) {
+		gpio_data_write(sc->sc_gpio_pwren, sc->sc_gpio_pwren_active);
+		delay(100 * 1000);
+		gpio_data_write(sc->sc_gpio_pwren, !sc->sc_gpio_pwren_active);
+	}
+#endif
+
+	imx6pcie_clock_enable(sc);
+
+	v = iomux_read(IOMUX_GPR1);
+
+#if defined(IMX6DQP)
+	v &= ~IOMUX_GPR1_PCIE_SW_RST;
+	iomux_write(IOMUX_GPR1, v);
+#endif
+
+	delay(50 * 1000);
+
+	v &= ~IOMUX_GPR1_TEST_POWERDOWN;
+	iomux_write(IOMUX_GPR1, v);
+	delay(10);
+	v |= IOMUX_GPR1_REF_SSP_EN;
+	iomux_write(IOMUX_GPR1, v);
+
+	delay(50 * 1000);
+
+	/* Reset */
+#if NIMXGPIO > 0
+	if (sc->sc_gpio_reset >= 0) {
+		gpio_data_write(sc->sc_gpio_reset, sc->sc_gpio_reset_active);
+		delay(100 * 1000);
+		gpio_data_write(sc->sc_gpio_reset, !sc->sc_gpio_reset_active);
+	}
+#endif
+
+	return 0;
+}
+
+static int
+imx6pcie_wait_for_link(struct imx6pcie_softc *sc)
+{
+	uint32_t ltssm, valid, v;
+	uint32_t linkup;
+	int retry;
+
+#define LINKUP_RETRY	200
+	for (retry = LINKUP_RETRY; retry > 0; --retry) {
+		linkup = PCIE_READ(sc, PCIE_PL_DEBUG1);
+		if ((linkup & PCIE_PL_DEBUG1_XMLH_LINK_UP) &&
+		    !(linkup & PCIE_PL_DEBUG1_XMLH_LINK_IN_TRAINING)) {
+			delay(100);
+			continue;
+		}
+
+		valid = imx6pcie_phy_read(sc, PCIE_PHY_RX_ASIC_OUT) &
+		    PCIE_PHY_RX_ASIC_OUT_VALID;
+		ltssm = __SHIFTOUT(PCIE_READ(sc, PCIE_PL_DEBUG0),
+		    PCIE_PL_DEBUG0_XMLH_LTSSM_STATE);
+
+		if ((ltssm == 0x0d) && !valid) {
+			aprint_normal_dev(sc->sc_dev, "resetting PCIe phy\n");
+
+			v = imx6pcie_phy_read(sc, PCIE_PHY_RX_OVRD_IN_LO);
+			v |= PCIE_PHY_RX_OVRD_IN_LO_RX_PLL_EN_OVRD;
+			v |= PCIE_PHY_RX_OVRD_IN_LO_RX_DATA_EN_OVRD;
+			imx6pcie_phy_write(sc, PCIE_PHY_RX_OVRD_IN_LO, v);
+
+			delay(3000);
+
+			v = imx6pcie_phy_read(sc, PCIE_PHY_RX_OVRD_IN_LO);
+			v &= ~PCIE_PHY_RX_OVRD_IN_LO_RX_PLL_EN_OVRD;
+			v &= ~PCIE_PHY_RX_OVRD_IN_LO_RX_DATA_EN_OVRD;
+			imx6pcie_phy_write(sc, PCIE_PHY_RX_OVRD_IN_LO, v);
+		}
+
+		if (linkup)
+			return 0;
+	}
+
+	aprint_error_dev(sc->sc_dev, "Link Up failed.\n");
+
+	return -1;
+}
+
+static int
+imx6pcie_wait_for_changespeed(struct imx6pcie_softc *sc)
+{
+	uint32_t v;
+	int retry;
+
+#define CHANGESPEED_RETRY	200
+	for (retry = CHANGESPEED_RETRY; retry > 0; --retry) {
+		v = PCIE_READ(sc, PCIE_PL_G2CR);
+		if (!(v & PCIE_PL_G2CR_DIRECTED_SPEED_CHANGE))
+			return 0;
+		delay(100);
+	}
+
+	aprint_error_dev(sc->sc_dev, "Speed change timeout.\n");
+
+	return -1;
+}
+
+static void
+imx6pcie_linkup(struct imx6pcie_softc *sc)
+{
+	uint32_t v;
+	int ret;
+
+	imx6pcie_assert_core_reset(sc);
+	imx6pcie_init_phy(sc);
+	imx6pcie_deassert_core_reset(sc);
+
+	imx6pcie_setup(sc);
+
+	/* GEN1 Operation */
+	v = PCIE_READ(sc, PCIE_RC_LCR);
+	v &= ~PCIE_RC_LCR_MAX_LINK_SPEEDS;
+	v |= PCIE_RC_LCR_MAX_LINK_SPEEDS_GEN1;
+	PCIE_WRITE(sc, PCIE_RC_LCR, v);
+
+	/* Link Up */
+	v = iomux_read(IOMUX_GPR12);
+	v |= IOMUX_GPR12_APP_LTSSM_ENABLE;
+	iomux_write(IOMUX_GPR12, v);
+
+	ret = imx6pcie_wait_for_link(sc);
+	if (ret)
+		goto error;
+
+	/* Change speed */
+	v = PCIE_READ(sc, PCIE_PL_G2CR);
+	v |= PCIE_PL_G2CR_DIRECTED_SPEED_CHANGE;
+	PCIE_WRITE(sc, PCIE_PL_G2CR, v);
+
+	ret = imx6pcie_wait_for_changespeed(sc);
+	if (ret)
+		goto error;
+
+	/* Allow Gen2 mode */
+	v = PCIE_READ(sc, PCIE_RC_LCR);
+	v &= ~PCIE_RC_LCR_MAX_LINK_SPEEDS;
+	v |= PCIE_RC_LCR_MAX_LINK_SPEEDS_GEN2;
+	PCIE_WRITE(sc, PCIE_RC_LCR, v);
+
+	ret = imx6pcie_wait_for_link(sc);
+	if (ret)
+		goto error;
+
+	v = PCIE_READ(sc, PCIE_RC_LCSR);
+	aprint_normal_dev(sc->sc_dev, "LinkUp, Gen %d\n",
+	    (int)__SHIFTOUT(v, PCIE_RC_LCSR_LINK_SPEED));
+
+	return;
+
+error:
+	aprint_error_dev(sc->sc_dev,
+	    "PCIE_PL_DEBUG0,1 = %08x, %08x\n",
+	    PCIE_READ(sc, PCIE_PL_DEBUG0),
+	    PCIE_READ(sc, PCIE_PL_DEBUG1));
+
+	return;
+}
+
+static int
+imx6pcie_match(device_t parent, cfdata_t cf, void *aux)
+{
+	struct axi_attach_args * const aa = aux;
+
+	/* i.MX6 SoloLite has no PCIe controller */
+	switch (IMX6_CHIPID_MAJOR(imx6_chip_id())) {
+	case CHIPID_MAJOR_IMX6SL:
+		return 0;
+	default:
+		break;
+	}
+
+	switch (aa->aa_addr) {
+	case (IMX6_PCIE_BASE):
+		return 1;
+	}
+
+	return 0;
+}
+
+static void
+imx6pcie_attach(device_t parent, device_t self, void *aux)
+{
+	struct imx6pcie_softc * const sc = device_private(self);
+	struct axi_attach_args * const aa = aux;
+	struct pcibus_attach_args pba;
+
+	sc->sc_dev = self;
+	sc->sc_iot = aa->aa_iot;
+	sc->sc_dmat = aa->aa_dmat;
+
+	if (aa->aa_size == AXICF_SIZE_DEFAULT)
+		aa->aa_size = IMX6_PCIE_SIZE;
+
+	aprint_naive("\n");
+	aprint_normal(": PCI Express Controller\n");
+
+	if (bus_space_map(sc->sc_iot, aa->aa_addr, aa->aa_size, 0,
+	    &sc->sc_ioh)) {
+		aprint_error_dev(self, "Cannot map registers\n");
+		return;
+	}
+	if (bus_space_map(sc->sc_iot, IMX6_PCIE_ROOT_BASE,
+	    IMX6_PCIE_ROOT_SIZE, 0, &sc->sc_root_ioh)) {
+		aprint_error_dev(self, "Cannot map registers\n");
+		return;
+	}
+
+	imx6_set_gpio(self, "imx6pcie-reset-gpio", &sc->sc_gpio_reset,
+	    &sc->sc_gpio_reset_active, GPIO_DIR_OUT);
+	imx6_set_gpio(self, "imx6pcie-pwren-gpio", &sc->sc_gpio_pwren,
+	    &sc->sc_gpio_pwren_active, GPIO_DIR_OUT);
+
+	imx6pcie_linkup(sc);
+
+	TAILQ_INIT(&sc->sc_intrs);
+	mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_VM);
+
+	sc->sc_ih = intr_establish(aa->aa_irq, IPL_VM, IST_LEVEL,
+	    imx6pcie_intr, sc);
+	if (sc->sc_ih == NULL) {
+		aprint_error_dev(self, "failed to establish interrupt on %d\n",
+		    aa->aa_irq);
+		return;
+	}
+	aprint_normal_dev(self, "interrupting on %d\n", aa->aa_irq);
+
+	imx6pcie_init(&sc->sc_pc, sc);
+
+#ifdef PCI_NETBSD_CONFIGURE
+	struct extent *ioext, *memext;
+	int error;
+
+	ioext = extent_create("pciio", IMX6_PCIE_IO_BASE,
+	    IMX6_PCIE_IO_BASE + IMX6_PCIE_IO_SIZE - 1,
+	    NULL, 0, EX_NOWAIT);
+	memext = extent_create("pcimem", IMX6_PCIE_MEM_BASE,
+	    IMX6_PCIE_MEM_BASE + IMX6_PCIE_MEM_SIZE - 1,
+	    NULL, 0, EX_NOWAIT);
+
+	error = pci_configure_bus(&sc->sc_pc, ioext, memext, NULL, 0,
+	    arm_dcache_align);
+
+	extent_destroy(ioext);
+	extent_destroy(memext);
+
+	if (error) {
+		aprint_error_dev(self, "configuration failed (%d)\n",
+		    error);
+		return;
+	}
+#endif
+
+	memset(&pba, 0, sizeof(pba));
+	pba.pba_flags = PCI_FLAGS_MEM_OKAY |
+			PCI_FLAGS_IO_OKAY;
+	pba.pba_iot = sc->sc_iot;
+	pba.pba_memt = sc->sc_iot;
+	pba.pba_dmat = sc->sc_dmat;
+	pba.pba_pc = &sc->sc_pc;
+	pba.pba_bus = 0;
+
+	config_found_ia(self, "pcibus", &pba, pcibusprint);
+}
+
+static int
+imx6pcie_intr(void *priv)
+{
+	struct imx6pcie_softc *sc = priv;
+	struct imx6pcie_ih *pcie_ih;
+	int rv = 0;
+	uint32_t v;
+
+	for (int i = 0; i < 8; i++) {
+		v = PCIE_READ(sc, PCIE_PL_MSICIN_STATUS + i * 0xC);
+		int bit;
+		while ((bit = ffs(v) - 1) >= 0) {
+			PCIE_WRITE(sc, PCIE_PL_MSICIN_STATUS + i * 0xC,
+			    __BIT(bit));
+			v &= ~__BIT(bit);
+		}
+	}
+
+	mutex_enter(&sc->sc_lock);
+	const u_int lastgen = sc->sc_intrgen;
+	TAILQ_FOREACH(pcie_ih, &sc->sc_intrs, ih_entry) {
+		int (*callback)(void *) = pcie_ih->ih_handler;
+		void *arg = pcie_ih->ih_arg;
+		mutex_exit(&sc->sc_lock);
+		rv += callback(arg);
+		mutex_enter(&sc->sc_lock);
+		if (lastgen != sc->sc_intrgen)
+			break;
+	}
+	mutex_exit(&sc->sc_lock);
+
+	return rv;
+}
+
+static void
+imx6pcie_setup(struct imx6pcie_softc * const sc)
+{
+	uint32_t v;
+
+	/* Setup RC */
+
+	/* BARs */
+	PCIE_WRITE(sc, PCI_BAR0, 0x00000004);
+	PCIE_WRITE(sc, PCI_BAR1, 0x00000000);
+
+	/* Interurupt pins */
+	v = PCIE_READ(sc, PCI_INTERRUPT_REG);
+	v &= ~(PCI_INTERRUPT_PIN_MASK << PCI_INTERRUPT_PIN_SHIFT);
+	v |= PCI_INTERRUPT_PIN_A << PCI_INTERRUPT_PIN_SHIFT;
+	PCIE_WRITE(sc, PCI_INTERRUPT_REG, v);
+
+	/* Bus number */
+	v = PCIE_READ(sc, PCI_BRIDGE_BUS_REG);
+	v &= ~(PCI_BRIDGE_BUS_EACH_MASK << PCI_BRIDGE_BUS_SUBORDINATE_SHIFT |
+	    PCI_BRIDGE_BUS_EACH_MASK << PCI_BRIDGE_BUS_SECONDARY_SHIFT |
+	    PCI_BRIDGE_BUS_EACH_MASK << PCI_BRIDGE_BUS_PRIMARY_SHIFT);
+	v |= PCI_BRIDGE_BUS_SUBORDINATE(1);
+	v |= PCI_BRIDGE_BUS_SECONDARY(1);
+	v |= PCI_BRIDGE_BUS_PRIMARY(0);
+	PCIE_WRITE(sc, PCI_BRIDGE_BUS_REG, v);
+
+	/* Command register */
+	v = PCIE_READ(sc, PCI_COMMAND_STATUS_REG);
+	v |= PCI_COMMAND_IO_ENABLE |
+	    PCI_COMMAND_MEM_ENABLE |
+	    PCI_COMMAND_MASTER_ENABLE;
+	PCIE_WRITE(sc, PCI_COMMAND_STATUS_REG, v);
+
+	PCIE_WRITE(sc, PCI_CLASS_REG,
+	    PCI_CLASS_CODE(PCI_CLASS_BRIDGE, PCI_SUBCLASS_BRIDGE_PCI, PCI_INTERFACE_BRIDGE_PCI_PCI));
+
+	PCIE_WRITE(sc, PCIE_PL_IATUVR, 0);
+
+	PCIE_WRITE(sc, PCIE_PL_IATURLBA, IMX6_PCIE_ROOT_BASE);
+	PCIE_WRITE(sc, PCIE_PL_IATURUBA, 0);
+	PCIE_WRITE(sc, PCIE_PL_IATURLA, IMX6_PCIE_ROOT_BASE + IMX6_PCIE_ROOT_SIZE);
+
+	PCIE_WRITE(sc, PCIE_PL_IATURLTA, 0);
+	PCIE_WRITE(sc, PCIE_PL_IATURUTA, 0);
+	PCIE_WRITE(sc, PCIE_PL_IATURC1, PCIE_PL_IATURC1_TYPE_CFG0);
+	PCIE_WRITE(sc, PCIE_PL_IATURC2, PCIE_PL_IATURC2_REGION_ENABLE);
+}
+
+void
+imx6pcie_init(pci_chipset_tag_t pc, void *priv)
+{
+	pc->pc_conf_v = priv;
+	pc->pc_attach_hook = imx6pcie_attach_hook;
+	pc->pc_bus_maxdevs = imx6pcie_bus_maxdevs;
+	pc->pc_make_tag = imx6pcie_make_tag;
+	pc->pc_decompose_tag = imx6pcie_decompose_tag;
+	pc->pc_conf_read = imx6pcie_conf_read;
+	pc->pc_conf_write = imx6pcie_conf_write;
+#ifdef __HAVE_PCI_CONF_HOOK
+	pc->pc_conf_hook = imx6pcie_conf_hook;
+#endif
+	pc->pc_conf_interrupt = imx6pcie_conf_interrupt;
+
+	pc->pc_intr_v = priv;
+	pc->pc_intr_map = imx6pcie_intr_map;
+	pc->pc_intr_string = imx6pcie_intr_string;
+	pc->pc_intr_evcnt = imx6pcie_intr_evcnt;
+	pc->pc_intr_establish = imx6pcie_intr_establish;
+	pc->pc_intr_disestablish = imx6pcie_intr_disestablish;
+}
+
+static void
+imx6pcie_attach_hook(device_t parent, device_t self,
+    struct pcibus_attach_args *pba)
+{
+	/* nothing to do */
+}
+
+static int
+imx6pcie_bus_maxdevs(void *v, int busno)
+{
+	return 32;
+}
+
+static pcitag_t
+imx6pcie_make_tag(void *v, int b, int d, int f)
+{
+	return (b << 16) | (d << 11) | (f << 8);
+}
+
+static void
+imx6pcie_decompose_tag(void *v, pcitag_t tag, int *bp, int *dp, int *fp)
+{
+	if (bp)
+		*bp = (tag >> 16) & 0xff;
+	if (dp)
+		*dp = (tag >> 11) & 0x1f;
+	if (fp)
+		*fp = (tag >> 8) & 0x7;
+}
+
+/*
+ * work around.
+ * If there is no PCIe devices, DABT will be generated by read/write access to
+ * config area, so replace original DABT handler with simple jump-back one.
+ */
+extern u_int data_abort_handler_address;
+static bool data_abort_flag;
+static void
+imx6pcie_data_abort_handler(trapframe_t *tf)
+{
+	data_abort_flag = true;
+	tf->tf_pc += 0x4;
+	return;
+}
+
+static pcireg_t
+imx6pcie_conf_read(void *v, pcitag_t tag, int offset)
+{
+	struct imx6pcie_softc *sc = v;
+	bus_space_handle_t bsh;
+	int b, d, f;
+	pcireg_t ret = -1;
+	int s;
+
+	imx6pcie_decompose_tag(v, tag, &b, &d, &f);
+
+	if ((unsigned int)offset >= PCI_EXTCONF_SIZE)
+		return ret;
+	if (b <= 1 && d > 0)
+		return ret;
+
+	PCIE_WRITE(sc, PCIE_PL_IATUVR, 0);
+	if (b < 2)
+		PCIE_WRITE(sc, PCIE_PL_IATURC1, PCIE_PL_IATURC1_TYPE_CFG0);
+	else
+		PCIE_WRITE(sc, PCIE_PL_IATURC1, PCIE_PL_IATURC1_TYPE_CFG1);
+
+	if (b == 0) {
+		bsh = sc->sc_ioh;
+	} else {
+		PCIE_WRITE(sc, PCIE_PL_IATURLTA, tag << 8);
+		bsh = sc->sc_root_ioh;
+	}
+	PCIE_READ(sc, PCIE_PL_IATURC2);
+
+	PCIE_CONF_LOCK(s);
+
+	u_int saved = data_abort_handler_address;
+	data_abort_handler_address = (u_int)imx6pcie_data_abort_handler;
+	data_abort_flag = false;
+
+	ret = bus_space_read_4(sc->sc_iot, bsh, offset & ~0x3);
+
+	data_abort_handler_address = saved;
+
+	PCIE_CONF_UNLOCK(s);
+
+	if (data_abort_flag)
+		ret = -1;
+
+	return ret;
+}
+
+static void
+imx6pcie_conf_write(void *v, pcitag_t tag, int offset, pcireg_t val)
+{
+	struct imx6pcie_softc *sc = v;
+	bus_space_handle_t bsh;
+	int b, d, f;
+	int s;
+
+	imx6pcie_decompose_tag(v, tag, &b, &d, &f);
+
+	if ((unsigned int)offset >= PCI_EXTCONF_SIZE)
+		return;
+	if (b <= 1 && d > 0)
+		return;
+
+	PCIE_WRITE(sc, PCIE_PL_IATUVR, 0);
+	if (b < 2)
+		PCIE_WRITE(sc, PCIE_PL_IATURC1, PCIE_PL_IATURC1_TYPE_CFG0);
+	else
+		PCIE_WRITE(sc, PCIE_PL_IATURC1, PCIE_PL_IATURC1_TYPE_CFG1);
+
+	if (b == 0) {
+		bsh = sc->sc_ioh;
+	} else {
+		PCIE_WRITE(sc, PCIE_PL_IATURLTA, tag << 8);
+		bsh = sc->sc_root_ioh;
+	}
+	PCIE_READ(sc, PCIE_PL_IATURC2);
+
+	PCIE_CONF_LOCK(s);
+
+	u_int saved = data_abort_handler_address;
+	data_abort_handler_address = (u_int)imx6pcie_data_abort_handler;
+
+	bus_space_write_4(sc->sc_iot, bsh, offset & ~0x3, val);
+
+	data_abort_handler_address = saved;
+
+	PCIE_CONF_UNLOCK(s);
+
+	return;
+}
+
+#ifdef __HAVE_PCI_CONF_HOOK
+static int
+imx6pcie_conf_hook(void *v, int b, int d, int f, pcireg_t id)
+{
+	return PCI_CONF_DEFAULT;
+}
+#endif
+
+static void
+imx6pcie_conf_interrupt(void *v, int bus, int dev, int ipin, int swiz,
+    int *ilinep)
+{
+	/* nothing to do */
+}
+
+static int
+imx6pcie_intr_map(const struct pci_attach_args *pa, pci_intr_handle_t *ih)
+{
+	if (pa->pa_intrpin == 0)
+		return EINVAL;
+	*ih = pa->pa_intrpin;
+	return 0;
+}
+
+static const char *
+imx6pcie_intr_string(void *v, pci_intr_handle_t ih, char *buf, size_t len)
+{
+	if (ih == PCI_INTERRUPT_PIN_NONE)
+		return NULL;
+
+	strlcpy(buf, "pci", len);
+
+	return buf;
+}
+
+const struct evcnt *
+imx6pcie_intr_evcnt(void *v, pci_intr_handle_t ih)
+{
+	return NULL;
+}
+
+static void *
+imx6pcie_intr_establish(void *v, pci_intr_handle_t ih, int ipl,
+    int (*callback)(void *), void *arg)
+{
+	struct imx6pcie_softc *sc = v;
+	struct imx6pcie_ih *pcie_ih;
+
+	if (ih == 0)
+		return NULL;
+
+	pcie_ih = kmem_alloc(sizeof(*pcie_ih), KM_SLEEP);
+	pcie_ih->ih_handler = callback;
+	pcie_ih->ih_arg = arg;
+	pcie_ih->ih_ipl = ipl;
+
+	mutex_enter(&sc->sc_lock);
+	TAILQ_INSERT_TAIL(&sc->sc_intrs, pcie_ih, ih_entry);
+	sc->sc_intrgen++;
+	mutex_exit(&sc->sc_lock);
+
+	return pcie_ih;
+}
+
+static void
+imx6pcie_intr_disestablish(void *v, void *vih)
+{
+	struct imx6pcie_softc *sc = v;
+	struct imx6pcie_ih *pcie_ih = vih;
+
+	mutex_enter(&sc->sc_lock);
+	TAILQ_REMOVE(&sc->sc_intrs, pcie_ih, ih_entry);
+	sc->sc_intrgen++;
+	mutex_exit(&sc->sc_lock);
+
+	kmem_free(pcie_ih, sizeof(*pcie_ih));
+}
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/sys/arch/arm/imx/imx6_pciereg.h	Mon Dec 05 10:54:48 2016 +0000
@@ -0,0 +1,295 @@
+/*	$NetBSD: imx6_pciereg.h,v 1.1.2.2 2016/12/05 10:54:50 skrll Exp $	*/
+
+/*
+ * Copyright (c) 2015 Ryo Shimizu <ryo@nerv.org>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _ARM_IMX_IMX6_PCIEREG_H_
+#define _ARM_IMX_IMX6_PCIEREG_H_
+
+/* PCIe EP Mode Registers */
+#define PCIE_EP_DEVICEID			0x00000000
+#define PCIE_EP_COMMAND				0x00000004
+#define PCIE_EP_BIST				0x0000000c
+#define PCIE_EP_BAR0				0x00000010
+#define PCIE_EP_MASK0				0x00000010
+#define PCIE_EP_MASK1				0x00000014
+#define PCIE_EP_MASK2				0x00000018
+#define PCIE_EP_MASK3				0x0000001c
+#define PCIE_EP_CISP				0x00000028
+#define PCIE_EP_SSID				0x0000002c
+#define PCIE_EP_EROMBAR				0x00000030
+#define PCIE_EP_EROMMASK			0x00000030
+#define PCIE_EP_CAPPR				0x00000034
+#define PCIE_EP_ILR				0x0000003c
+#define PCIE_EP_AER				0x00000100
+#define PCIE_EP_UESR				0x00000104
+#define PCIE_EP_UEMR				0x00000108
+#define PCIE_EP_UESEVR				0x0000010c
+#define PCIE_EP_CESR				0x00000110
+#define PCIE_EP_CEMR				0x00000114
+#define PCIE_EP_ACCR				0x00000118
+#define PCIE_EP_HLR				0x0000011c
+#define PCIE_EP_VCECHR				0x00000140
+#define PCIE_EP_PVCCR1				0x00000144
+#define PCIE_EP_PVCCR2				0x00000148
+#define PCIE_EP_PVCCSR				0x0000014c
+#define PCIE_EP_VCRCR				0x00000150
+#define PCIE_EP_VCRCONR				0x00000154
+#define PCIE_EP_VCRSR				0x00000158
+
+/* PCIe RC Mode Registers */
+#define PCIE_RC_DEVICEID			0x00000000
+#define PCIE_RC_COMMAND				0x00000004
+#define PCIE_RC_REVID				0x00000008
+#define PCIE_RC_BIST				0x0000000c
+#define PCIE_RC_BAR0				0x00000010
+#define PCIE_RC_BAR1				0x00000014
+#define PCIE_RC_BNR				0x00000018
+#define PCIE_RC_IOBLSSR				0x0000001c
+#define PCIE_RC_MEM_BLR				0x00000020
+#define PCIE_RC_PREF_MEM_BLR			0x00000024
+#define PCIE_RC_PREF_BASE_U32			0x00000028
+#define PCIE_RC_PREF_LIM_U32			0x0000002c
+#define PCIE_RC_IO_BASE_LIM_U16			0x00000030
+#define PCIE_RC_CAPPR				0x00000034
+#define PCIE_RC_EROMBAR				0x00000038
+#define PCIE_RC_EROMMASK			0x00000038
+#define PCIE_RC_PMCR				0x00000040
+#define PCIE_RC_PMCSR				0x00000044
+#define PCIE_RC_CIDR				0x00000070
+#define PCIE_RC_DCR				0x00000074
+#define PCIE_RC_DCONR				0x00000078
+#define PCIE_RC_LCR				0x0000007c
+#define  PCIE_RC_LCR_MAX_LINK_SPEEDS		__BITS(3, 0)
+#define  PCIE_RC_LCR_MAX_LINK_SPEEDS_GEN1	__SHIFTIN(0x1, PCIE_RC_LCR_MAX_LINK_SPEEDS)
+#define  PCIE_RC_LCR_MAX_LINK_SPEEDS_GEN2	__SHIFTIN(0x2, PCIE_RC_LCR_MAX_LINK_SPEEDS)
+#define PCIE_RC_LCSR				0x00000080
+#define  PCIE_RC_LCSR_LINK_SPEED		__BITS(19, 16)
+#define PCIE_RC_SCR				0x00000084
+#define PCIE_RC_SCSR				0x00000088
+#define PCIE_RC_RCCR				0x0000008c
+#define PCIE_RC_RSR				0x00000090
+#define PCIE_RC_DCR2				0x00000094
+#define PCIE_RC_DCSR2				0x00000098
+#define PCIE_RC_LCR2				0x0000009c
+#define PCIE_RC_LCSR2				0x000000a0
+#define PCIE_RC_AER				0x00000100
+#define PCIE_RC_UESR				0x00000104
+#define PCIE_RC_UEMR				0x00000108
+#define PCIE_RC_UESEVR				0x0000010c
+#define PCIE_RC_CESR				0x00000110
+#define PCIE_RC_CEMR				0x00000114
+#define PCIE_RC_ACCR				0x00000118
+#define PCIE_RC_HLR				0x0000011c
+#define PCIE_RC_RECR				0x0000012c
+#define PCIE_RC_RESR				0x00000130
+#define PCIE_RC_ESIR				0x00000134
+#define PCIE_RC_VCECHR				0x00000140
+#define PCIE_RC_PVCCR1				0x00000144
+#define PCIE_RC_PVCCR2				0x00000148
+#define PCIE_RC_PVCCSR				0x0000014c
+#define PCIE_RC_VCRCR				0x00000150
+#define PCIE_RC_VCRCONR				0x00000154
+#define PCIE_RC_VCRSR				0x00000158
+
+/* PCIe Port Logic Registers */
+#define PCIE_PL_ALTRTR				0x00000700
+#define PCIE_PL_VSDR				0x00000704
+#define PCIE_PL_PFLR				0x00000708
+#define  PCIE_PL_PFLR_LOW_POWER_ENTRANCE_COUNT	__BITS(31, 24)
+#define  PCIE_PL_PFLR_LINK_STATE		__BITS(21, 16)
+#define  PCIE_PL_PFLR_FORCE_LINK		__BIT(15)
+#define  PCIE_PL_PFLR_LINK_NUMBER		__BITS(7, 0)
+#define PCIE_PL_AFLACR				0x0000070c
+#define PCIE_PL_PLCR				0x00000710
+#define PCIE_PL_LSR				0x00000714
+#define PCIE_PL_SNR				0x00000718
+#define PCIE_PL_STRFM1				0x0000071c
+#define PCIE_PL_STRFM2				0x00000720
+#define PCIE_PL_AMODNPSR			0x00000724
+#define PCIE_PL_DEBUG0				0x00000728
+#define  PCIE_PL_DEBUG0_XMLH_LTSSM_STATE	__BITS(0, 5)
+#define PCIE_PL_DEBUG1				0x0000072c
+#define  PCIE_PL_DEBUG1_XMLH_LINK_UP		__BIT(4)
+#define  PCIE_PL_DEBUG1_XMLH_LINK_IN_TRAINING	__BIT(29)
+#define PCIE_PL_TPFCSR				0x00000730
+#define PCIE_PL_TNFCSR				0x00000734
+#define PCIE_PL_TCFCSR				0x00000738
+#define PCIE_PL_QSR				0x0000073c
+#define PCIE_PL_VCTAR1				0x00000740
+#define PCIE_PL_VCTAR2				0x00000744
+#define PCIE_PL_VC0PRQC				0x00000748
+#define PCIE_PL_VC0NRQC				0x0000074c
+#define PCIE_PL_VC0CRQC				0x00000750
+#define PCIE_PL_VCNPRQC				0x00000754
+#define PCIE_PL_VCNNRQC				0x00000758
+#define PCIE_PL_VCNCRQC				0x0000075c
+#define PCIE_PL_VC0PBD				0x000007a8
+#define PCIE_PL_VC0NPBD				0x000007ac
+#define PCIE_PL_VC0CBD				0x000007b0
+#define PCIE_PL_VC1PBD				0x000007b4
+#define PCIE_PL_VC1NPBD				0x000007b8
+#define PCIE_PL_VC1CBD				0x000007bc
+#define PCIE_PL_G2CR				0x0000080c
+#define  PCIE_PL_G2CR_DIRECTED_SPEED_CHANGE	__BIT(17)
+#define PCIE_PL_PHY_STATUS			0x00000810
+#define  PCIE_PL_PHY_STATUS_ACK			__BIT(16)
+#define  PCIE_PL_PHY_STATUS_DATA		__BITS(0, 15)
+#define PCIE_PL_PHY_CTRL			0x00000814
+#define  PCIE_PL_PHY_CTRL_RD			__BIT(19)
+#define  PCIE_PL_PHY_CTRL_WR			__BIT(18)
+#define  PCIE_PL_PHY_CTRL_CAP_DAT		__BIT(17)
+#define  PCIE_PL_PHY_CTRL_CAP_ADR		__BIT(16)
+#define  PCIE_PL_PHY_CTRL_DATA			__BITS(0, 15)
+#define PCIE_PL_MRCCR0				0x00000818
+#define PCIE_PL_MRCCR1				0x0000081c
+#define PCIE_PL_MSICA				0x00000820
+#define PCIE_PL_MSICUA				0x00000824
+#define PCIE_PL_MSICIN_ENB			0x00000828
+#define PCIE_PL_MSICIN_MASK			0x0000082c
+#define PCIE_PL_MSICIN_STATUS			0x00000830
+#define PCIE_PL_MSICGPIO			0x00000888
+
+// ATU_R_BaseAddress 0x900
+#define PCIE_PL_IATUVR				0x00000900
+// ATU_VIEWPORT_R (ATU_R_BaseAddress + 0x0)
+
+#define PCIE_PL_IATURC1				0x00000904
+// ATU_REGION_CTRL1_R (ATU_R_BaseAddress + 0x4)
+#define  PCIE_PL_IATURC1_FUNC			__BITS(22, 20)
+#define  PCIE_PL_IATURC1_AT			__BITS(17, 16)
+#define  PCIE_PL_IATURC1_ATTR			__BITS(10, 9)
+#define  PCIE_PL_IATURC1_TD			__BIT(8)
+#define  PCIE_PL_IATURC1_TC			__BITS(7, 5)
+#define  PCIE_PL_IATURC1_TYPE			__BITS(4, 0)
+#define   PCIE_PL_IATURC1_TYPE_IO		__SHIFTIN(0, PCIE_PL_IATURC1_TYPE)
+#define   PCIE_PL_IATURC1_TYPE_MEM		__SHIFTIN(2, PCIE_PL_IATURC1_TYPE)
+#define   PCIE_PL_IATURC1_TYPE_CFG0		__SHIFTIN(4, PCIE_PL_IATURC1_TYPE)
+#define   PCIE_PL_IATURC1_TYPE_CFG1		__SHIFTIN(5, PCIE_PL_IATURC1_TYPE)
+
+#define PCIE_PL_IATURC2				0x00000908
+// ATU_REGION_CTRL2_R (ATU_R_BaseAddress + 0x8)
+#define  PCIE_PL_IATURC2_REGION_ENABLE		__BIT(31)
+
+#define PCIE_PL_IATURLBA			0x0000090c
+// ATU_REGION_LOWBASE_R (ATU_R_BaseAddress + 0xC)
+
+#define PCIE_PL_IATURUBA			0x00000910
+// ATU_REGION_UPBASE_R (ATU_R_BaseAddress + 0x10)
+
+#define PCIE_PL_IATURLA				0x00000914
+// ATU_REGION_LIMIT_ADDR_R (ATU_R_BaseAddress + 0x14)
+
+#define PCIE_PL_IATURLTA			0x00000918
+// ATU_REGION_LOW_TRGT_ADDR_R (ATU_R_BaseAddress + 0x18)
+
+#define PCIE_PL_IATURUTA			0x0000091c
+// ATU_REGION_UP_TRGT_ADDR_R (ATU_R_BaseAddress + 0x1C)
+
+/* PCIe PHY registers */
+#define PCIE_PHY_IDCODE_LO			0x0000
+#define PCIE_PHY_IDCODE_HI			0x0001
+#define PCIE_PHY_DEBUG				0x0002
+#define PCIE_PHY_RTUNE_DEBUG			0x0003
+#define PCIE_PHY_RTUNE_STAT			0x0004
+#define PCIE_PHY_SS_PHASE			0x0005
+#define PCIE_PHY_SS_FREQ			0x0006
+#define PCIE_PHY_ATEOVRD			0x0010
+#define PCIE_PHY_MPLL_OVRD_IN_LO		0x0011
+#define PCIE_PHY_MPLL_OVRD_IN_HI		0x0011
+#define PCIE_PHY_SSC_OVRD_IN			0x0013
+#define PCIE_PHY_BS_OVRD_IN			0x0014
+#define PCIE_PHY_LEVEL_OVRD_IN			0x0015
+#define PCIE_PHY_SUP_OVRD_OUT			0x0016
+#define PCIE_PHY_MPLL_ASIC_IN			0x0017
+#define PCIE_PHY_BS_ASIC_IN			0x0018
+#define PCIE_PHY_LEVEL_ASIC_IN			0x0019
+#define PCIE_PHY_SSC_ASIC_IN			0x001a
+#define PCIE_PHY_SUP_ASIC_OUT			0x001b
+#define PCIE_PHY_ATEOVRD_STATUS			0x001c
+#define PCIE_PHY_SCOPE_ENABLES			0x0020
+#define PCIE_PHY_SCOPE_SAMPLES			0x0021
+#define PCIE_PHY_SCOPE_COUNT			0x0022
+#define PCIE_PHY_SCOPE_CTL			0x0023
+#define PCIE_PHY_SCOPE_MASK_000			0x0024
+#define PCIE_PHY_SCOPE_MASK_001			0x0025
+#define PCIE_PHY_SCOPE_MASK_010			0x0026
+#define PCIE_PHY_SCOPE_MASK_011			0x0027
+#define PCIE_PHY_SCOPE_MASK_100			0x0028
+#define PCIE_PHY_SCOPE_MASK_101			0x0029
+#define PCIE_PHY_SCOPE_MASK_110			0x002a
+#define PCIE_PHY_SCOPE_MASK_111			0x002b
+#define PCIE_PHY_MPLL_LOOP_CTL			0x0030
+#define PCIE_PHY_MPLL_ATB_MEAS2			0x0032
+#define PCIE_PHY_MPLL_OVR			0x0033
+#define PCIE_PHY_RTUNE_RTUNE_CTRL		0x0034
+#define PCIE_PHY_TX_OVRD_IN_LO			0x1000
+#define PCIE_PHY_TX_OVRD_IN_HI			0x1001
+#define PCIE_PHY_TX_OVRD_DRV_LO			0x1003
+#define PCIE_PHY_TX_OVRD_OUT			0x1004
+#define PCIE_PHY_RX_OVRD_IN_LO			0x1005
+#define  PCIE_PHY_RX_OVRD_IN_LO_RX_PLL_EN_OVRD	__BIT(3)
+#define  PCIE_PHY_RX_OVRD_IN_LO_RX_DATA_EN_OVRD	__BIT(5)
+#define PCIE_PHY_RX_OVRD_IN_HI			0x1006
+#define PCIE_PHY_RX_OVRD_OUT			0x1007
+#define PCIE_PHY_TX_ASIC_IN			0x1008
+#define PCIE_PHY_TX_ASIC_DRV_LO			0x1009
+#define PCIE_PHY_TX_ASIC_DRV_HI			0x100a
+#define PCIE_PHY_TX_ASIC_OUT			0x100b
+#define PCIE_PHY_RX_ASIC_IN			0x100c
+#define PCIE_PHY_RX_ASIC_OUT			0x100d
+#define  PCIE_PHY_RX_ASIC_OUT_LOS		__BIT(2)
+#define  PCIE_PHY_RX_ASIC_OUT_PLL_STATE		__BIT(1)
+#define  PCIE_PHY_RX_ASIC_OUT_VALID		__BIT(0)
+#define PCIE_PHY_TX_VMD_FSM_TX_VCM_0		0x1011
+#define PCIE_PHY_TX_VMD_FSM_TX_VCM_1		0x1012
+#define PCIE_PHY_TX_VMD_FSM_TX_VCM_DEBUG_IN	0x1013
+#define PCIE_PHY_TX_VMD_FSM_TX_VCM_DEBUG_OUT	0x1014
+#define PCIE_PHY_TX_LBERT_CTL			0x1015
+#define PCIE_PHY_RX_LBERT_CTL			0x1016
+#define PCIE_PHY_RX_LBERT_ERR			0x1017
+#define PCIE_PHY_RX_SCOPE_CTL			0x1018
+#define PCIE_PHY_RX_SCOPE_PHASE			0x1019
+#define PCIE_PHY_RX_DPLL_FREQ			0x101a
+#define PCIE_PHY_RX_CDR_CTL			0x101b
+#define PCIE_PHY_RX_CDR_CDR_FSM_DEBUG		0x101c
+#define PCIE_PHY_RX_CDR_LOCK_VEC_OVRD		0x101d
+#define PCIE_PHY_RX_CDR_LOCK_VEC		0x101e
+#define PCIE_PHY_RX_CDR_ADAP_FSM		0x101f
+#define PCIE_PHY_RX_ATB0			0x1020
+#define PCIE_PHY_RX_ATB1			0x1021
+#define PCIE_PHY_RX_ENPWR0			0x1022
+#define PCIE_PHY_RX_PMIX_PHASE			0x1023
+#define PCIE_PHY_RX_ENPWR1			0x1024
+#define PCIE_PHY_RX_ENPWR2			0x1025
+#define PCIE_PHY_RX_SCOPE			0x1026
+#define PCIE_PHY_TX_TXDRV_CNTRL			0x102b
+#define PCIE_PHY_TX_POWER_CTL			0x102c
+#define PCIE_PHY_TX_ALT_BLOCK			0x102d
+#define PCIE_PHY_TX_ALT_AND_LOOPBACK		0x102e
+#define PCIE_PHY_TX_TX_ATB_REG			0x102f
+
+#endif /* _ARM_IMX_IMX6_PCIEREG_H_ */
--- a/sys/arch/arm/imx/imx6_usdhc.c	Sun Nov 06 11:50:54 2016 +0000
+++ b/sys/arch/arm/imx/imx6_usdhc.c	Mon Dec 05 10:54:48 2016 +0000
@@ -1,4 +1,4 @@
-/*	$NetBSD: imx6_usdhc.c,v 1.1.2.1 2016/03/19 11:29:56 skrll Exp $ */
+/*	$NetBSD: imx6_usdhc.c,v 1.1.2.2 2016/12/05 10:54:50 skrll Exp $ */
 
 /*-
  * Copyright (c) 2012  Genetec Corporation.  All rights reserved.
@@ -30,7 +30,7 @@
 
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: imx6_usdhc.c,v 1.1.2.1 2016/03/19 11:29:56 skrll Exp $");
+__KERNEL_RCSID(0, "$NetBSD: imx6_usdhc.c,v 1.1.2.2 2016/12/05 10:54:50 skrll Exp $");
 
 #include "imxgpio.h"
 
@@ -39,6 +39,7 @@
 #include <sys/systm.h>
 #include <sys/bus.h>
 #include <sys/pmf.h>
+#include <sys/gpio.h>
 
 #include <machine/intr.h>
 
@@ -58,7 +59,7 @@
 	/* we have only one slot */
 	struct sdhc_host *sc_hosts[1];
 	int32_t sc_gpio_cd;
-	int32_t sc_gpio_cd_low_active;
+	int32_t sc_gpio_cd_active;
 	void *sc_ih;
 };
 
@@ -95,60 +96,16 @@
 #if NIMXGPIO > 0
 	if (sc->sc_gpio_cd >= 0) {
 		detect = gpio_data_read(sc->sc_gpio_cd);
+		if (sc->sc_gpio_cd_active == GPIO_PIN_LOW)
+			detect = !detect;
 	} else
 #endif
 		detect = 1;
-	if (sc->sc_gpio_cd_low_active)
-		detect = detect ? 0 : 1;
 
 	return detect;
 }
 
 static void
-sdhc_set_gpio_cd(struct sdhc_axi_softc *sc, const char *name)
-{
-	prop_dictionary_t dict;
-	const char *pin_data;
-	int grp, pin;
-
-	dict = device_properties(sc->sc_sdhc.sc_dev);
-	if (!prop_dictionary_get_cstring_nocopy(dict, name, &pin_data))
-		return;
-
-	/*
-	 * "!1,6" -> gpio_cd = GPIO_NO(1,6),  gpio_cd_low_active = 1
-	 * "3,31" -> gpio_cd = GPIO_NO(3,31), gpio_cd_low_active = 0
-	 * "!"    -> always not detected
-	 * none   -> always detected
-	 */
-	if (*pin_data == '!') {
-		sc->sc_gpio_cd_low_active = 1;
-		pin_data++;
-	} else
-		sc->sc_gpio_cd_low_active = 0;
-
-	sc->sc_gpio_cd = -1;
-	if (*pin_data == '\0')
-		return;
-
-	for (grp = 0; (*pin_data >= '0') && (*pin_data <= '9'); pin_data++)
-		grp = grp * 10 + *pin_data - '0';
-
-	KASSERT(*pin_data == ',');
-	pin_data++;
-
-	for (pin = 0; (*pin_data >= '0') && (*pin_data <= '9'); pin_data++)
-		pin = pin * 10 + *pin_data - '0';
-
-	KASSERT(*pin_data == '\0');
-
-	sc->sc_gpio_cd = GPIO_NO(grp, pin);
-#if NIMXGPIO > 0
-	gpio_set_direction(sc->sc_gpio_cd, GPIO_DIR_IN);
-#endif
-}
-
-static void
 sdhc_attach(device_t parent, device_t self, void *aux)
 {
 	struct sdhc_axi_softc *sc = device_private(self);
@@ -174,25 +131,29 @@
 		v = imx6_ccm_read(CCM_CCGR6);
 		imx6_ccm_write(CCM_CCGR6, v | CCM_CCGR6_USDHC1_CLK_ENABLE(3));
 		perclk = imx6_get_clock(IMX6CLK_USDHC1);
-		sdhc_set_gpio_cd(sc, "usdhc1-cd-gpio");
+		imx6_set_gpio(self, "usdhc1-cd-gpio", &sc->sc_gpio_cd,
+		    &sc->sc_gpio_cd_active, GPIO_DIR_IN);
 		break;
 	case IMX6_AIPS2_BASE + AIPS2_USDHC2_BASE:
 		v = imx6_ccm_read(CCM_CCGR6);
 		imx6_ccm_write(CCM_CCGR6, v | CCM_CCGR6_USDHC2_CLK_ENABLE(3));
 		perclk = imx6_get_clock(IMX6CLK_USDHC2);
-		sdhc_set_gpio_cd(sc, "usdhc2-cd-gpio");
+		imx6_set_gpio(self, "usdhc2-cd-gpio", &sc->sc_gpio_cd,
+		    &sc->sc_gpio_cd_active, GPIO_DIR_IN);
 		break;
 	case IMX6_AIPS2_BASE + AIPS2_USDHC3_BASE:
 		v = imx6_ccm_read(CCM_CCGR6);
 		imx6_ccm_write(CCM_CCGR6, v | CCM_CCGR6_USDHC3_CLK_ENABLE(3));
 		perclk = imx6_get_clock(IMX6CLK_USDHC3);
-		sdhc_set_gpio_cd(sc, "usdhc3-cd-gpio");
+		imx6_set_gpio(self, "usdhc3-cd-gpio", &sc->sc_gpio_cd,
+		    &sc->sc_gpio_cd_active, GPIO_DIR_IN);
 		break;
 	case IMX6_AIPS2_BASE + AIPS2_USDHC4_BASE:
 		v = imx6_ccm_read(CCM_CCGR6);
 		imx6_ccm_write(CCM_CCGR6, v | CCM_CCGR6_USDHC4_CLK_ENABLE(3));
 		perclk = imx6_get_clock(IMX6CLK_USDHC4);
-		sdhc_set_gpio_cd(sc, "usdhc4-cd-gpio");
+		imx6_set_gpio(self, "usdhc4-cd-gpio", &sc->sc_gpio_cd,
+		    &sc->sc_gpio_cd_active, GPIO_DIR_IN);
 		break;
 	}
 
--- a/sys/arch/arm/imx/imx6var.h	Sun Nov 06 11:50:54 2016 +0000
+++ b/sys/arch/arm/imx/imx6var.h	Mon Dec 05 10:54:48 2016 +0000
@@ -1,4 +1,4 @@
-/*	$NetBSD: imx6var.h,v 1.2.2.2 2016/03/19 11:29:56 skrll Exp $	*/
+/*	$NetBSD: imx6var.h,v 1.2.2.3 2016/12/05 10:54:50 skrll Exp $	*/
 
 /*
  * Copyright (c) 2014 Ryo Shimizu <ryo@nerv.org>
@@ -68,6 +68,7 @@
 void imx6_reset(void) __dead;
 void imx6_device_register(device_t, void *);
 void imx6_cpu_hatch(struct cpu_info *);
+void imx6_set_gpio(device_t, const char *, int32_t *, int32_t *, u_int);
 uint32_t imx6_chip_id(void);
 #define CHIPID_MINOR_MASK		0x000000ff
 #define CHIPID_MAJOR_MASK		0x00ffff00
--- a/sys/arch/arm/imx/imx7_board.c	Sun Nov 06 11:50:54 2016 +0000
+++ b/sys/arch/arm/imx/imx7_board.c	Mon Dec 05 10:54:48 2016 +0000
@@ -1,4 +1,4 @@
-/*	$NetBSD: imx7_board.c,v 1.1.2.2 2016/05/29 08:44:16 skrll Exp $	*/
+/*	$NetBSD: imx7_board.c,v 1.1.2.3 2016/12/05 10:54:50 skrll Exp $	*/
 
 /*
  * Copyright (c) 2012  Genetec Corporation.  All rights reserved.
@@ -27,7 +27,7 @@
  */
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: imx7_board.c,v 1.1.2.2 2016/05/29 08:44:16 skrll Exp $");
+__KERNEL_RCSID(0, "$NetBSD: imx7_board.c,v 1.1.2.3 2016/12/05 10:54:50 skrll Exp $");
 
 #include "opt_imx.h"
 
@@ -217,7 +217,7 @@
 		 * XXX KLUDGE ALERT XXX
 		 * The iot mainbus supplies is completely wrong since it scales
 		 * addresses by 2.  The simpliest remedy is to replace with our
-		 * bus space used for the armcore regisers
+		 * bus space used for the armcore registers
 		 * (which armperiph uses).
 		 */
 		struct mainbus_attach_args * const mb = aux;
--- a/sys/arch/arm/imx/imx7_ccm.c	Sun Nov 06 11:50:54 2016 +0000
+++ b/sys/arch/arm/imx/imx7_ccm.c	Mon Dec 05 10:54:48 2016 +0000
@@ -1,4 +1,4 @@
-/*	$NetBSD: imx7_ccm.c,v 1.1.2.2 2016/05/29 08:44:16 skrll Exp $	*/
+/*	$NetBSD: imx7_ccm.c,v 1.1.2.3 2016/12/05 10:54:50 skrll Exp $	*/
 
 /*
  * Copyright (c) 2010-2012, 2014  Genetec Corporation.  All rights reserved.
@@ -31,7 +31,7 @@
  */
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: imx7_ccm.c,v 1.1.2.2 2016/05/29 08:44:16 skrll Exp $");
+__KERNEL_RCSID(0, "$NetBSD: imx7_ccm.c,v 1.1.2.3 2016/12/05 10:54:50 skrll Exp $");
 
 #include "opt_imx.h"
 
@@ -1059,10 +1059,12 @@
 
 	if (rnode->sysctl_num == sc->sc_sysctlnode_arm_pll)
 		return imx7_set_clock(IMX7CLK_ARM_PLL, value);
-	if (rnode->sysctl_num == sc->sc_sysctlnode_arm_a7_clk)
+	else if (rnode->sysctl_num == sc->sc_sysctlnode_arm_a7_clk)
 		return imx7_set_clock(IMX7CLK_ARM_A7_CLK_ROOT, value);
+	else if (rnode->sysctl_num == sc->sc_sysctlnode_arm_m4_clk)
+		return imx7_set_clock(IMX7CLK_ARM_M4_CLK_ROOT, value);
 
-	return 0;
+	return EOPNOTSUPP;
 }
 
 
@@ -1105,7 +1107,7 @@
 }
 
 static uint64_t
-rootclk(int clk)
+rootclk(int clk, bool nodiv)
 {
 	uint32_t d, v;
 	uint64_t freq;
@@ -1126,6 +1128,9 @@
 	}
 #endif
 
+	if (nodiv)
+		return freq;
+
 	/* eval TARGET_ROOT[PRE_PODF] */
 	if ((imx7clkroottbl[clk].type != CLKTYPE_CORE) &&
 	    (imx7clkroottbl[clk].type != CLKTYPE_DRAM) &&
@@ -1449,7 +1454,7 @@
 	case IMX7CLK_AUDIO_MCLK_CLK_ROOT:
 	case IMX7CLK_CCM_CLKO1:
 	case IMX7CLK_CCM_CLKO2:
-		freq = rootclk(clk);
+		freq = rootclk(clk, false);
 		break;
 
 	default:
@@ -1461,10 +1466,45 @@
 	return freq;
 }
 
+/*
+ * resolve two clock divisors d3 and d6.
+ * freq = maxfreq / d3(3bit) / d6(6bit)
+ */
+static void
+getrootclkdiv(uint32_t maxfreq, uint32_t freq, uint32_t *d3p, uint32_t *d6p)
+{
+	uint32_t c_dif, c_d3, c_d6;
+	uint32_t dif, d3, d6;
+	uint32_t lim, base, f;
+
+	c_dif = 0xffffffff;
+	c_d3 = c_d6 = 0;
+	for (d3 = 0; d3 < 8; d3++) {
+		base = 0;
+		for (lim = 64; lim != 0; lim >>= 1) {
+			d6 = (lim >> 1) + base;
+			f = maxfreq / (d3 + 1) / (d6 + 1);
+			if (freq < f) {
+				base = d6 + 1;
+				lim--;
+			}
+			dif = (freq > f) ? freq - f : f - freq;
+			if (c_dif > dif) {
+				c_dif = dif;
+				c_d3 = d3;
+				c_d6 = d6;
+			}
+		}
+	}
+	*d3p = c_d3;
+	*d6p = c_d6;
+}
+
 int
 imx7_set_clock(enum imx7_clock clk, uint32_t freq)
 {
 	uint32_t v, x;
+	uint32_t d3, d6, maxfreq;
 
 	if (ccm_softc == NULL)
 		return 0;
@@ -1477,6 +1517,36 @@
 		v |=  __SHIFTIN(x, CCM_ANALOG_PLL_ARM_DIV_SELECT);
 		imx7_ccm_analog_write(CCM_ANALOG_PLL_ARM, v);
 		break;
+
+	/* core type clock */
+	case IMX7CLK_ARM_A7_CLK_ROOT:
+		maxfreq = rootclk(clk, true);
+		getrootclkdiv(maxfreq, freq, &d3, &d6);
+		v = imx7_ccm_read(imx7clkroottbl[clk].targetroot);
+		/* core type clocks use AUTO_PODF and POST_PODF */
+		v &= ~CCM_TARGET_ROOT_AUTO_PODF;
+		v |= __SHIFTIN(d3, CCM_TARGET_ROOT_AUTO_PODF);
+		v |= CCM_TARGET_ROOT_AUTO_ENABLE;
+		v &= ~CCM_TARGET_ROOT_POST_PODF;
+		v |= __SHIFTIN(d6, CCM_TARGET_ROOT_POST_PODF);
+		imx7_ccm_write(imx7clkroottbl[clk].targetroot, v);
+		break;
+
+	/* bus type clocks */
+	case IMX7CLK_ARM_M4_CLK_ROOT:
+	case IMX7CLK_MAIN_AXI_CLK_ROOT:
+	case IMX7CLK_DISP_AXI_CLK_ROOT:
+		maxfreq = rootclk(clk, true);
+		getrootclkdiv(maxfreq, freq, &d3, &d6);
+		/* bus type clocks use PRE_PODF and POST_PODF */
+		v = imx7_ccm_read(imx7clkroottbl[clk].targetroot);
+		v &= ~CCM_TARGET_ROOT_PRE_PODF;
+		v |= __SHIFTIN(d3, CCM_TARGET_ROOT_PRE_PODF);
+		v &= ~CCM_TARGET_ROOT_POST_PODF;
+		v |= __SHIFTIN(d6, CCM_TARGET_ROOT_POST_PODF);
+		imx7_ccm_write(imx7clkroottbl[clk].targetroot, v);
+		break;
+
 	default:
 		aprint_error_dev(ccm_softc->sc_dev,
 		    "%s: clockid %d: not supported\n", __func__, clk);
--- a/sys/arch/arm/imx/imx7_ccmreg.h	Sun Nov 06 11:50:54 2016 +0000
+++ b/sys/arch/arm/imx/imx7_ccmreg.h	Mon Dec 05 10:54:48 2016 +0000
@@ -1,4 +1,4 @@
-/*	$NetBSD: imx7_ccmreg.h,v 1.1.2.2 2016/05/29 08:44:16 skrll Exp $	*/
+/*	$NetBSD: imx7_ccmreg.h,v 1.1.2.3 2016/12/05 10:54:50 skrll Exp $	*/
 
 /*
  * Copyright (c) 2015 Internet Initiative Japan, Inc.
@@ -974,6 +974,10 @@
 #define CCM_CCGR190_TOG			0x00004bec
 
 /* CCGR mapping */
+#define CCM_CCGR_M4			CCM_CCGR1
+#define CCM_CCGR_M4_SET			(CCM_CCGR_M4 + 4)
+#define CCM_CCGR_M4_CLR			(CCM_CCGR_M4 + 8)
+#define CCM_CCGR_M4_TOG			(CCM_CCGR_M4 + 12)
 #define CCM_CCGR_SIM_MAIN		CCM_CCGR4
 #define CCM_CCGR_SIM_MAIN_SET		(CCM_CCGR_SIM_MAIN + 4)
 #define CCM_CCGR_SIM_MAIN_CLR		(CCM_CCGR_SIM_MAIN + 8)
--- a/sys/arch/arm/imx/imx7_gpcreg.h	Sun Nov 06 11:50:54 2016 +0000
+++ b/sys/arch/arm/imx/imx7_gpcreg.h	Mon Dec 05 10:54:48 2016 +0000
@@ -1,4 +1,4 @@
-/*	$NetBSD: imx7_gpcreg.h,v 1.1.2.2 2016/05/29 08:44:16 skrll Exp $	*/
+/*	$NetBSD: imx7_gpcreg.h,v 1.1.2.3 2016/12/05 10:54:50 skrll Exp $	*/
 
 /*
  * Copyright (c) 2015 Internet Initiative Japan, Inc.
@@ -59,6 +59,8 @@
 #define  GPC_PGC_ACK_SEL_A7_A7_PGC_PUP_ACK		__BIT(31)
 #define  GPC_PGC_ACK_SEL_A7_A7_PGC_PDN_ACK		__BIT(15)
 #define GPC_PGC_ACK_SEL_M4				0x00000028
+#define  GPC_PGC_ACK_SEL_M4_M4_DUMMY_PGC_PUP_ACK	__BIT(31)
+#define  GPC_PGC_ACK_SEL_M4_M4_DUMMY_PGC_PDN_ACK	__BIT(15)
 #define GPC_MISC					0x0000002c
 #define GPC_IMR1_CORE0_A7				0x00000030
 #define GPC_IMR2_CORE0_A7				0x00000034
@@ -92,6 +94,7 @@
 #define GPC_SLT9_CFG					0x000000d4
 #define GPC_PGC_CPU_MAPPING				0x000000ec
 #define  GPC_PGC_CPU_MAPPING_FASTMEGA_A7_DOMAIN		__BIT(0)
+#define  GPC_PGC_CPU_MAPPING_FASTMEGA_M4_DOMAIN		__BIT(8)
 #define GPC_CPU_PGC_SW_PUP_REQ				0x000000f0
 #define GPC_PU_PGC_SW_PUP_REQ				0x000000f8
 #define GPC_CPU_PGC_SW_PDN_REQ				0x000000fc
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/sys/arch/arm/imx/imx7_rdcreg.h	Mon Dec 05 10:54:48 2016 +0000
@@ -0,0 +1,643 @@
+/*	$NetBSD: imx7_rdcreg.h,v 1.1.4.2 2016/12/05 10:54:50 skrll Exp $	*/
+
+/*
+ * Copyright (c) 2016 Ryo Shimizu <ryo@nerv.org>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _ARM_IMX_IMX7_RDCREG_H_
+#define _ARM_IMX_IMX7_RDCREG_H_
+
+#include <sys/cdefs.h>
+
+/*
+ * Resource Domain Controller Module (AIPS1_RDC_BASE:0x303d0000)
+ */
+#define RDC_VIR					0x00000000
+#define RDC_STAT				0x00000024
+#define RDC_INTCTRL				0x00000028
+#define RDC_INTSTAT				0x0000002c
+
+/* Master Domain Assignment */
+#define RDC_MDA0				0x00000200
+#define RDC_MDA1				0x00000204
+#define RDC_MDA2				0x00000208
+#define RDC_MDA3				0x0000020c
+#define RDC_MDA4				0x00000210
+#define RDC_MDA5				0x00000214
+#define RDC_MDA6				0x00000218
+#define RDC_MDA7				0x0000021c
+#define RDC_MDA8				0x00000220
+#define RDC_MDA9				0x00000224
+#define RDC_MDA10				0x00000228
+#define RDC_MDA11				0x0000022c
+#define RDC_MDA12				0x00000230
+#define RDC_MDA13				0x00000234
+#define RDC_MDA14				0x00000238
+#define RDC_MDA15				0x0000023c
+#define RDC_MDA16				0x00000240
+#define RDC_MDA17				0x00000244
+#define RDC_MDA18				0x00000248
+#define RDC_MDA19				0x0000024c
+#define RDC_MDA20				0x00000250
+#define RDC_MDA21				0x00000254
+#define RDC_MDA22				0x00000258
+#define RDC_MDA23				0x0000025c
+#define RDC_MDA24				0x00000260
+#define RDC_MDA25				0x00000264
+#define RDC_MDA26				0x00000268
+
+#define RDC_MDA_A7_CORE_0			RDC_MDA0
+#define RDC_MDA_A7_CORE_1			RDC_MDA0
+#define RDC_MDA_M4_CORE				RDC_MDA1
+#define RDC_MDA_PCIE_CTRL			RDC_MDA2
+#define RDC_MDA_SCI				RDC_MDA3
+#define RDC_MDA_EPDC				RDC_MDA4
+#define RDC_MDA_LCDIF				RDC_MDA5
+#define RDC_MDA_DISPLAY_PORT			RDC_MDA6
+#define RDC_MDA_PXP				RDC_MDA7
+#define RDC_MDA_CORESIGHT			RDC_MDA8
+#define RDC_MDA_DAP				RDC_MDA9
+#define RDC_MDA_CAAM				RDC_MDA10
+#define RDC_MDA_SDMA_PERIPHERAL_DMA_PORT	RDC_MDA11
+#define RDC_MDA_SDMA_BURST_DMA_PORT		RDC_MDA12
+#define RDC_MDA_APBHDMA				RDC_MDA13
+#define RDC_MDA_RAWNAND				RDC_MDA14
+#define RDC_MDA_USDHC1				RDC_MDA15
+#define RDC_MDA_USDHC2				RDC_MDA16
+#define RDC_MDA_USDHC3				RDC_MDA17
+#define RDC_MDA_NC18				RDC_MDA18
+#define RDC_MDA_USB				RDC_MDA19
+#define RDC_MDA_NC20				RDC_MDA20
+#define RDC_MDA_TESTPORT			RDC_MDA21
+#define RDC_MDA_ENET1_TX			RDC_MDA22
+#define RDC_MDA_ENET1_RX			RDC_MDA23
+#define RDC_MDA_ENET2_TX			RDC_MDA24
+#define RDC_MDA_ENET2_RX			RDC_MDA25
+#define RDC_MDA_SDMA_PORT			RDC_MDA26
+
+/* RDC Peripheral Mapping */
+#define RDC_PDAP0				0x00000400
+#define RDC_PDAP1				0x00000404
+#define RDC_PDAP2				0x00000408
+#define RDC_PDAP3				0x0000040c
+#define RDC_PDAP4				0x00000410
+#define RDC_PDAP5				0x00000414
+#define RDC_PDAP6				0x00000418
+#define RDC_PDAP7				0x0000041c
+#define RDC_PDAP8				0x00000420
+#define RDC_PDAP9				0x00000424
+#define RDC_PDAP10				0x00000428
+#define RDC_PDAP11				0x0000042c
+#define RDC_PDAP12				0x00000430
+#define RDC_PDAP13				0x00000434
+#define RDC_PDAP14				0x00000438
+#define RDC_PDAP15				0x0000043c
+#define RDC_PDAP16				0x00000440
+#define RDC_PDAP17				0x00000444
+#define RDC_PDAP18				0x00000448
+#define RDC_PDAP19				0x0000044c
+#define RDC_PDAP20				0x00000450
+#define RDC_PDAP21				0x00000454
+#define RDC_PDAP22				0x00000458
+#define RDC_PDAP23				0x0000045c
+#define RDC_PDAP24				0x00000460
+#define RDC_PDAP25				0x00000464
+#define RDC_PDAP26				0x00000468
+#define RDC_PDAP27				0x0000046c
+#define RDC_PDAP28				0x00000470
+#define RDC_PDAP29				0x00000474
+#define RDC_PDAP30				0x00000478
+#define RDC_PDAP31				0x0000047c
+#define RDC_PDAP32				0x00000480
+#define RDC_PDAP33				0x00000484
+#define RDC_PDAP34				0x00000488
+#define RDC_PDAP35				0x0000048c
+#define RDC_PDAP36				0x00000490
+#define RDC_PDAP37				0x00000494
+#define RDC_PDAP38				0x00000498
+#define RDC_PDAP39				0x0000049c
+#define RDC_PDAP40				0x000004a0
+#define RDC_PDAP41				0x000004a4
+#define RDC_PDAP42				0x000004a8
+#define RDC_PDAP43				0x000004ac
+#define RDC_PDAP44				0x000004b0
+#define RDC_PDAP45				0x000004b4
+#define RDC_PDAP46				0x000004b8
+#define RDC_PDAP47				0x000004bc
+#define RDC_PDAP48				0x000004c0
+#define RDC_PDAP49				0x000004c4
+#define RDC_PDAP50				0x000004c8
+#define RDC_PDAP51				0x000004cc
+#define RDC_PDAP52				0x000004d0
+#define RDC_PDAP53				0x000004d4
+#define RDC_PDAP54				0x000004d8
+#define RDC_PDAP55				0x000004dc
+#define RDC_PDAP56				0x000004e0
+#define RDC_PDAP57				0x000004e4
+#define RDC_PDAP58				0x000004e8
+#define RDC_PDAP59				0x000004ec
+#define RDC_PDAP60				0x000004f0
+#define RDC_PDAP61				0x000004f4
+#define RDC_PDAP62				0x000004f8
+#define RDC_PDAP63				0x000004fc
+#define RDC_PDAP64				0x00000500
+#define RDC_PDAP65				0x00000504
+#define RDC_PDAP66				0x00000508
+#define RDC_PDAP67				0x0000050c
+#define RDC_PDAP68				0x00000510
+#define RDC_PDAP69				0x00000514
+#define RDC_PDAP70				0x00000518
+#define RDC_PDAP71				0x0000051c
+#define RDC_PDAP72				0x00000520
+#define RDC_PDAP73				0x00000524
+#define RDC_PDAP74				0x00000528
+#define RDC_PDAP75				0x0000052c
+#define RDC_PDAP76				0x00000530
+#define RDC_PDAP77				0x00000534
+#define RDC_PDAP78				0x00000538
+#define RDC_PDAP79				0x0000053c
+#define RDC_PDAP80				0x00000540
+#define RDC_PDAP81				0x00000544
+#define RDC_PDAP82				0x00000548
+#define RDC_PDAP83				0x0000054c
+#define RDC_PDAP84				0x00000550
+#define RDC_PDAP85				0x00000554
+#define RDC_PDAP86				0x00000558
+#define RDC_PDAP87				0x0000055c
+#define RDC_PDAP88				0x00000560
+#define RDC_PDAP89				0x00000564
+#define RDC_PDAP90				0x00000568
+#define RDC_PDAP91				0x0000056c
+#define RDC_PDAP92				0x00000570
+#define RDC_PDAP93				0x00000574
+#define RDC_PDAP94				0x00000578
+#define RDC_PDAP95				0x0000057c
+#define RDC_PDAP96				0x00000580
+#define RDC_PDAP97				0x00000584
+#define RDC_PDAP98				0x00000588
+#define RDC_PDAP99				0x0000058c
+#define RDC_PDAP100				0x00000590
+#define RDC_PDAP101				0x00000594
+#define RDC_PDAP102				0x00000598
+#define RDC_PDAP103				0x0000059c
+#define RDC_PDAP104				0x000005a0
+#define RDC_PDAP105				0x000005a4
+#define RDC_PDAP106				0x000005a8
+#define RDC_PDAP107				0x000005ac
+#define RDC_PDAP108				0x000005b0
+#define RDC_PDAP109				0x000005b4
+#define RDC_PDAP110				0x000005b8
+#define RDC_PDAP111				0x000005bc
+#define RDC_PDAP112				0x000005c0
+#define RDC_PDAP113				0x000005c4
+#define RDC_PDAP114				0x000005c8
+#define RDC_PDAP115				0x000005cc
+#define RDC_PDAP116				0x000005d0
+#define RDC_PDAP117				0x000005d4
+
+#define RDC_PDAP_GPIO1				RDC_PDAP0
+#define RDC_PDAP_GPIO2				RDC_PDAP1
+#define RDC_PDAP_GPIO3				RDC_PDAP2
+#define RDC_PDAP_GPIO4				RDC_PDAP3
+#define RDC_PDAP_GPIO5				RDC_PDAP4
+#define RDC_PDAP_GPIO6				RDC_PDAP5
+#define RDC_PDAP_GPIO7				RDC_PDAP6
+#define RDC_PDAP_IOMUXC_LPSR_GPR		RDC_PDAP7
+#define RDC_PDAP_WDOG1				RDC_PDAP8
+#define RDC_PDAP_WDOG2				RDC_PDAP9
+#define RDC_PDAP_WDOG3				RDC_PDAP10
+#define RDC_PDAP_WDOG4				RDC_PDAP11
+#define RDC_PDAP_IOMUXC_LPSR			RDC_PDAP12
+#define RDC_PDAP_GPT1				RDC_PDAP13
+#define RDC_PDAP_GPT2				RDC_PDAP14
+#define RDC_PDAP_GPT3				RDC_PDAP15
+#define RDC_PDAP_GPT4				RDC_PDAP16
+#define RDC_PDAP_ROMCP				RDC_PDAP17
+#define RDC_PDAP_KPP				RDC_PDAP18
+#define RDC_PDAP_IOMUXC				RDC_PDAP19
+#define RDC_PDAP_IOMUXC_GPR			RDC_PDAP20
+#define RDC_PDAP_OCOTP_CTRL			RDC_PDAP21
+#define RDC_PDAP_ANATOP_DIG			RDC_PDAP22
+#define RDC_PDAP_SNVS_HP			RDC_PDAP23
+#define RDC_PDAP_CCM				RDC_PDAP24
+#define RDC_PDAP_SRC				RDC_PDAP25
+#define RDC_PDAP_GPC				RDC_PDAP26
+#define RDC_PDAP_SEMAPHORE1			RDC_PDAP27
+#define RDC_PDAP_SEMAPHORE2			RDC_PDAP28
+#define RDC_PDAP_RDC				RDC_PDAP29
+#define RDC_PDAP_CSU				RDC_PDAP30
+#define RDC_PDAP_RESERVED_31			RDC_PDAP31
+#define RDC_PDAP_RESERVED_32			RDC_PDAP32
+#define RDC_PDAP_ADC1_WRAPPER			RDC_PDAP33
+#define RDC_PDAP_ADC2_WRAPPER			RDC_PDAP34
+#define RDC_PDAP_ECSPI4				RDC_PDAP35
+#define RDC_PDAP_FLEX_TIMER_1			RDC_PDAP36
+#define RDC_PDAP_FLEX_TIMER_2			RDC_PDAP37
+#define RDC_PDAP_PWM1				RDC_PDAP38
+#define RDC_PDAP_PWM2				RDC_PDAP39
+#define RDC_PDAP_PWM3				RDC_PDAP40
+#define RDC_PDAP_PWM4				RDC_PDAP41
+#define RDC_PDAP_SYSTEM_COUNTER_READ		RDC_PDAP42
+#define RDC_PDAP_SYSTEM_COUNTER_COMPARE		RDC_PDAP43
+#define RDC_PDAP_SYSTEM_COUNTER_CONTROL		RDC_PDAP44
+#define RDC_PDAP_PCIE_PHY			RDC_PDAP45
+#define RDC_PDAP_RESERVED_46			RDC_PDAP46
+#define RDC_PDAP_EPDC				RDC_PDAP47
+#define RDC_PDAP_PXP				RDC_PDAP48
+#define RDC_PDAP_CSI				RDC_PDAP49
+#define RDC_PDAP_RESERVED_50			RDC_PDAP50
+#define RDC_PDAP_LCDIF				RDC_PDAP51
+#define RDC_PDAP_RESERVED_52			RDC_PDAP52
+#define RDC_PDAP_MIPI_CSI			RDC_PDAP53
+#define RDC_PDAP_MIPI_DSI			RDC_PDAP54
+#define RDC_PDAP_RESERVED_55			RDC_PDAP55
+#define RDC_PDAP_TZASC				RDC_PDAP56
+#define RDC_PDAP_DDR_PHY			RDC_PDAP57
+#define RDC_PDAP_DDRC				RDC_PDAP58
+#define RDC_PDAP_RESERVED_59			RDC_PDAP59
+#define RDC_PDAP_PERFMON1			RDC_PDAP60
+#define RDC_PDAP_PERFMON2			RDC_PDAP61
+#define RDC_PDAP_AXI_DEBUG_MON			RDC_PDAP62
+#define RDC_PDAP_QOSC				RDC_PDAP63
+#define RDC_PDAP_FLEXCAN1			RDC_PDAP64
+#define RDC_PDAP_FLEXCAN2			RDC_PDAP65
+#define RDC_PDAP_I2C1				RDC_PDAP66
+#define RDC_PDAP_I2C2				RDC_PDAP67
+#define RDC_PDAP_I2C3				RDC_PDAP68
+#define RDC_PDAP_I2C4				RDC_PDAP69
+#define RDC_PDAP_UART4				RDC_PDAP70
+#define RDC_PDAP_UART5				RDC_PDAP71
+#define RDC_PDAP_UART6				RDC_PDAP72
+#define RDC_PDAP_UART7				RDC_PDAP73
+#define RDC_PDAP_MU_A				RDC_PDAP74
+#define RDC_PDAP_MU_B				RDC_PDAP75
+#define RDC_PDAP_SEMAPHORE_HS			RDC_PDAP76
+#define RDC_PDAP_USB_PL301			RDC_PDAP77
+#define RDC_PDAP_RESERVED_78			RDC_PDAP78
+#define RDC_PDAP_RESERVED_79			RDC_PDAP79
+#define RDC_PDAP_RESERVED_80			RDC_PDAP80
+#define RDC_PDAP_USB1_OTG1			RDC_PDAP81
+#define RDC_PDAP_USB2_OTG2			RDC_PDAP82
+#define RDC_PDAP_USB3_HOST			RDC_PDAP83
+#define RDC_PDAP_USDHC1				RDC_PDAP84
+#define RDC_PDAP_USDHC2				RDC_PDAP85
+#define RDC_PDAP_USDHC3				RDC_PDAP86
+#define RDC_PDAP_RESERVED_87			RDC_PDAP87
+#define RDC_PDAP_RESERVED_88			RDC_PDAP88
+#define RDC_PDAP_SIM1				RDC_PDAP89
+#define RDC_PDAP_SIM2				RDC_PDAP90
+#define RDC_PDAP_QSPI				RDC_PDAP91
+#define RDC_PDAP_WEIM				RDC_PDAP92
+#define RDC_PDAP_SDMA				RDC_PDAP93
+#define RDC_PDAP_ENET1				RDC_PDAP94
+#define RDC_PDAP_ENET2				RDC_PDAP95
+#define RDC_PDAP_RESERVED_96_FOR_SDMA		RDC_PDAP96
+#define RDC_PDAP_RESERVED_97			RDC_PDAP97
+#define RDC_PDAP_ECSPI1				RDC_PDAP98
+#define RDC_PDAP_ECSPI2				RDC_PDAP99
+#define RDC_PDAP_ECSPI3				RDC_PDAP100
+#define RDC_PDAP_RESERVED_101			RDC_PDAP101
+#define RDC_PDAP_UART1				RDC_PDAP102
+#define RDC_PDAP_UART2				RDC_PDAP103
+#define RDC_PDAP_UART3				RDC_PDAP104
+#define RDC_PDAP_RESERVED_105_FOR_SDMA		RDC_PDAP105
+#define RDC_PDAP_SAI1				RDC_PDAP106
+#define RDC_PDAP_SAI2				RDC_PDAP107
+#define RDC_PDAP_SAI3				RDC_PDAP108
+#define RDC_PDAP_RESERVED_109			RDC_PDAP109
+#define RDC_PDAP_RESERVED_110_FOR_SDMA		RDC_PDAP110
+#define RDC_PDAP_SPBA				RDC_PDAP111
+#define RDC_PDAP_ULT1_DAP			RDC_PDAP112
+#define RDC_PDAP_RESERVED_113			RDC_PDAP113
+#define RDC_PDAP_RESERVED_114			RDC_PDAP114
+#define RDC_PDAP_RESERVED_115			RDC_PDAP115
+#define RDC_PDAP_CAAM				RDC_PDAP116
+#define RDC_PDAP_RESERVED_117			RDC_PDAP117
+
+/* RDC Memory Region Map */
+#define RDC_MRSA0				0x00000800
+#define RDC_MREA0				0x00000804
+#define RDC_MRC0				0x00000808
+#define RDC_MRVS0				0x0000080c
+#define RDC_MRSA1				0x00000810
+#define RDC_MREA1				0x00000814
+#define RDC_MRC1				0x00000818
+#define RDC_MRVS1				0x0000081c
+/* skip 2..50 */
+#define RDC_MRSA51				0x00000b30
+#define RDC_MREA51				0x00000b34
+#define RDC_MRC51				0x00000b38
+#define RDC_MRVS51				0x00000b3c
+
+#define RDC_MRSA(n)				(0x00000800 + ((n) * 0x10))
+#define RDC_MREA(n)				(0x00000804 + ((n) * 0x10))
+#define RDC_MRC(n)				(0x00000808 + ((n) * 0x10))
+#define RDC_MRVS(n)				(0x0000080c + ((n) * 0x10))
+
+#define RDC_MR_MMDC_START		0		/* start of MMDC(n) */
+#define RDC_MR_MMDC_N			8		/* number of MMDC */
+#define RDC_MR_MMDC_RESSIZE		(1024 * 4)	/* region resolution */
+#define RDC_MR_QSPI_START		8		/* start of MMDC(n) */
+#define RDC_MR_QSPI_N			8		/* number of MMDC */
+#define RDC_MR_QSPI_RESSIZE		(1024 * 4)	/* region resolution */
+#define RDC_MR_WEIM_START		16		/* start of MMDC(n) */
+#define RDC_MR_WEIM_N			8		/* number of MMDC */
+#define RDC_MR_WEIM_RESSIZE		(1024 * 4)	/* region resolution */
+#define RDC_MR_PCIE_START		24		/* start of MMDC(n) */
+#define RDC_MR_PCIE_N			8		/* number of MMDC */
+#define RDC_MR_PCIE_RESSIZE		(1024 * 4)	/* region resolution */
+#define RDC_MR_OCRAM_START		32		/* start of MMDC(n) */
+#define RDC_MR_OCRAM_N			5		/* number of MMDC */
+#define RDC_MR_OCRAM_RESSIZE		(1024 * 128)	/* region resolution */
+#define RDC_MR_OCRAM_S_START		37		/* start of MMDC(n) */
+#define RDC_MR_OCRAM_S_N		5		/* number of MMDC */
+#define RDC_MR_OCRAM_S_RESSIZE		(1024 * 128)	/* region resolution */
+#define RDC_MR_OCRAM_EPDC_START		42		/* start of MMDC(n) */
+#define RDC_MR_OCRAM_EPDC_N		5		/* number of MMDC */
+#define RDC_MR_OCRAM_EPDC_RESSIZE	(1024 * 128)	/* region resolution */
+#define RDC_MR_OCRAM_PXP_START		47		/* start of MMDC(n) */
+#define RDC_MR_OCRAM_PXP_N		5		/* number of MMDC */
+#define RDC_MR_OCRAM_PXP_RESSIZE	(1024 * 128)	/* region resolution */
+
+/*
+ * RDC SEMAPHORE1 (AIPS1_SEMAPHORE1_BASE:0x303b0000)
+ */
+#define RDC_SEMAPHORE1_GATE0			0x00000000
+#define RDC_SEMAPHORE1_GATE1			0x00000001
+#define RDC_SEMAPHORE1_GATE2			0x00000002
+#define RDC_SEMAPHORE1_GATE3			0x00000003
+#define RDC_SEMAPHORE1_GATE4			0x00000004
+#define RDC_SEMAPHORE1_GATE5			0x00000005
+#define RDC_SEMAPHORE1_GATE6			0x00000006
+#define RDC_SEMAPHORE1_GATE7			0x00000007
+#define RDC_SEMAPHORE1_GATE8			0x00000008
+#define RDC_SEMAPHORE1_GATE9			0x00000009
+#define RDC_SEMAPHORE1_GATE10			0x0000000a
+#define RDC_SEMAPHORE1_GATE11			0x0000000b
+#define RDC_SEMAPHORE1_GATE12			0x0000000c
+#define RDC_SEMAPHORE1_GATE13			0x0000000d
+#define RDC_SEMAPHORE1_GATE14			0x0000000e
+#define RDC_SEMAPHORE1_GATE15			0x0000000f
+#define RDC_SEMAPHORE1_GATE16			0x00000010
+#define RDC_SEMAPHORE1_GATE17			0x00000011
+#define RDC_SEMAPHORE1_GATE18			0x00000012
+#define RDC_SEMAPHORE1_GATE19			0x00000013
+#define RDC_SEMAPHORE1_GATE20			0x00000014
+#define RDC_SEMAPHORE1_GATE21			0x00000015
+#define RDC_SEMAPHORE1_GATE22			0x00000016
+#define RDC_SEMAPHORE1_GATE23			0x00000017
+#define RDC_SEMAPHORE1_GATE24			0x00000018
+#define RDC_SEMAPHORE1_GATE25			0x00000019
+#define RDC_SEMAPHORE1_GATE26			0x0000001a
+#define RDC_SEMAPHORE1_GATE27			0x0000001b
+#define RDC_SEMAPHORE1_GATE28			0x0000001c
+#define RDC_SEMAPHORE1_GATE29			0x0000001d
+#define RDC_SEMAPHORE1_GATE30			0x0000001e
+#define RDC_SEMAPHORE1_GATE31			0x0000001f
+#define RDC_SEMAPHORE1_GATE32			0x00000020
+#define RDC_SEMAPHORE1_GATE33			0x00000021
+#define RDC_SEMAPHORE1_GATE34			0x00000022
+#define RDC_SEMAPHORE1_GATE35			0x00000023
+#define RDC_SEMAPHORE1_GATE36			0x00000024
+#define RDC_SEMAPHORE1_GATE37			0x00000025
+#define RDC_SEMAPHORE1_GATE38			0x00000026
+#define RDC_SEMAPHORE1_GATE39			0x00000027
+#define RDC_SEMAPHORE1_GATE40			0x00000028
+#define RDC_SEMAPHORE1_GATE41			0x00000029
+#define RDC_SEMAPHORE1_GATE42			0x0000002a
+#define RDC_SEMAPHORE1_GATE43			0x0000002b
+#define RDC_SEMAPHORE1_GATE44			0x0000002c
+#define RDC_SEMAPHORE1_GATE45			0x0000002d
+#define RDC_SEMAPHORE1_GATE46			0x0000002e
+#define RDC_SEMAPHORE1_GATE47			0x0000002f
+#define RDC_SEMAPHORE1_GATE48			0x00000030
+#define RDC_SEMAPHORE1_GATE49			0x00000031
+#define RDC_SEMAPHORE1_GATE50			0x00000032
+#define RDC_SEMAPHORE1_GATE51			0x00000033
+#define RDC_SEMAPHORE1_GATE52			0x00000034
+#define RDC_SEMAPHORE1_GATE53			0x00000035
+#define RDC_SEMAPHORE1_GATE54			0x00000036
+#define RDC_SEMAPHORE1_GATE55			0x00000037
+#define RDC_SEMAPHORE1_GATE56			0x00000038
+#define RDC_SEMAPHORE1_GATE57			0x00000039
+#define RDC_SEMAPHORE1_GATE58			0x0000003a
+#define RDC_SEMAPHORE1_GATE59			0x0000003b
+#define RDC_SEMAPHORE1_GATE60			0x0000003c
+#define RDC_SEMAPHORE1_GATE61			0x0000003d
+#define RDC_SEMAPHORE1_GATE62			0x0000003e
+#define RDC_SEMAPHORE1_GATE63			0x0000003f
+#define RDC_SEMAPHORE1_RSTGT_W			0x00000040
+#define RDC_SEMAPHORE1_RSTGT_R			0x00000040
+
+/*
+ * RDC SEMAPHORE2 (AIPS1_SEMAPHORE2_BASE:0x303c0000)
+ */
+#define RDC_SEMAPHORE2_GATE0			0x00000000
+#define RDC_SEMAPHORE2_GATE1			0x00000001
+#define RDC_SEMAPHORE2_GATE2			0x00000002
+#define RDC_SEMAPHORE2_GATE3			0x00000003
+#define RDC_SEMAPHORE2_GATE4			0x00000004
+#define RDC_SEMAPHORE2_GATE5			0x00000005
+#define RDC_SEMAPHORE2_GATE6			0x00000006
+#define RDC_SEMAPHORE2_GATE7			0x00000007
+#define RDC_SEMAPHORE2_GATE8			0x00000008
+#define RDC_SEMAPHORE2_GATE9			0x00000009
+#define RDC_SEMAPHORE2_GATE10			0x0000000a
+#define RDC_SEMAPHORE2_GATE11			0x0000000b
+#define RDC_SEMAPHORE2_GATE12			0x0000000c
+#define RDC_SEMAPHORE2_GATE13			0x0000000d
+#define RDC_SEMAPHORE2_GATE14			0x0000000e
+#define RDC_SEMAPHORE2_GATE15			0x0000000f
+#define RDC_SEMAPHORE2_GATE16			0x00000010
+#define RDC_SEMAPHORE2_GATE17			0x00000011
+#define RDC_SEMAPHORE2_GATE18			0x00000012
+#define RDC_SEMAPHORE2_GATE19			0x00000013
+#define RDC_SEMAPHORE2_GATE20			0x00000014
+#define RDC_SEMAPHORE2_GATE21			0x00000015
+#define RDC_SEMAPHORE2_GATE22			0x00000016
+#define RDC_SEMAPHORE2_GATE23			0x00000017
+#define RDC_SEMAPHORE2_GATE24			0x00000018
+#define RDC_SEMAPHORE2_GATE25			0x00000019
+#define RDC_SEMAPHORE2_GATE26			0x0000001a
+#define RDC_SEMAPHORE2_GATE27			0x0000001b
+#define RDC_SEMAPHORE2_GATE28			0x0000001c
+#define RDC_SEMAPHORE2_GATE29			0x0000001d
+#define RDC_SEMAPHORE2_GATE30			0x0000001e
+#define RDC_SEMAPHORE2_GATE31			0x0000001f
+#define RDC_SEMAPHORE2_GATE32			0x00000020
+#define RDC_SEMAPHORE2_GATE33			0x00000021
+#define RDC_SEMAPHORE2_GATE34			0x00000022
+#define RDC_SEMAPHORE2_GATE35			0x00000023
+#define RDC_SEMAPHORE2_GATE36			0x00000024
+#define RDC_SEMAPHORE2_GATE37			0x00000025
+#define RDC_SEMAPHORE2_GATE38			0x00000026
+#define RDC_SEMAPHORE2_GATE39			0x00000027
+#define RDC_SEMAPHORE2_GATE40			0x00000028
+#define RDC_SEMAPHORE2_GATE41			0x00000029
+#define RDC_SEMAPHORE2_GATE42			0x0000002a
+#define RDC_SEMAPHORE2_GATE43			0x0000002b
+#define RDC_SEMAPHORE2_GATE44			0x0000002c
+#define RDC_SEMAPHORE2_GATE45			0x0000002d
+#define RDC_SEMAPHORE2_GATE46			0x0000002e
+#define RDC_SEMAPHORE2_GATE47			0x0000002f
+#define RDC_SEMAPHORE2_GATE48			0x00000030
+#define RDC_SEMAPHORE2_GATE49			0x00000031
+#define RDC_SEMAPHORE2_GATE50			0x00000032
+#define RDC_SEMAPHORE2_GATE51			0x00000033
+#define RDC_SEMAPHORE2_GATE52			0x00000034
+#define RDC_SEMAPHORE2_GATE53			0x00000035
+#define RDC_SEMAPHORE2_GATE54			0x00000036
+#define RDC_SEMAPHORE2_GATE55			0x00000037
+#define RDC_SEMAPHORE2_GATE56			0x00000038
+#define RDC_SEMAPHORE2_GATE57			0x00000039
+#define RDC_SEMAPHORE2_GATE58			0x0000003a
+#define RDC_SEMAPHORE2_GATE59			0x0000003b
+#define RDC_SEMAPHORE2_GATE60			0x0000003c
+#define RDC_SEMAPHORE2_GATE61			0x0000003d
+#define RDC_SEMAPHORE2_GATE62			0x0000003e
+#define RDC_SEMAPHORE2_GATE63			0x0000003f
+#define RDC_SEMAPHORE2_RSTGT_W			0x00000040
+#define RDC_SEMAPHORE2_RSTGT_R			0x00000040
+
+#define RDC_SEMAPHORE2_GPIO1			RDC_SEMAPHORE1_GATE0
+#define RDC_SEMAPHORE2_GPIO2			RDC_SEMAPHORE1_GATE1
+#define RDC_SEMAPHORE2_GPIO3			RDC_SEMAPHORE1_GATE2
+#define RDC_SEMAPHORE2_GPIO4			RDC_SEMAPHORE1_GATE3
+#define RDC_SEMAPHORE2_GPIO5			RDC_SEMAPHORE1_GATE4
+#define RDC_SEMAPHORE2_GPIO6			RDC_SEMAPHORE1_GATE5
+#define RDC_SEMAPHORE2_GPIO7			RDC_SEMAPHORE1_GATE6
+#define RDC_SEMAPHORE2_IOMUXC_LPSR_GPR		RDC_SEMAPHORE1_GATE7
+#define RDC_SEMAPHORE2_WDOG1			RDC_SEMAPHORE1_GATE8
+#define RDC_SEMAPHORE2_WDOG2			RDC_SEMAPHORE1_GATE9
+#define RDC_SEMAPHORE2_WDOG3			RDC_SEMAPHORE1_GATE10
+#define RDC_SEMAPHORE2_WDOG4			RDC_SEMAPHORE1_GATE11
+#define RDC_SEMAPHORE2_IOMUXC_LPSR		RDC_SEMAPHORE1_GATE12
+#define RDC_SEMAPHORE2_GPT1			RDC_SEMAPHORE1_GATE13
+#define RDC_SEMAPHORE2_GPT2			RDC_SEMAPHORE1_GATE14
+#define RDC_SEMAPHORE2_GPT3			RDC_SEMAPHORE1_GATE15
+#define RDC_SEMAPHORE2_GPT4			RDC_SEMAPHORE1_GATE16
+#define RDC_SEMAPHORE2_ROMCP			RDC_SEMAPHORE1_GATE17
+#define RDC_SEMAPHORE2_KPP			RDC_SEMAPHORE1_GATE18
+#define RDC_SEMAPHORE2_IOMUXC			RDC_SEMAPHORE1_GATE19
+#define RDC_SEMAPHORE2_IOMUXC_GPR		RDC_SEMAPHORE1_GATE20
+#define RDC_SEMAPHORE2_OCOTP_CTRL		RDC_SEMAPHORE1_GATE21
+#define RDC_SEMAPHORE2_ANATOP_DIG		RDC_SEMAPHORE1_GATE22
+#define RDC_SEMAPHORE2_SNVS_HP			RDC_SEMAPHORE1_GATE23
+#define RDC_SEMAPHORE2_CCM			RDC_SEMAPHORE1_GATE24
+#define RDC_SEMAPHORE2_SRC			RDC_SEMAPHORE1_GATE25
+#define RDC_SEMAPHORE2_GPC			RDC_SEMAPHORE1_GATE26
+#define RDC_SEMAPHORE2_SEMAPHORE1		RDC_SEMAPHORE1_GATE27
+#define RDC_SEMAPHORE2_SEMAPHORE2		RDC_SEMAPHORE1_GATE28
+#define RDC_SEMAPHORE2_RDC			RDC_SEMAPHORE1_GATE29
+#define RDC_SEMAPHORE2_CSU			RDC_SEMAPHORE1_GATE30
+#define RDC_SEMAPHORE2_RESERVED_31		RDC_SEMAPHORE1_GATE31
+#define RDC_SEMAPHORE2_RESERVED_32		RDC_SEMAPHORE1_GATE32
+#define RDC_SEMAPHORE2_ADC1_WRAPPER		RDC_SEMAPHORE1_GATE33
+#define RDC_SEMAPHORE2_ADC2_WRAPPER		RDC_SEMAPHORE1_GATE34
+#define RDC_SEMAPHORE2_ECSPI4			RDC_SEMAPHORE1_GATE35
+#define RDC_SEMAPHORE2_FLEX_TIMER_1		RDC_SEMAPHORE1_GATE36
+#define RDC_SEMAPHORE2_FLEX_TIMER_2		RDC_SEMAPHORE1_GATE37
+#define RDC_SEMAPHORE2_PWM1			RDC_SEMAPHORE1_GATE38
+#define RDC_SEMAPHORE2_PWM2			RDC_SEMAPHORE1_GATE39
+#define RDC_SEMAPHORE2_PWM3			RDC_SEMAPHORE1_GATE40
+#define RDC_SEMAPHORE2_PWM4			RDC_SEMAPHORE1_GATE41
+#define RDC_SEMAPHORE2_SYSTEM_COUNTER_READ	RDC_SEMAPHORE1_GATE42
+#define RDC_SEMAPHORE2_SYSTEM_COUNTER_COMPARE	RDC_SEMAPHORE1_GATE43
+#define RDC_SEMAPHORE2_SYSTEM_COUNTER_CONTROL	RDC_SEMAPHORE1_GATE44
+#define RDC_SEMAPHORE2_PCIE_PHY			RDC_SEMAPHORE1_GATE45
+#define RDC_SEMAPHORE2_RESERVED_46		RDC_SEMAPHORE1_GATE46
+#define RDC_SEMAPHORE2_EPDC			RDC_SEMAPHORE1_GATE47
+#define RDC_SEMAPHORE2_PXP			RDC_SEMAPHORE1_GATE48
+#define RDC_SEMAPHORE2_CSI			RDC_SEMAPHORE1_GATE49
+#define RDC_SEMAPHORE2_RESERVED_50		RDC_SEMAPHORE1_GATE50
+#define RDC_SEMAPHORE2_LCDIF			RDC_SEMAPHORE1_GATE51
+#define RDC_SEMAPHORE2_RESERVED_52		RDC_SEMAPHORE1_GATE52
+#define RDC_SEMAPHORE2_MIPI_CSI			RDC_SEMAPHORE1_GATE53
+#define RDC_SEMAPHORE2_MIPI_DSI			RDC_SEMAPHORE1_GATE54
+#define RDC_SEMAPHORE2_RESERVED_55		RDC_SEMAPHORE1_GATE55
+#define RDC_SEMAPHORE2_TZASC			RDC_SEMAPHORE1_GATE56
+#define RDC_SEMAPHORE2_DDR_PHY			RDC_SEMAPHORE1_GATE57
+#define RDC_SEMAPHORE2_DDRC			RDC_SEMAPHORE1_GATE58
+#define RDC_SEMAPHORE2_RESERVED_59		RDC_SEMAPHORE1_GATE59
+#define RDC_SEMAPHORE2_PERFMON1			RDC_SEMAPHORE1_GATE60
+#define RDC_SEMAPHORE2_PERFMON2			RDC_SEMAPHORE1_GATE61
+#define RDC_SEMAPHORE2_AXI_DEBUG_MON		RDC_SEMAPHORE1_GATE62
+#define RDC_SEMAPHORE2_QOSC			RDC_SEMAPHORE1_GATE63
+#define RDC_SEMAPHORE2_FLEXCAN1			RDC_SEMAPHORE2_GATE0
+#define RDC_SEMAPHORE2_FLEXCAN2			RDC_SEMAPHORE2_GATE1
+#define RDC_SEMAPHORE2_I2C1			RDC_SEMAPHORE2_GATE2
+#define RDC_SEMAPHORE2_I2C2			RDC_SEMAPHORE2_GATE3
+#define RDC_SEMAPHORE2_I2C3			RDC_SEMAPHORE2_GATE4
+#define RDC_SEMAPHORE2_I2C4			RDC_SEMAPHORE2_GATE5
+#define RDC_SEMAPHORE2_UART4			RDC_SEMAPHORE2_GATE6
+#define RDC_SEMAPHORE2_UART5			RDC_SEMAPHORE2_GATE7
+#define RDC_SEMAPHORE2_UART6			RDC_SEMAPHORE2_GATE8
+#define RDC_SEMAPHORE2_UART7			RDC_SEMAPHORE2_GATE9
+#define RDC_SEMAPHORE2_MU_A			RDC_SEMAPHORE2_GATE10
+#define RDC_SEMAPHORE2_MU_B			RDC_SEMAPHORE2_GATE11
+#define RDC_SEMAPHORE2_SEMAPHORE_HS		RDC_SEMAPHORE2_GATE12
+#define RDC_SEMAPHORE2_USB_PL301		RDC_SEMAPHORE2_GATE13
+#define RDC_SEMAPHORE2_RESERVED_78		RDC_SEMAPHORE2_GATE14
+#define RDC_SEMAPHORE2_RESERVED_79		RDC_SEMAPHORE2_GATE15
+#define RDC_SEMAPHORE2_RESERVED_80		RDC_SEMAPHORE2_GATE16
+#define RDC_SEMAPHORE2_USB1_OTG1		RDC_SEMAPHORE2_GATE17
+#define RDC_SEMAPHORE2_USB2_OTG2		RDC_SEMAPHORE2_GATE18
+#define RDC_SEMAPHORE2_USB3_HOST		RDC_SEMAPHORE2_GATE19
+#define RDC_SEMAPHORE2_USDHC1			RDC_SEMAPHORE2_GATE20
+#define RDC_SEMAPHORE2_USDHC2			RDC_SEMAPHORE2_GATE21
+#define RDC_SEMAPHORE2_USDHC3			RDC_SEMAPHORE2_GATE22
+#define RDC_SEMAPHORE2_RESERVED_87		RDC_SEMAPHORE2_GATE23
+#define RDC_SEMAPHORE2_RESERVED_88		RDC_SEMAPHORE2_GATE24
+#define RDC_SEMAPHORE2_SIM1			RDC_SEMAPHORE2_GATE25
+#define RDC_SEMAPHORE2_SIM2			RDC_SEMAPHORE2_GATE26
+#define RDC_SEMAPHORE2_QSPI			RDC_SEMAPHORE2_GATE27
+#define RDC_SEMAPHORE2_WEIM			RDC_SEMAPHORE2_GATE28
+#define RDC_SEMAPHORE2_SDMA			RDC_SEMAPHORE2_GATE29
+#define RDC_SEMAPHORE2_ENET1			RDC_SEMAPHORE2_GATE30
+#define RDC_SEMAPHORE2_ENET2			RDC_SEMAPHORE2_GATE31
+#define RDC_SEMAPHORE2_RESERVED_96_FOR_SDMA	RDC_SEMAPHORE2_GATE32
+#define RDC_SEMAPHORE2_RESERVED_97		RDC_SEMAPHORE2_GATE33
+#define RDC_SEMAPHORE2_ECSPI1			RDC_SEMAPHORE2_GATE34
+#define RDC_SEMAPHORE2_ECSPI2			RDC_SEMAPHORE2_GATE35
+#define RDC_SEMAPHORE2_ECSPI3			RDC_SEMAPHORE2_GATE36
+#define RDC_SEMAPHORE2_RESERVED_101		RDC_SEMAPHORE2_GATE37
+#define RDC_SEMAPHORE2_UART1			RDC_SEMAPHORE2_GATE38
+#define RDC_SEMAPHORE2_UART2			RDC_SEMAPHORE2_GATE39
+#define RDC_SEMAPHORE2_UART3			RDC_SEMAPHORE2_GATE40
+#define RDC_SEMAPHORE2_RESERVED_105_FOR_SDMA	RDC_SEMAPHORE2_GATE41
+#define RDC_SEMAPHORE2_SAI1			RDC_SEMAPHORE2_GATE42
+#define RDC_SEMAPHORE2_SAI2			RDC_SEMAPHORE2_GATE43
+#define RDC_SEMAPHORE2_SAI3			RDC_SEMAPHORE2_GATE44
+#define RDC_SEMAPHORE2_RESERVED_109		RDC_SEMAPHORE2_GATE45
+#define RDC_SEMAPHORE2_RESERVED_110_FOR_SDMA	RDC_SEMAPHORE2_GATE46
+#define RDC_SEMAPHORE2_SPBA			RDC_SEMAPHORE2_GATE47
+#define RDC_SEMAPHORE2_ULT1_DAP			RDC_SEMAPHORE2_GATE48
+#define RDC_SEMAPHORE2_RESERVED_113		RDC_SEMAPHORE2_GATE49
+#define RDC_SEMAPHORE2_RESERVED_114		RDC_SEMAPHORE2_GATE50
+#define RDC_SEMAPHORE2_RESERVED_115		RDC_SEMAPHORE2_GATE51
+#define RDC_SEMAPHORE2_CAAM			RDC_SEMAPHORE2_GATE52
+#define RDC_SEMAPHORE2_RESERVED_117		RDC_SEMAPHORE2_GATE53
+
+#endif /* _ARM_IMX_IMX7_RDCREG_H_ */
--- a/sys/arch/arm/imx/imx7_srcreg.h	Sun Nov 06 11:50:54 2016 +0000
+++ b/sys/arch/arm/imx/imx7_srcreg.h	Mon Dec 05 10:54:48 2016 +0000
@@ -1,4 +1,4 @@
-/*	$NetBSD: imx7_srcreg.h,v 1.1.2.2 2016/05/29 08:44:16 skrll Exp $	*/
+/*	$NetBSD: imx7_srcreg.h,v 1.1.2.3 2016/12/05 10:54:50 skrll Exp $	*/
 
 /*
  * Copyright (c) 2015 Internet Initiative Japan, Inc.
@@ -45,6 +45,7 @@
 #define  SRC_M4RCR_ENABLE_M4			__BIT(3)
 #define  SRC_M4RCR_SW_M4P_RST			__BIT(2)
 #define  SRC_M4RCR_SW_M4C_RST			__BIT(1)
+#define  SRC_M4RCR_SW_M4C_NON_SCLR_RST		__BIT(0)
 #define SRC_ERCR				0x00000014
 #define SRC_HSICPHY_RCR				0x0000001c
 #define  SRC_HSICPHY_PORT_RST			__BIT(1)
--- a/sys/arch/arm/include/isa_machdep.h	Sun Nov 06 11:50:54 2016 +0000
+++ b/sys/arch/arm/include/isa_machdep.h	Mon Dec 05 10:54:48 2016 +0000
@@ -1,4 +1,4 @@
-/*	$NetBSD: isa_machdep.h,v 1.11 2014/01/29 00:42:15 matt Exp $	*/
+/*	$NetBSD: isa_machdep.h,v 1.11.6.1 2016/12/05 10:54:50 skrll Exp $	*/
 
 /*-
  * Copyright (c) 1996, 1997, 1998 The NetBSD Foundation, Inc.
@@ -56,6 +56,8 @@
 const struct evcnt *isa_intr_evcnt(isa_chipset_tag_t ic, int irq);
 void	*isa_intr_establish(isa_chipset_tag_t ic, int irq, int type,
 	    int level, int (*ih_fun)(void *), void *ih_arg);
+void	*isa_intr_establish_xname(isa_chipset_tag_t ic, int irq, int type,
+	    int level, int (*ih_fun)(void *), void *ih_arg, const char *xname);
 void	isa_intr_disestablish(isa_chipset_tag_t ic, void *handler);
 
 #define	isa_dmainit(ic, bst, dmat, d)					\
--- a/sys/arch/arm/include/ptrace.h	Sun Nov 06 11:50:54 2016 +0000
+++ b/sys/arch/arm/include/ptrace.h	Mon Dec 05 10:54:48 2016 +0000
@@ -1,4 +1,4 @@
-/*	$NetBSD: ptrace.h,v 1.6.14.2 2015/12/27 12:09:30 skrll Exp $	*/
+/*	$NetBSD: ptrace.h,v 1.6.14.3 2016/12/05 10:54:50 skrll Exp $	*/
 
 /*
  * Copyright (c) 1995 Frank Lancaster
@@ -53,10 +53,10 @@
 	"PT_SETFPREGS",
 
 #include <machine/reg.h>
-#define PTRACE_REG_PC(r)	(r)->r_pc
-#define PTRACE_REG_SET_PC(r, v)	(r)->r_pc = (v)
-#define PTRACE_REG_SP(r)	(r)->r_sp
-#define PTRACE_REG_INTRV(r)	(r)->r[0]
+#define PTRACE_REG_PC(_r)		(_r)->r_pc
+#define PTRACE_REG_SET_PC(_r, _v)	(_r)->r_pc = (_v)
+#define PTRACE_REG_SP(_r)		(_r)->r_sp
+#define PTRACE_REG_INTRV(_r)		(_r)->r[0]
 
 #define PTRACE_BREAKPOINT	((const uint8_t[]) { 0xe7, 0xff, 0xff, 0xff })
 #define PTRACE_BREAKPOINT_SIZE	4
--- a/sys/arch/arm/nvidia/tegra_cpufreq.c	Sun Nov 06 11:50:54 2016 +0000
+++ b/sys/arch/arm/nvidia/tegra_cpufreq.c	Mon Dec 05 10:54:48 2016 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: tegra_cpufreq.c,v 1.1.2.3 2015/12/27 12:09:31 skrll Exp $ */
+/* $NetBSD: tegra_cpufreq.c,v 1.1.2.4 2016/12/05 10:54:50 skrll Exp $ */
 
 /*-
  * Copyright (c) 2015 Jared D. McNeill <jmcneill@invisible.ca>
@@ -29,7 +29,7 @@
 #include "locators.h"
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: tegra_cpufreq.c,v 1.1.2.3 2015/12/27 12:09:31 skrll Exp $");
+__KERNEL_RCSID(0, "$NetBSD: tegra_cpufreq.c,v 1.1.2.4 2016/12/05 10:54:50 skrll Exp $");
 
 #include <sys/param.h>
 #include <sys/bus.h>
@@ -39,7 +39,6 @@
 #include <sys/kernel.h>
 #include <sys/atomic.h>
 #include <sys/kmem.h>
-#include <sys/xcall.h>
 #include <sys/sysctl.h>
 
 #include <arm/nvidia/tegra_var.h>
--- a/sys/arch/arm/omap/am335x_prcm.c	Sun Nov 06 11:50:54 2016 +0000
+++ b/sys/arch/arm/omap/am335x_prcm.c	Mon Dec 05 10:54:48 2016 +0000
@@ -1,4 +1,4 @@
-/*	$NetBSD: am335x_prcm.c,v 1.8 2014/09/30 11:34:07 jmcneill Exp $	*/
+/*	$NetBSD: am335x_prcm.c,v 1.8.2.1 2016/12/05 10:54:50 skrll Exp $	*/
 
 /*
  * TI OMAP Power, Reset, and Clock Management on the AM335x
@@ -34,10 +34,13 @@
  */
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: am335x_prcm.c,v 1.8 2014/09/30 11:34:07 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: am335x_prcm.c,v 1.8.2.1 2016/12/05 10:54:50 skrll Exp $");
+
+#include "tps65217pmic.h"
 
 #include <sys/types.h>
 #include <sys/param.h>
+#include <sys/device.h>
 #include <sys/sysctl.h>
 #include <sys/pmf.h>
 
@@ -46,6 +49,8 @@
 #include <arm/omap/omap2_prcm.h>
 #include <arm/omap/omap_var.h>
 
+#include <dev/i2c/tps65217pmicvar.h>
+
 #define AM335X_CLKCTRL_MODULEMODE_MASK		__BITS(0, 1)
 #define   AM335X_CLKCTRL_MODULEMODE_DISABLED	0
 #define   AM335X_CLKCTRL_MODULEMODE_ENABLE	2
@@ -161,6 +166,25 @@
 	}
 }
 
+const char *mpu_supply = NULL;
+static int
+set_mpu_volt(int mvolt)
+{
+	device_t dev;
+
+	__USE(dev);	// Simpler than complex ifdef.
+
+	if (mpu_supply == NULL)
+		return ENODEV;
+
+#if NTPS65217PMIC > 0
+	dev = device_find_by_xname("tps65217pmic0");
+	if (dev != NULL)
+		return tps65217pmic_set_volt(dev, mpu_supply, mvolt);
+#endif
+	return ENODEV;
+}
+
 static int
 mpu_current_frequency_sysctl_helper(SYSCTLFN_ARGS)
 {
--- a/sys/arch/arm/omap/am335x_prcm.h	Sun Nov 06 11:50:54 2016 +0000
+++ b/sys/arch/arm/omap/am335x_prcm.h	Mon Dec 05 10:54:48 2016 +0000
@@ -1,4 +1,4 @@
-/*	$NetBSD: am335x_prcm.h,v 1.8.4.1 2015/09/22 12:05:38 skrll Exp $	*/
+/*	$NetBSD: am335x_prcm.h,v 1.8.4.2 2016/12/05 10:54:50 skrll Exp $	*/
 
 /*
  * TI OMAP Power, Reset, and Clock Management on the AM335x
@@ -150,7 +150,6 @@
 #define RST_GLOBAL_COLD_SW	__BIT(1)
 
 #ifdef _KERNEL
-int  set_mpu_volt(int);
 void am335x_sys_clk(bus_space_handle_t);
 void am335x_cpu_clk(void);
 #endif
--- a/sys/arch/arm/omap/files.omap2	Sun Nov 06 11:50:54 2016 +0000
+++ b/sys/arch/arm/omap/files.omap2	Mon Dec 05 10:54:48 2016 +0000
@@ -1,4 +1,4 @@
-#	$NetBSD: files.omap2,v 1.29.2.4 2016/07/09 20:24:50 skrll Exp $
+#	$NetBSD: files.omap2,v 1.29.2.5 2016/12/05 10:54:50 skrll Exp $
 #
 # Configuration info for Texas Instruments OMAP2/OMAP3 CPU support
 # Based on xscale/files.pxa2x0
@@ -59,8 +59,7 @@
 # OMAP2 GPIO controllers
 device	omapgpio: gpiobus
 attach	omapgpio at obio with omap2gpio
-file	arch/arm/omap/omap2_gpio.c		(omap2 | omap3) & !ti_am335x & omapgpio
-file	arch/arm/omap/am335x_gpio.c		ti_am335x & omapgpio
+file	arch/arm/omap/omap2_gpio.c		(omap2 | omap3) & omapgpio
 
 # TI_AM335X (and maybe TI OMAP4) I2C controllers
 device	tiiic: i2cbus, i2cexec
@@ -117,7 +116,7 @@
 # General Purpose Memory Controller
 # XXX some addl. chip select config parms may be desired here (e.g. timing)
 # XXX so far we just use the setup established by boot firmware
-device	gpmc { [addr=-1], [size=0], [intr=-1], [mult=1], [nobyteacc=0]
+device	gpmc { [cs=-1], [addr=-1], [size=0], [intr=-1], [mult=1], [nobyteacc=0]
 	      } : bus_space_generic
 attach	gpmc at mainbus
 file	arch/arm/omap/omap2_gpmc.c		gpmc
@@ -134,8 +133,9 @@
 attach  motg at tiotg_port
 
 # SDMMC controller
+attach	sdhc at mainbus with mainbussdhc
 attach	sdhc at obio with obiosdhc
-file	arch/arm/omap/omap3_sdhc.c		obiosdhc
+file	arch/arm/omap/omap3_sdhc.c		mainbussdhc | obiosdhc
 
 # NAND flash controller
 device	omapnand: nandbus
--- a/sys/arch/arm/omap/omap2430_intr.h	Sun Nov 06 11:50:54 2016 +0000
+++ b/sys/arch/arm/omap/omap2430_intr.h	Mon Dec 05 10:54:48 2016 +0000
@@ -1,4 +1,4 @@
-/*	$NetBSD: omap2430_intr.h,v 1.4 2012/07/14 07:42:57 matt Exp $ */
+/*	$NetBSD: omap2430_intr.h,v 1.4.16.1 2016/12/05 10:54:50 skrll Exp $ */
 
 /*
  * Define the SDP2430 specific information and then include the generic OMAP
@@ -161,7 +161,11 @@
 #define	IRQ_MMC3		94	/* (3530) MMC/SD module 3 */
 #define	IRQ_GPT12_3530		95	/* (3530) GPT12 */
 
+#if defined(TI_AM335X)
+#define	PIC_MAXSOURCES		128
+#else
 #define	PIC_MAXSOURCES		96
+#endif
 #define	PIC_MAXMAXSOURCES	(PIC_MAXSOURCES+192)
 
 void omap_irq_handler(void *);
--- a/sys/arch/arm/omap/omap2_gpio.c	Sun Nov 06 11:50:54 2016 +0000
+++ b/sys/arch/arm/omap/omap2_gpio.c	Mon Dec 05 10:54:48 2016 +0000
@@ -1,4 +1,4 @@
-/*	$NetBSD: omap2_gpio.c,v 1.16.10.1 2016/10/05 20:55:25 skrll Exp $	*/
+/*	$NetBSD: omap2_gpio.c,v 1.16.10.2 2016/12/05 10:54:50 skrll Exp $	*/
 /*-
  * Copyright (c) 2007 The NetBSD Foundation, Inc.
  * All rights reserved.
@@ -28,7 +28,7 @@
  * POSSIBILITY OF SUCH DAMAGE.
  */
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: omap2_gpio.c,v 1.16.10.1 2016/10/05 20:55:25 skrll Exp $");
+__KERNEL_RCSID(0, "$NetBSD: omap2_gpio.c,v 1.16.10.2 2016/12/05 10:54:50 skrll Exp $");
 
 #define _INTR_PRIVATE
 
@@ -50,9 +50,13 @@
 
 #include <sys/bus.h>
 
+#include <arm/omap/am335x_prcm.h>
 #include <arm/omap/omap2_reg.h>
 #include <arm/omap/omap2_obiovar.h>
 #include <arm/omap/omap2_gpio.h>
+#include <arm/omap/omap2_prcm.h>
+#include <arm/omap/sitara_cm.h>
+#include <arm/omap/sitara_cmreg.h>
 #include <arm/pic/picvar.h>
 
 #if NGPIO > 0
@@ -60,6 +64,15 @@
 #include <dev/gpio/gpiovar.h>
 #endif
 
+#ifdef TI_AM335X
+static const struct omap_module gpio_module[] = {
+	{ 0, 0 },
+	{ AM335X_PRCM_CM_PER, CM_PER_GPIO1_CLKCTRL },
+	{ AM335X_PRCM_CM_PER, CM_PER_GPIO2_CLKCTRL },
+	{ AM335X_PRCM_CM_PER, CM_PER_GPIO3_CLKCTRL },
+};
+#endif
+
 static void gpio_pic_block_irqs(struct pic_softc *, size_t, uint32_t);
 static void gpio_pic_block_irqs2(struct pic_softc *, size_t, uint32_t);
 static void gpio_pic_unblock_irqs(struct pic_softc *, size_t, uint32_t);
@@ -318,16 +331,11 @@
 {
 	struct gpio_softc * const gpio = arg;
 	uint32_t mask = 1 << pin;
-	uint32_t old, new;
 
-	old = GPIO_READ(gpio, GPIO_DATAOUT);
 	if (value)
-		new = old | mask;
+		GPIO_WRITE(gpio, GPIO_SETDATAOUT, mask);
 	else
-		new = old & ~mask;
-
-	if (old != new)
-		GPIO_WRITE(gpio, GPIO_DATAOUT, new);
+		GPIO_WRITE(gpio, GPIO_CLEARDATAOUT, mask);
 }
 
 static void
@@ -483,9 +491,6 @@
 
 	gpio->gpio_dev = self;
 
-	if (oa->obio_intr == OBIOCF_INTR_DEFAULT)
-		panic("\n%s: no intr assigned", device_xname(self));
-
 	if (oa->obio_size == OBIOCF_SIZE_DEFAULT)
 		panic("\n%s: no size assigned", device_xname(self));
 
@@ -524,6 +529,23 @@
 		aprint_normal(", intr %d", oa->obio_intr);
 	}
 	aprint_normal("\n");
+
+#ifdef TI_AM335X
+	switch (oa->obio_addr) {
+	case GPIO0_BASE_TI_AM335X:
+		break;
+	case GPIO1_BASE_TI_AM335X:
+		prcm_module_enable(&gpio_module[1]);
+		break;
+	case GPIO2_BASE_TI_AM335X:
+		prcm_module_enable(&gpio_module[2]);
+		break;
+	case GPIO3_BASE_TI_AM335X:
+		prcm_module_enable(&gpio_module[3]);
+		break;
+	}
+#endif
+
 #if NGPIO > 0
 #if 0
 	config_interrupts(self, gpio_attach1);
--- a/sys/arch/arm/omap/omap2_gpmc.c	Sun Nov 06 11:50:54 2016 +0000
+++ b/sys/arch/arm/omap/omap2_gpmc.c	Mon Dec 05 10:54:48 2016 +0000
@@ -1,7 +1,7 @@
-/*	$Id: omap2_gpmc.c,v 1.9 2011/07/01 20:30:21 dyoung Exp $	*/
+/*	$Id: omap2_gpmc.c,v 1.9.30.1 2016/12/05 10:54:50 skrll Exp $	*/
 
 /* adapted from: */
-/*	$NetBSD: omap2_gpmc.c,v 1.9 2011/07/01 20:30:21 dyoung Exp $ */
+/*	$NetBSD: omap2_gpmc.c,v 1.9.30.1 2016/12/05 10:54:50 skrll Exp $ */
 
 
 /*
@@ -102,7 +102,7 @@
 
 #include "opt_omap.h"
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: omap2_gpmc.c,v 1.9 2011/07/01 20:30:21 dyoung Exp $");
+__KERNEL_RCSID(0, "$NetBSD: omap2_gpmc.c,v 1.9.30.1 2016/12/05 10:54:50 skrll Exp $");
 
 #include "locators.h"
 
@@ -278,7 +278,22 @@
 	aa.gpmc_intr = cf->cf_loc[GPMCCF_INTR];
 
 	cs = &sc->sc_csconfig[0];
-	for (i=0; i < GPMC_NCS; i++) {
+	for (i = 0; i < GPMC_NCS; i++) {
+		if (cf->cf_loc[GPMCCF_CS] != GPMCCF_CS_DEFAULT) {
+			if (i != cf->cf_loc[GPMCCF_CS]) {
+				cs++;
+				continue;
+			}
+
+			if (aa.gpmc_addr != GPMCCF_ADDR_DEFAULT
+			&&  aa.gpmc_addr != cs->cs_addr)
+				panic("cs:addr missmatch:"
+				    " cs %d(0x%08lx), addr 0x%08lx\n",
+				    cf->cf_loc[GPMCCF_CS], cs->cs_addr,
+				    aa.gpmc_addr);
+			aa.gpmc_addr = cs->cs_addr;
+		}
+
 		if ((aa.gpmc_addr >= cs->cs_addr)
 		&&  (aa.gpmc_addr < (cs->cs_addr + cs->cs_size))) {
 			/* XXX
--- a/sys/arch/arm/omap/omap2_icu.c	Sun Nov 06 11:50:54 2016 +0000
+++ b/sys/arch/arm/omap/omap2_icu.c	Mon Dec 05 10:54:48 2016 +0000
@@ -1,4 +1,4 @@
-/*	$NetBSD: omap2_icu.c,v 1.9 2012/08/20 12:38:28 matt Exp $	*/
+/*	$NetBSD: omap2_icu.c,v 1.9.16.1 2016/12/05 10:54:50 skrll Exp $	*/
 /*
  * Define the SDP2430 specific information and then include the generic OMAP
  * interrupt header.
@@ -30,7 +30,7 @@
 #define _INTR_PRIVATE
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: omap2_icu.c,v 1.9 2012/08/20 12:38:28 matt Exp $");
+__KERNEL_RCSID(0, "$NetBSD: omap2_icu.c,v 1.9.16.1 2016/12/05 10:54:50 skrll Exp $");
 
 #include <sys/param.h>
 #include <sys/evcnt.h>
@@ -82,11 +82,19 @@
 	bus_space_tag_t sc_memt;
 	bus_space_handle_t sc_memh;
 	struct pic_softc sc_pic;
+#if defined(TI_AM335X)
+	uint32_t sc_enabled_irqs[4];
+#else
 	uint32_t sc_enabled_irqs[3];
+#endif
 } omap2icu_softc = {
 	.sc_pic = {
 		.pic_ops = &omap2icu_picops,
+#if defined(TI_AM335X)
+		.pic_maxsources = 128,
+#else
 		.pic_maxsources = 96,
+#endif
 		.pic_name = "omap2icu",
 	},
 };
@@ -161,7 +169,7 @@
 void
 omap2icu_establish_irq(struct pic_softc *pic, struct intrsource *is)
 {
-	KASSERT(is->is_irq < 96);
+	KASSERT(is->is_irq < omap2icu_softc.sc_pic.pic_maxsources);
 	KASSERT(is->is_type == IST_LEVEL);
 }
 
--- a/sys/arch/arm/omap/omap2_nand.c	Sun Nov 06 11:50:54 2016 +0000
+++ b/sys/arch/arm/omap/omap2_nand.c	Mon Dec 05 10:54:48 2016 +0000
@@ -1,4 +1,4 @@
-/*	$NetBSD: omap2_nand.c,v 1.5 2012/10/27 17:17:40 chs Exp $	*/
+/*	$NetBSD: omap2_nand.c,v 1.5.14.1 2016/12/05 10:54:50 skrll Exp $	*/
 
 /*-
  * Copyright (c) 2010 Department of Software Engineering,
@@ -36,7 +36,7 @@
  */
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: omap2_nand.c,v 1.5 2012/10/27 17:17:40 chs Exp $");
+__KERNEL_RCSID(0, "$NetBSD: omap2_nand.c,v 1.5.14.1 2016/12/05 10:54:50 skrll Exp $");
 
 #include "opt_omap.h"
 #include "opt_flash.h"
@@ -209,7 +209,6 @@
 	sc->sc_dev = self;
 	sc->sc_cs = gpmc->gpmc_cs;
 
-//	cs_offset = GPMC_BASE + GPMC_CONFIG1_0 + sc->sc_cs * GPMC_CS_SIZE;
 	cs_offset = GPMC_CS_CONFIG_BASE(sc->sc_cs);
 
 	/* map i/o space */
--- a/sys/arch/arm/omap/omap2_obio.c	Sun Nov 06 11:50:54 2016 +0000
+++ b/sys/arch/arm/omap/omap2_obio.c	Mon Dec 05 10:54:48 2016 +0000
@@ -1,7 +1,7 @@
-/*	$Id: omap2_obio.c,v 1.21.10.2 2016/05/29 08:44:16 skrll Exp $	*/
+/*	$Id: omap2_obio.c,v 1.21.10.3 2016/12/05 10:54:50 skrll Exp $	*/
 
 /* adapted from: */
-/*	$NetBSD: omap2_obio.c,v 1.21.10.2 2016/05/29 08:44:16 skrll Exp $ */
+/*	$NetBSD: omap2_obio.c,v 1.21.10.3 2016/12/05 10:54:50 skrll Exp $ */
 
 
 /*
@@ -103,7 +103,7 @@
 
 #include "opt_omap.h"
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: omap2_obio.c,v 1.21.10.2 2016/05/29 08:44:16 skrll Exp $");
+__KERNEL_RCSID(0, "$NetBSD: omap2_obio.c,v 1.21.10.3 2016/12/05 10:54:50 skrll Exp $");
 
 #include "locators.h"
 #include "obio.h"
@@ -378,6 +378,9 @@
 #if defined(OMAP_3530)
 	{ .name = "avic",    .addr = INTC_BASE_3530, .required = true },
 #endif
+#if defined(TI_AM335X)
+	{ .name = "omapicu", .addr = 0x48200000, .required = true },
+#endif
 	{ .name = "gpio1", .addr = GPIO1_BASE, .required = false },
 	{ .name = "gpio2", .addr = GPIO2_BASE, .required = false },
 	{ .name = "gpio3", .addr = GPIO3_BASE, .required = false },
@@ -400,7 +403,6 @@
 	{ .name = "dmac", .addr = DMAC_BASE, .required = true },
 #endif
 #if defined(TI_AM335X)
-	{ .name = "omapicu", .addr = 0x48200000, .required = true },
 	{ .name = "prcm", .addr = 0x44e00000, .required = true },
 	{ .name = "sitaracm", .addr = 0x44e10000, .required = true },
 	{ .name = "edma", .addr = 0x49000000, .required = false },
--- a/sys/arch/arm/omap/omap2_reg.h	Sun Nov 06 11:50:54 2016 +0000
+++ b/sys/arch/arm/omap/omap2_reg.h	Mon Dec 05 10:54:48 2016 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: omap2_reg.h,v 1.28.4.5 2016/10/05 20:55:25 skrll Exp $ */
+/* $NetBSD: omap2_reg.h,v 1.28.4.6 2016/12/05 10:54:50 skrll Exp $ */
 
 /*
  * Copyright (c) 2007 Microsoft
@@ -163,6 +163,18 @@
 #define DEVID_AMDM37X_ES11	0x1b89102f
 #define DEVID_AMDM37X_ES12	0x2b89102f
 
+#define CHIPID_AM3351		0x00fc0302
+#define CHIPID_AM3352		0x00fc0382
+#define CHIPID_AM3354		0x20fc0382
+#define CHIPID_AM3356		0x00fd0383
+#define CHIPID_AM3357		0x00ff0383
+#define CHIPID_AM3358		0x20fd0383
+#define CHIPID_AM3359		0x20ff0383
+
+#define DEVID_AM335X_SR_10	0x0b94402e
+#define DEVID_AM335X_SR_20	0x1b94402e
+#define DEVID_AM335X_SR_21	0x2b94402e
+
 /*
  * Clock Management registers base, offsets, and size
  */
--- a/sys/arch/arm/omap/omap3_ehci.c	Sun Nov 06 11:50:54 2016 +0000
+++ b/sys/arch/arm/omap/omap3_ehci.c	Mon Dec 05 10:54:48 2016 +0000
@@ -1,4 +1,4 @@
-/* $NetBSD: omap3_ehci.c,v 1.10.6.4 2015/12/27 12:09:31 skrll Exp $ */
+/* $NetBSD: omap3_ehci.c,v 1.10.6.5 2016/12/05 10:54:50 skrll Exp $ */
 
 /*-
  * Copyright (c) 2010-2012 Jared D. McNeill <jmcneill@invisible.ca>
@@ -26,7 +26,7 @@
  */
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: omap3_ehci.c,v 1.10.6.4 2015/12/27 12:09:31 skrll Exp $");
+__KERNEL_RCSID(0, "$NetBSD: omap3_ehci.c,v 1.10.6.5 2016/12/05 10:54:50 skrll Exp $");
 
 #include "locators.h"
 
@@ -196,6 +196,7 @@
 		enum omap3_ehci_port_mode mode;
 		int gpio;
 		bool value;
+		bool extclk;
 	} sc_portconfig[3];
 	struct {
 		uint16_t m, n, m2;
@@ -405,15 +406,24 @@
 	sc->sc_portconfig[0].mode = omap3_ehci_get_port_mode(prop, "port0-mode");
 	sc->sc_portconfig[0].gpio = omap3_ehci_get_port_gpio(prop, "port0-gpio");
 	prop_dictionary_get_bool(prop, "port0-gpioval", &sc->sc_portconfig[0].value);
+#if defined(OMAP4) || defined(OMAP5)
+	prop_dictionary_get_bool(prop, "port0-extclk", &sc->sc_portconfig[0].extclk);
+#endif
 	if (sc->sc_nports > 1) {
 		sc->sc_portconfig[1].mode = omap3_ehci_get_port_mode(prop, "port1-mode");
 		sc->sc_portconfig[1].gpio = omap3_ehci_get_port_gpio(prop, "port1-gpio");
 		prop_dictionary_get_bool(prop, "port1-gpioval", &sc->sc_portconfig[1].value);
+#if defined(OMAP4) || defined(OMAP5)
+		prop_dictionary_get_bool(prop, "port1-extclk", &sc->sc_portconfig[1].extclk);
+#endif
 	}
 	if (sc->sc_nports > 2) {
 		sc->sc_portconfig[2].mode = omap3_ehci_get_port_mode(prop, "port2-mode");
 		sc->sc_portconfig[2].gpio = omap3_ehci_get_port_gpio(prop, "port2-gpio");
 		prop_dictionary_get_bool(prop, "port2-gpioval", &sc->sc_portconfig[2].value);
+#if defined(OMAP4) || defined(OMAP5)
+		prop_dictionary_get_bool(prop, "port2-extclk", &sc->sc_portconfig[2].extclk);
+#endif
 	}
 
 #ifdef OMAP_3XXX
@@ -670,17 +680,43 @@
 	KASSERT(err == 0);
 
 	val = bus_space_read_4(iot, ioh, OMAP4_CM_L3INIT_USB_HOST_HS_CLKCTRL);
-	val |= OMAP4_CM_L3INIT_USB_HOST_HS_CLKCTRL_OPTFCLKEN_HSIC60M_P3_CLK
-	    |  OMAP4_CM_L3INIT_USB_HOST_HS_CLKCTRL_OPTFCLKEN_HSIC60M_P2_CLK
-	    |  OMAP4_CM_L3INIT_USB_HOST_HS_CLKCTRL_OPTFCLKEN_HSIC480M_P3_CLK
-	    |  OMAP4_CM_L3INIT_USB_HOST_HS_CLKCTRL_OPTFCLKEN_HSIC480M_P2_CLK
-	    |  OMAP4_CM_L3INIT_USB_HOST_HS_CLKCTRL_OPTFCLKEN_UTMI_P3_CLK
-	    |  OMAP4_CM_L3INIT_USB_HOST_HS_CLKCTRL_OPTFCLKEN_UTMI_P2_CLK;
+	if (sc->sc_portconfig[0].mode != OMAP3_EHCI_PORT_MODE_NONE) {
+		if (sc->sc_portconfig[0].extclk)
+			val |= OMAP4_CM_L3INIT_USB_HOST_HS_CLKCTRL_CLKSEL_UTMI_P1;
+		else
+			val |= OMAP4_CM_L3INIT_USB_HOST_HS_CLKCTRL_OPTFCLKEN_UTMI_P1_CLK;
+		if (sc->sc_portconfig[0].mode == OMAP3_EHCI_PORT_MODE_HSIC)
+			val |= OMAP4_CM_L3INIT_USB_HOST_HS_CLKCTRL_OPTFCLKEN_HSIC60M_P1_CLK
+			    |  OMAP4_CM_L3INIT_USB_HOST_HS_CLKCTRL_OPTFCLKEN_HSIC480M_P1_CLK;
+	}
+	if (sc->sc_nports > 1
+	    && sc->sc_portconfig[1].mode != OMAP3_EHCI_PORT_MODE_NONE) {
+		if (sc->sc_portconfig[1].extclk)
+			val |= OMAP4_CM_L3INIT_USB_HOST_HS_CLKCTRL_CLKSEL_UTMI_P2;
+		else
+			val |= OMAP4_CM_L3INIT_USB_HOST_HS_CLKCTRL_OPTFCLKEN_UTMI_P2_CLK;
+		if (sc->sc_portconfig[1].mode == OMAP3_EHCI_PORT_MODE_HSIC)
+			val |= OMAP4_CM_L3INIT_USB_HOST_HS_CLKCTRL_OPTFCLKEN_HSIC60M_P2_CLK
+			    |  OMAP4_CM_L3INIT_USB_HOST_HS_CLKCTRL_OPTFCLKEN_HSIC480M_P2_CLK;
+	}
+	if (sc->sc_nports > 2
+	    && sc->sc_portconfig[2].mode != OMAP3_EHCI_PORT_MODE_NONE) {
+		val |= OMAP4_CM_L3INIT_USB_HOST_HS_CLKCTRL_OPTFCLKEN_UTMI_P3_CLK;
+		if (sc->sc_portconfig[2].mode == OMAP3_EHCI_PORT_MODE_HSIC)
+			val |= OMAP4_CM_L3INIT_USB_HOST_HS_CLKCTRL_OPTFCLKEN_HSIC60M_P3_CLK
+			    |  OMAP4_CM_L3INIT_USB_HOST_HS_CLKCTRL_OPTFCLKEN_HSIC480M_P3_CLK;
+	}
 	bus_space_write_4(iot, ioh, OMAP4_CM_L3INIT_USB_HOST_HS_CLKCTRL, val);
 
 	val = bus_space_read_4(iot, ioh, OMAP4_CM_L3INIT_USB_TLL_HS_CLKCTRL);
-	val |= OMAP4_CM_L3INIT_USB_TLL_HS_CLKCTRL_USB_CH2_CLK
-	    |  OMAP4_CM_L3INIT_USB_TLL_HS_CLKCTRL_USB_CH1_CLK;
+	if (sc->sc_portconfig[0].mode != OMAP3_EHCI_PORT_MODE_NONE)
+		val |= OMAP4_CM_L3INIT_USB_TLL_HS_CLKCTRL_USB_CH0_CLK;
+	if (sc->sc_nports > 1
+	    && sc->sc_portconfig[1].mode != OMAP3_EHCI_PORT_MODE_NONE)
+		val |= OMAP4_CM_L3INIT_USB_TLL_HS_CLKCTRL_USB_CH1_CLK;
+	if (sc->sc_nports > 2
+	    && sc->sc_portconfig[2].mode != OMAP3_EHCI_PORT_MODE_NONE)
+		val |= OMAP4_CM_L3INIT_USB_TLL_HS_CLKCTRL_USB_CH2_CLK;
 	bus_space_write_4(iot, ioh, OMAP4_CM_L3INIT_USB_TLL_HS_CLKCTRL, val);
 
 	bus_space_unmap(iot, ioh, 0x100);
--- a/sys/arch/arm/omap/omap3_sdhc.c	Sun Nov 06 11:50:54 2016 +0000
+++ b/sys/arch/arm/omap/omap3_sdhc.c	Mon Dec 05 10:54:48 2016 +0000
@@ -1,4 +1,4 @@
-/*	$NetBSD: omap3_sdhc.c,v 1.14.6.7 2016/10/05 20:55:25 skrll Exp $	*/
+/*	$NetBSD: omap3_sdhc.c,v 1.14.6.8 2016/12/05 10:54:50 skrll Exp $	*/
 /*-
  * Copyright (c) 2011 The NetBSD Foundation, Inc.
  * All rights reserved.
@@ -29,7 +29,7 @@
  */
 
 #include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: omap3_sdhc.c,v 1.14.6.7 2016/10/05 20:55:25 skrll Exp $");
+__KERNEL_RCSID(0, "$NetBSD: omap3_sdhc.c,v 1.14.6.8 2016/12/05 10:54:50 skrll Exp $");
 
 #include "opt_omap.h"
 #include "edma.h"
@@ -37,6 +37,7 @@
 #include <sys/param.h>
 #include <sys/systm.h>
 #include <sys/device.h>
+#include <sys/errno.h>
 #include <sys/kernel.h>
 #include <sys/proc.h>
 #include <sys/queue.h>
@@ -49,8 +50,10 @@
 #include <arm/omap/omap3_sdmmcreg.h>
 
 #ifdef TI_AM335X
+#  include <arm/mainbus/mainbus.h>
 #  include <arm/omap/am335x_prcm.h>
 #  include <arm/omap/omap2_prcm.h>
+#  include <arm/omap/omap_var.h>
 #  include <arm/omap/sitara_cm.h>
 #  include <arm/omap/sitara_cmreg.h>
 #endif
@@ -82,25 +85,19 @@
 #define SDHC_WRITE(sc, reg, val) \
 	bus_space_write_4((sc)->sc_bst, (sc)->sc_sdhc_bsh, (reg), (val))
 
-static int obiosdhc_match(device_t, cfdata_t, void *);
-static void obiosdhc_attach(device_t, device_t, void *);
-static int obiosdhc_detach(device_t, int);
-
-static int obiosdhc_bus_width(struct sdhc_softc *, int);
-static int obiosdhc_rod(struct sdhc_softc *, int);
-static int obiosdhc_write_protect(struct sdhc_softc *);
-static int obiosdhc_card_detect(struct sdhc_softc *);
-
-struct obiosdhc_softc {
+struct mmchs_softc {
 	struct sdhc_softc	sc;
+	bus_addr_t		sc_addr;
 	bus_space_tag_t		sc_bst;
 	bus_space_handle_t	sc_bsh;
 	bus_space_handle_t	sc_hl_bsh;
 	bus_space_handle_t	sc_sdhc_bsh;
 	struct sdhc_host	*sc_hosts[1];
+	int			sc_irq;
 	void 			*sc_ih;		/* interrupt vectoring */
 
 #if NEDMA > 0
+	int			sc_edmabase;
 	struct edma_channel	*sc_edma_tx;
 	struct edma_channel	*sc_edma_rx;
 	uint16_t		sc_edma_param_tx[EDMA_MAX_PARAMS];
@@ -114,26 +111,45 @@
 #endif
 };
 
+static int obiosdhc_match(device_t, cfdata_t, void *);
+static void obiosdhc_attach(device_t, device_t, void *);
+#ifdef TI_AM335X
+static int mainbussdhc_match(device_t, cfdata_t, void *);
+static void mainbussdhc_attach(device_t, device_t, void *);
+#endif
+static int mmchs_detach(device_t, int);
+
+static int mmchs_attach(struct mmchs_softc *);
+static void mmchs_init(device_t);
+
+static int mmchs_bus_width(struct sdhc_softc *, int);
+static int mmchs_rod(struct sdhc_softc *, int);
+static int mmchs_write_protect(struct sdhc_softc *);
+static int mmchs_card_detect(struct sdhc_softc *);
+
 #if NEDMA > 0
-static int obiosdhc_edma_init(struct obiosdhc_softc *, unsigned int);
-static int obiosdhc_edma_xfer_data(struct sdhc_softc *, struct sdmmc_command *);
-static void obiosdhc_edma_done(void *);
-static int obiosdhc_edma_transfer(struct sdhc_softc *, struct sdmmc_command *);
+static int mmchs_edma_init(struct mmchs_softc *, unsigned int);
+static int mmchs_edma_xfer_data(struct sdhc_softc *, struct sdmmc_command *);
+static void mmchs_edma_done(void *);
+static int mmchs_edma_transfer(struct sdhc_softc *, struct sdmmc_command *);
 #endif
 
 #ifdef TI_AM335X
-struct am335x_sdhc {
+struct am335x_mmchs {
 	const char *as_name;
+	const char *as_parent_name;
 	bus_addr_t as_base_addr;
 	int as_intr;
 	struct omap_module as_module;
 };
 
-static const struct am335x_sdhc am335x_sdhc[] = {