- Share pchb(4) between i386 and amd64; one copy is enough for both. trunk
authorxtraeme <xtraeme@NetBSD.org>
Fri, 26 Oct 2007 21:49:50 +0000
branchtrunk
changeset 162808 ea442cbf5f28
parent 162807 adaeec7de78e
child 162809 145bbf4adeb6
- Share pchb(4) between i386 and amd64; one copy is enough for both. - Move some of the x86 PCI devices into x86/pci/files.pci. - Add more x86 stuff into x86/conf/files.x86. ok joerg.
sys/arch/amd64/conf/files.amd64
sys/arch/amd64/pci/pchb.c
sys/arch/i386/conf/files.i386
sys/arch/i386/pci/pchb.c
sys/arch/x86/conf/files.x86
sys/arch/x86/pci/files.pci
sys/arch/x86/pci/pchb.c
sys/arch/xen/conf/files.xen
--- a/sys/arch/amd64/conf/files.amd64	Fri Oct 26 21:09:49 2007 +0000
+++ b/sys/arch/amd64/conf/files.amd64	Fri Oct 26 21:49:50 2007 +0000
@@ -1,4 +1,4 @@
-#	$NetBSD: files.amd64,v 1.46 2007/10/18 15:28:33 yamt Exp $
+#	$NetBSD: files.amd64,v 1.47 2007/10/26 21:49:50 xtraeme Exp $
 #
 # new style config file for amd64 architecture
 #
@@ -33,7 +33,6 @@
 file	arch/amd64/amd64/kgdb_machdep.c		kgdb
 file	kern/subr_disk_mbr.c			disk
 file	arch/amd64/amd64/gdt.c
-file	arch/x86/x86/idle_machdep.c
 #
 # XXXfvdl write the optimized versions for these.
 #
@@ -44,7 +43,6 @@
 file	arch/amd64/amd64/identcpu.c
 file	arch/amd64/amd64/math_emulate.c	math_emulate
 file	arch/amd64/amd64/mem.c
-file	arch/x86/x86/pmap.c
 file	arch/amd64/amd64/process_machdep.c
 file	arch/amd64/amd64/procfs_machdep.c	procfs
 file	arch/amd64/amd64/syscall.c
@@ -91,10 +89,6 @@
 attach	mainbus at root
 file	arch/amd64/amd64/mainbus.c		mainbus
 
-device cpu
-attach cpu at cpubus
-file	arch/x86/x86/cpu.c		cpu
-
 include "dev/wsfb/files.wsfb"
 
 #
@@ -106,13 +100,9 @@
 include	"dev/pci/files.pci"
 defparam			PCI_CONF_MODE
 include "dev/pci/files.agp"
-file	arch/x86/pci/agp_machdep.c	agp
 
-# PCI-Host bridge chipsets
-device	pchb: pcibus, agpbus, agp_i810, agp_intel, agp_sis, agp_via, agp_amd, agp_ali, agp_amd64
-attach	pchb at pci
-file	arch/amd64/pci/pchb.c			pchb		needs-flag
-file	arch/x86/pci/pchb_rnd.c			pchb & rnd
+# x86 specific PCI hardware
+include "arch/x86/pci/files.pci"
 
 # PCI-ISA bridges
 device	pcib: isabus
@@ -126,14 +116,6 @@
 attach 	hpet at amdpcib with amdpcib_hpet
 file 	arch/amd64/pci/amdpcib_hpet.c		amdpcib_hpet
 
-device  ichlpcib: acpipmtimer, isabus, sysmon_wdog
-attach  ichlpcib at pci
-file    arch/x86/pci/ichlpcib.c 		ichlpcib
-
-device 	aapic
-attach 	aapic at pci
-file 	arch/x86/pci/aapic.c			aapic
-
 #
 # ISA or ISA+PCI drivers
 #
@@ -141,7 +123,7 @@
 include	"dev/isa/files.isa"
 
 # PC clock
-file	arch/x86/isa/clock.c			isa
+file 	arch/x86/isa/clock.c 			isa
 
 # TSC timecounter support
 file	arch/x86/x86/tsc.c
--- a/sys/arch/amd64/pci/pchb.c	Fri Oct 26 21:09:49 2007 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,189 +0,0 @@
-/*	$NetBSD: pchb.c,v 1.7 2006/12/18 12:07:40 christos Exp $	*/
-
-/*-
- * Copyright (c) 1996, 1998, 2000 The NetBSD Foundation, Inc.
- * All rights reserved.
- *
- * This code is derived from software contributed to The NetBSD Foundation
- * by Jason R. Thorpe.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. All advertising materials mentioning features or use of this software
- *    must display the following acknowledgement:
- *        This product includes software developed by the NetBSD
- *        Foundation, Inc. and its contributors.
- * 4. Neither the name of The NetBSD Foundation nor the names of its
- *    contributors may be used to endorse or promote products derived
- *    from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
- * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
- * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
- * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
- * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- */
-
-#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: pchb.c,v 1.7 2006/12/18 12:07:40 christos Exp $");
-
-#include <sys/types.h>
-#include <sys/param.h>
-#include <sys/systm.h>
-#include <sys/device.h>
-
-#include <machine/bus.h>
-
-#include <dev/pci/pcivar.h>
-#include <dev/pci/pcireg.h>
-
-#include <dev/pci/pcidevs.h>
-
-#include <arch/x86/pci/pchbvar.h>
-
-#include <dev/pci/agpreg.h>
-#include <dev/pci/agpvar.h>
-
-#include "rnd.h"
-
-#define PCISET_BRIDGETYPE_MASK	0x3
-#define PCISET_TYPE_COMPAT	0x1
-#define PCISET_TYPE_AUX		0x2
-
-#define PCISET_BUSCONFIG_REG	0x48
-#define PCISET_BRIDGE_NUMBER(reg)	(((reg) >> 8) & 0xff)
-#define PCISET_PCI_BUS_NUMBER(reg)	(((reg) >> 16) & 0xff)
-
-/* XXX should be in dev/ic/i82443reg.h */
-#define	I82443BX_SDRAMC_REG	0x76
-
-/* XXX should be in dev/ic/i82424{reg.var}.h */
-#define I82424_CPU_BCTL_REG		0x53
-#define I82424_PCI_BCTL_REG		0x54
-
-#define I82424_BCTL_CPUMEM_POSTEN	0x01
-#define I82424_BCTL_CPUPCI_POSTEN	0x02
-#define I82424_BCTL_PCIMEM_BURSTEN	0x01
-#define I82424_BCTL_PCI_BURSTEN		0x02
-
-int	pchbmatch(struct device *, struct cfdata *, void *);
-void	pchbattach(struct device *, struct device *, void *);
-
-CFATTACH_DECL(pchb, sizeof(struct pchb_softc),
-    pchbmatch, pchbattach, NULL, NULL);
-
-int
-pchbmatch(struct device *parent, struct cfdata *match, void *aux)
-{
-	struct pci_attach_args *pa = aux;
-
-	if (PCI_CLASS(pa->pa_class) == PCI_CLASS_BRIDGE &&
-	    PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_BRIDGE_HOST) {
-		return (1);
-	}
-
-	return (0);
-}
-
-void
-pchbattach(struct device *parent, struct device *self, void *aux)
-{
-#if NRND > 0
-	struct pchb_softc *sc = (void *) self;
-#endif
-	struct pci_attach_args *pa = aux;
-	char devinfo[256];
-	struct pcibus_attach_args pba;
-	struct agpbus_attach_args apa;
-	u_char pbnum = 0; /* XXX: gcc */
-	int doattach, attachflags, has_agp;
-
-	printf("\n");
-
-	doattach = 0;
-	has_agp = 0;
-	attachflags = pa->pa_flags;
-
-	/*
-	 * Print out a description, and configure certain chipsets which
-	 * have auxiliary PCI buses.
-	 */
-
-	pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo, sizeof(devinfo));
-	printf("%s: %s (rev. 0x%02x)\n", self->dv_xname, devinfo,
-	    PCI_REVISION(pa->pa_class));
-	switch (PCI_VENDOR(pa->pa_id)) {
-	case PCI_VENDOR_INTEL:
-		switch (PCI_PRODUCT(pa->pa_id)) {
-		case PCI_PRODUCT_INTEL_82810_MCH:
-		case PCI_PRODUCT_INTEL_82810_DC100_MCH:
-		case PCI_PRODUCT_INTEL_82810E_MCH:
-		case PCI_PRODUCT_INTEL_82815_FULL_HUB:
-		case PCI_PRODUCT_INTEL_82830MP_IO_1:
-		case PCI_PRODUCT_INTEL_82845G_DRAM:
-		case PCI_PRODUCT_INTEL_82855GM_MCH:
-		case PCI_PRODUCT_INTEL_82865_HB:
-		case PCI_PRODUCT_INTEL_82915G_HB:
-		case PCI_PRODUCT_INTEL_82915GM_HB:
-		case PCI_PRODUCT_INTEL_82945P_MCH:
-		case PCI_PRODUCT_INTEL_82945GM_HB:
-			/*
-			 * The host bridge is either in GFX mode (internal
-			 * graphics) or in AGP mode. In GFX mode, we pretend
-			 * to have AGP because the graphics memory access
-			 * is very similar and the AGP GATT code will
-			 * deal with this. In the latter case, the
-			 * pci_get_capability(PCI_CAP_AGP) test below will
-			 * fire, so we do no harm by already setting the flag.
-			 */
-			has_agp = 1;
-			break;
-		}
-		break;
-	}
-
-#if NRND > 0
-	/*
-	 * Attach a random number generator, if there is one.
-	 */
-	pchb_attach_rnd(sc, pa);
-#endif
-
-	/*
-	 * If we haven't detected AGP yet (via a product ID),
-	 * then check for AGP capability on the device.
-	 */
-	if (has_agp ||
-	    pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_AGP,
-			       NULL, NULL) != 0) {
-		apa.apa_pci_args = *pa;
-		config_found_ia(self, "agpbus", &apa, agpbusprint);
-	}
-
-	if (doattach) {
-		pba.pba_iot = pa->pa_iot;
-		pba.pba_memt = pa->pa_memt;
-		pba.pba_dmat = pa->pa_dmat;
-		pba.pba_dmat64 = pa->pa_dmat64;
-		pba.pba_pc = pa->pa_pc;
-		pba.pba_flags = attachflags;
-		pba.pba_bus = pbnum;
-		pba.pba_bridgetag = NULL;
-		pba.pba_pc = pa->pa_pc;
-		pba.pba_intrswiz = 0;
-		memset(&pba.pba_intrtag, 0, sizeof(pba.pba_intrtag));
-		config_found_ia(self, "pcibus", &pba, pcibusprint);
-	}
-}
--- a/sys/arch/i386/conf/files.i386	Fri Oct 26 21:09:49 2007 +0000
+++ b/sys/arch/i386/conf/files.i386	Fri Oct 26 21:49:50 2007 +0000
@@ -1,4 +1,4 @@
-#	$NetBSD: files.i386,v 1.317 2007/10/18 15:28:34 yamt Exp $
+#	$NetBSD: files.i386,v 1.318 2007/10/26 21:49:50 xtraeme Exp $
 #
 # new style config file for i386 architecture
 #
@@ -50,18 +50,18 @@
 defflag	opt_kstack_dr0.h		KSTACK_CHECK_DR0
 
 # Beep on halt
-defflag opt_beep.h		BEEP_ONHALT
-defparam opt_beep.h		BEEP_ONHALT_COUNT=3
-defparam opt_beep.h		BEEP_ONHALT_PITCH=1500
-defparam opt_beep.h		BEEP_ONHALT_PERIOD=250
+defflag 	opt_beep.h		BEEP_ONHALT
+defparam 	opt_beep.h		BEEP_ONHALT_COUNT=3
+defparam 	opt_beep.h		BEEP_ONHALT_PITCH=1500
+defparam 	opt_beep.h		BEEP_ONHALT_PERIOD=250
 
 # Multiboot support
-defflag opt_multiboot.h		MULTIBOOT
-obsolete defparam		MULTIBOOT_SYMTAB_SPACE
-file	arch/i386/i386/multiboot.c	multiboot
+defflag 	opt_multiboot.h		MULTIBOOT
+obsolete 	defparam		MULTIBOOT_SYMTAB_SPACE
+file 	arch/i386/i386/multiboot.c	multiboot
 
 # PowerNow K7
-defflag			POWERNOW_K7
+defflag 	POWERNOW_K7
 
 file	arch/i386/i386/autoconf.c
 file	arch/i386/i386/busfunc.S
@@ -74,7 +74,6 @@
 file	kern/subr_disk_mbr.c		disk
 file	arch/i386/i386/gdt.c
 file	arch/i386/i386/i386func.S
-file	arch/x86/x86/idle_machdep.c
 file	arch/i386/i386/in_cksum.S	inet | inet6
 file	arch/i386/i386/ipkdb_glue.c	ipkdb
 file	arch/i386/i386/kgdb_machdep.c	kgdb
@@ -83,7 +82,6 @@
 file	arch/i386/i386/math_emulate.c	math_emulate
 file	arch/i386/i386/mem.c
 file	arch/i386/i386/mtrr_k6.c	mtrr
-file	arch/x86/x86/pmap.c
 file	arch/i386/i386/process_machdep.c
 file	arch/i386/i386/procfs_machdep.c	procfs
 file	arch/i386/i386/syscall.c
@@ -133,9 +131,9 @@
 file	arch/i386/i386/bios32.c		bios32 needs-flag
 
 # i386 specific mainbus attributes
-define apmbus {}
-define pnpbiosbus {}
-define vesabiosbus {}
+define	apmbus {}
+define	pnpbiosbus {}
+define	vesabiosbus {}
 
 #
 # System bus types
@@ -156,7 +154,6 @@
 
 include	"dev/pci/files.pci"
 include "dev/pci/files.agp"
-file 	arch/x86/pci/agp_machdep.c	agp
 file	arch/i386/pci/pcibios.c		pcibios
 file	arch/i386/pci/pci_intr_fixup.c	pcibios & pci_intr_fixup
 file	arch/i386/pci/piix.c		pcibios & pci_intr_fixup
@@ -172,16 +169,8 @@
 defparam		PCI_CONF_MODE
 file	arch/i386/pci/pcic_pci_machdep.c	pcic_pci
 
-device 	aapic
-attach 	aapic at pci
-file 	arch/x86/pci/aapic.c			aapic
-
-# PCI-Host bridge chipsets
-device	pchb: pcibus, agpbus, agp_ali, agp_amd, agp_i810, agp_intel, agp_sis,
-	      agp_via
-attach	pchb at pci
-file	arch/i386/pci/pchb.c		pchb			needs-flag
-file	arch/x86/pci/pchb_rnd.c		pchb & rnd
+# x86 specific PCI hardware
+include "arch/x86/pci/files.pci"
 
 # AMD Elan SC520 System Controller (PCI-Host bridge)
 device	elansc: sysmon_wdog, gpiobus
@@ -224,10 +213,6 @@
 file	arch/i386/pci/pcib.c		pcib | ichlpcib | gscpcib | piixpcib | viapcib
 
 # PCI-LPC bridges
-device	ichlpcib: acpipmtimer, isabus, sysmon_wdog
-attach	ichlpcib at pci
-file 	arch/x86/pci/ichlpcib.c 	ichlpcib
-
 device	gscpcib: isabus, gpiobus
 attach	gscpcib at pci
 file	arch/i386/pci/gscpcib.c		gscpcib
@@ -352,12 +337,6 @@
 file	arch/i386/i386/apmbios.c	apmbios	needs-flag
 file	arch/i386/i386/apmcall.S	apmbios
 
-# CPUS
-
-device cpu
-attach cpu at cpubus
-file	arch/x86/x86/cpu.c		cpu
-
 # XBox LED & system support
 file	arch/i386/xbox/xbox.c			xbox
 
@@ -365,8 +344,8 @@
 file	arch/i386/xbox/xboxlcd.c		xbox
 
 # XBox framebuffer support
-device xboxfb: wsemuldisplaydev, rasops32, vcons
-attach xboxfb at pci
+device	xboxfb: wsemuldisplaydev, rasops32, vcons
+attach	xboxfb at pci
 file	arch/i386/xbox/xboxfb.c			xboxfb needs-flag
 
 #
@@ -524,24 +503,24 @@
 file	arch/i386/acpi/npx_acpi.c		npx_acpi
 
 device	vesabios {}
-attach vesabios at vesabiosbus
+attach	vesabios at vesabiosbus
 file	arch/i386/bios/vesabios.c		vesabios needs-flag
 defflag	opt_vesabios.h	VESABIOSVERBOSE
 
 include	"dev/rasops/files.rasops"
 
-device vesafb: wsemuldisplaydev, vcons, rasops8, rasops16, rasops32, splash, bioscall
-attach vesafb at vesabios
+device	vesafb: wsemuldisplaydev, vcons, rasops8, rasops16, rasops32, splash, bioscall
+attach	vesafb at vesabios
 file	arch/i386/bios/vesafb.c		vesafb needs-flag
-defparam opt_vesafb.h	VESAFB_WIDTH VESAFB_HEIGHT VESAFB_DEPTH
-defflag opt_vesafb.h	VESAFB_PM
+defparam 	opt_vesafb.h	VESAFB_WIDTH VESAFB_HEIGHT VESAFB_DEPTH
+defflag 	opt_vesafb.h	VESAFB_PM
 
-device vesatext
-attach vesatext at vesabios
+device	vesatext
+attach	vesatext at vesabios
 file	arch/i386/bios/vesa_text.c	vesatext
 
 # AMD PowerNow K7
-file   arch/i386/i386/powernow_k7.c	powernow_k7
+file	arch/i386/i386/powernow_k7.c	powernow_k7
 
 # AMD Geode LX Security Block
 device	glxsb: opencrypto
--- a/sys/arch/i386/pci/pchb.c	Fri Oct 26 21:09:49 2007 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,367 +0,0 @@
-/*	$NetBSD: pchb.c,v 1.66 2007/10/17 19:54:58 garbled Exp $	*/
-
-/*-
- * Copyright (c) 1996, 1998, 2000 The NetBSD Foundation, Inc.
- * All rights reserved.
- *
- * This code is derived from software contributed to The NetBSD Foundation
- * by Jason R. Thorpe.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. All advertising materials mentioning features or use of this software
- *    must display the following acknowledgement:
- *        This product includes software developed by the NetBSD
- *        Foundation, Inc. and its contributors.
- * 4. Neither the name of The NetBSD Foundation nor the names of its
- *    contributors may be used to endorse or promote products derived
- *    from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
- * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
- * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
- * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
- * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- */
-
-#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: pchb.c,v 1.66 2007/10/17 19:54:58 garbled Exp $");
-
-#include <sys/types.h>
-#include <sys/param.h>
-#include <sys/systm.h>
-#include <sys/device.h>
-
-#include <machine/bus.h>
-
-#include <dev/pci/pcivar.h>
-#include <dev/pci/pcireg.h>
-
-#include <dev/pci/pcidevs.h>
-
-#include <dev/pci/agpreg.h>
-#include <dev/pci/agpvar.h>
-
-#include <arch/x86/pci/pchbvar.h>
-
-#include "rnd.h"
-
-#define PCISET_BRIDGETYPE_MASK	0x3
-#define PCISET_TYPE_COMPAT	0x1
-#define PCISET_TYPE_AUX		0x2
-
-#define PCISET_BUSCONFIG_REG	0x48
-#define PCISET_BRIDGE_NUMBER(reg)	(((reg) >> 8) & 0xff)
-#define PCISET_PCI_BUS_NUMBER(reg)	(((reg) >> 16) & 0xff)
-
-/* XXX should be in dev/ic/i82443reg.h */
-#define	I82443BX_SDRAMC_REG	0x76
-
-/* XXX should be in dev/ic/i82424{reg.var}.h */
-#define I82424_CPU_BCTL_REG		0x53
-#define I82424_PCI_BCTL_REG		0x54
-
-#define I82424_BCTL_CPUMEM_POSTEN	0x01
-#define I82424_BCTL_CPUPCI_POSTEN	0x02
-#define I82424_BCTL_PCIMEM_BURSTEN	0x01
-#define I82424_BCTL_PCI_BURSTEN		0x02
-
-int	pchbmatch(struct device *, struct cfdata *, void *);
-void	pchbattach(struct device *, struct device *, void *);
-
-CFATTACH_DECL(pchb, sizeof(struct pchb_softc),
-    pchbmatch, pchbattach, NULL, NULL);
-
-int
-pchbmatch(struct device *parent, struct cfdata *match,
-    void *aux)
-{
-	struct pci_attach_args *pa = aux;
-
-	if (PCI_CLASS(pa->pa_class) == PCI_CLASS_BRIDGE &&
-	    PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_BRIDGE_HOST) {
-		return (1);
-	}
-
-	return (0);
-}
-
-void
-pchbattach(struct device *parent, struct device *self, void *aux)
-{
-#if NRND > 0
-	struct pchb_softc *sc = (void *) self;
-#endif
-	struct pci_attach_args *pa = aux;
-	char devinfo[256];
-	struct pcibus_attach_args pba;
-	struct agpbus_attach_args apa;
-	pcireg_t bcreg;
-	u_char bdnum, pbnum = 0; /* XXX: gcc */
-	pcitag_t tag;
-	int doattach, attachflags, has_agp;
-
-	aprint_naive("\n");
-	aprint_normal("\n");
-
-	doattach = 0;
-	has_agp = 0;
-	attachflags = pa->pa_flags;
-
-	/*
-	 * Print out a description, and configure certain chipsets which
-	 * have auxiliary PCI buses.
-	 */
-
-	pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo, sizeof(devinfo));
-	aprint_normal("%s: %s (rev. 0x%02x)\n", self->dv_xname, devinfo,
-	    PCI_REVISION(pa->pa_class));
-	switch (PCI_VENDOR(pa->pa_id)) {
-	case PCI_VENDOR_SERVERWORKS:
-		pbnum = pci_conf_read(pa->pa_pc, pa->pa_tag, 0x44) & 0xff;
-
-		if (pbnum == 0)
-			break;
-
-		/*
-		 * This host bridge has a second PCI bus.
-		 * Configure it.
-		 */
-		switch (PCI_PRODUCT(pa->pa_id)) {
-		case PCI_PRODUCT_SERVERWORKS_CSB5:
-		case PCI_PRODUCT_SERVERWORKS_CSB6:
-			/* These devices show up as host bridges, but are
-			   really southbridges. */
-			break;
-		case PCI_PRODUCT_SERVERWORKS_CMIC_HE:
-		case PCI_PRODUCT_SERVERWORKS_CMIC_LE:
-		case PCI_PRODUCT_SERVERWORKS_CMIC_SL:
-			/* CNBs and CIOBs are connected to these using a
-			   private bus.  The bus number register is that of
-			   the first PCI bus hanging off the CIOB.  We let
-			   the CIOB attachment handle configuring the PCI
-			   buses. */
-			break;
-		default:
-			aprint_error("%s: unknown ServerWorks chip ID 0x%04x; trying to attach PCI buses behind it\n", self->dv_xname, PCI_PRODUCT(pa->pa_id));
-			/* FALLTHROUGH */
-		case PCI_PRODUCT_SERVERWORKS_CNB20_LE_AGP:
-		case PCI_PRODUCT_SERVERWORKS_CNB30_LE_PCI:
-		case PCI_PRODUCT_SERVERWORKS_CNB20_LE_PCI:
-		case PCI_PRODUCT_SERVERWORKS_CNB20_HE_PCI:
-		case PCI_PRODUCT_SERVERWORKS_CNB20_HE_AGP:
-		case PCI_PRODUCT_SERVERWORKS_CIOB_X:
-		case PCI_PRODUCT_SERVERWORKS_CNB30_HE:
-		case PCI_PRODUCT_SERVERWORKS_CNB20_HE_PCI2:
-		case PCI_PRODUCT_SERVERWORKS_CIOB_X2:
-		case PCI_PRODUCT_SERVERWORKS_CIOB_E:
-			switch (attachflags & (PCI_FLAGS_IO_ENABLED | PCI_FLAGS_MEM_ENABLED)) {
-			case 0:
-				/* Doesn't smell like there's anything there. */
-				break;
-			case PCI_FLAGS_MEM_ENABLED:
-				attachflags |= PCI_FLAGS_IO_ENABLED;
-				/* FALLTHROUGH */
-			default:
-				doattach = 1;
-				break;
-			}
-			break;
-		}
-		break;
-
-	case PCI_VENDOR_INTEL:
-		switch (PCI_PRODUCT(pa->pa_id)) {
-		case PCI_PRODUCT_INTEL_82452_PB:
-			bcreg = pci_conf_read(pa->pa_pc, pa->pa_tag, 0x40);
-			pbnum = PCISET_BRIDGE_NUMBER(bcreg);
-			if (pbnum != 0xff) {
-				pbnum++;
-				doattach = 1;
-			}
-			break;
-		case PCI_PRODUCT_INTEL_82443BX_AGP:
-		case PCI_PRODUCT_INTEL_82443BX_NOAGP:
-		/*
-		 * http://www.intel.com/design/chipsets/specupdt/290639.htm
-		 * says this bug is fixed in steppings >= C0 (erratum 11),
-		 * so don't tweak the bits in that case.
-		 */
-			if (!(PCI_REVISION(pa->pa_class) >= 0x03)) {
-				/*
-				 * BIOS BUG WORKAROUND!  The 82443BX
-				 * datasheet indicates that the only
-				 * legal setting for the "Idle/Pipeline
-				 * DRAM Leadoff Timing (IPLDT)" parameter
-				 * (bits 9:8) is 01.  Unfortunately, some
-				 * BIOSs do not set these bits properly.
-				 */
-				bcreg = pci_conf_read(pa->pa_pc, pa->pa_tag,
-				    I82443BX_SDRAMC_REG);
-				if ((bcreg & 0x0300) != 0x0100) {
-					aprint_verbose("%s: fixing "
-					    "Idle/Pipeline DRAM "
-					    "Leadoff Timing\n", self->dv_xname);
-					bcreg &= ~0x0300;
-					bcreg |=  0x0100;
-					pci_conf_write(pa->pa_pc, pa->pa_tag,
-					    I82443BX_SDRAMC_REG, bcreg);
-				}
-			}
-			break;
-
-		case PCI_PRODUCT_INTEL_PCI450_PB:
-			bcreg = pci_conf_read(pa->pa_pc, pa->pa_tag,
-					      PCISET_BUSCONFIG_REG);
-			bdnum = PCISET_BRIDGE_NUMBER(bcreg);
-			pbnum = PCISET_PCI_BUS_NUMBER(bcreg);
-			switch (bdnum & PCISET_BRIDGETYPE_MASK) {
-			default:
-				aprint_error("%s: bdnum=%x (reserved)\n",
-				       self->dv_xname, bdnum);
-				break;
-			case PCISET_TYPE_COMPAT:
-				aprint_verbose(
-				    "%s: Compatibility PB (bus %d)\n",
-				    self->dv_xname, pbnum);
-				break;
-			case PCISET_TYPE_AUX:
-				aprint_verbose("%s: Auxiliary PB (bus %d)\n",
-				       self->dv_xname, pbnum);
-				/*
-				 * This host bridge has a second PCI bus.
-				 * Configure it.
-				 */
-				doattach = 1;
-				break;
-			}
-			break;
-		case PCI_PRODUCT_INTEL_CDC:
-			bcreg = pci_conf_read(pa->pa_pc, pa->pa_tag,
-					      I82424_CPU_BCTL_REG);
-			if (bcreg & I82424_BCTL_CPUPCI_POSTEN) {
-				bcreg &= ~I82424_BCTL_CPUPCI_POSTEN;
-				pci_conf_write(pa->pa_pc, pa->pa_tag,
-					       I82424_CPU_BCTL_REG, bcreg);
-				aprint_verbose(
-				    "%s: disabled CPU-PCI write posting\n",
-				    self->dv_xname);
-			}
-			break;
-		case PCI_PRODUCT_INTEL_82451NX_PXB:
-			/*
-			 * The NX chipset supports up to 2 "PXB" chips
-			 * which can drive 2 PCI buses each. Each bus
-			 * shows up as logical PCI device, with fixed
-			 * device numbers between 18 and 21.
-			 * See the datasheet at
-		ftp://download.intel.com/design/chipsets/datashts/24377102.pdf
-			 * for details.
-			 * (It would be easier to attach all the buses
-			 * at the MIOC, but less aesthetical imho.)
-			 */
-			if ((attachflags &
-			    (PCI_FLAGS_IO_ENABLED | PCI_FLAGS_MEM_ENABLED)) ==
-			    PCI_FLAGS_MEM_ENABLED)
-				attachflags |= PCI_FLAGS_IO_ENABLED;
-
-			pbnum = 0;
-			switch (pa->pa_device) {
-			case 18: /* PXB 0 bus A - primary bus */
-				break;
-			case 19: /* PXB 0 bus B */
-				/* read SUBA0 from MIOC */
-				tag = pci_make_tag(pa->pa_pc, 0, 16, 0);
-				bcreg = pci_conf_read(pa->pa_pc, tag, 0xd0);
-				pbnum = ((bcreg & 0x0000ff00) >> 8) + 1;
-				break;
-			case 20: /* PXB 1 bus A */
-				/* read BUSNO1 from MIOC */
-				tag = pci_make_tag(pa->pa_pc, 0, 16, 0);
-				bcreg = pci_conf_read(pa->pa_pc, tag, 0xd0);
-				pbnum = (bcreg & 0xff000000) >> 24;
-				break;
-			case 21: /* PXB 1 bus B */
-				/* read SUBA1 from MIOC */
-				tag = pci_make_tag(pa->pa_pc, 0, 16, 0);
-				bcreg = pci_conf_read(pa->pa_pc, tag, 0xd4);
-				pbnum = (bcreg & 0x000000ff) + 1;
-				break;
-			}
-			if (pbnum != 0)
-				doattach = 1;
-			break;
-
-		case PCI_PRODUCT_INTEL_82810_MCH:
-		case PCI_PRODUCT_INTEL_82810_DC100_MCH:
-		case PCI_PRODUCT_INTEL_82810E_MCH:
-		case PCI_PRODUCT_INTEL_82815_FULL_HUB:
-		case PCI_PRODUCT_INTEL_82830MP_IO_1:
-		case PCI_PRODUCT_INTEL_82845G_DRAM:
-		case PCI_PRODUCT_INTEL_82855GM_MCH:
-		case PCI_PRODUCT_INTEL_82865_HB:
-		case PCI_PRODUCT_INTEL_82915G_HB:
-		case PCI_PRODUCT_INTEL_82915GM_HB:
-		case PCI_PRODUCT_INTEL_82945P_MCH:
-		case PCI_PRODUCT_INTEL_82945GM_HB:
-		case PCI_PRODUCT_INTEL_82965Q_HB:
-			/*
-			 * The host bridge is either in GFX mode (internal
-			 * graphics) or in AGP mode. In GFX mode, we pretend
-			 * to have AGP because the graphics memory access
-			 * is very similar and the AGP GATT code will
-			 * deal with this. In the latter case, the
-			 * pci_get_capability(PCI_CAP_AGP) test below will
-			 * fire, so we do no harm by already setting the flag.
-			 */
-			has_agp = 1;
-			break;
-		}
-		break;
-	}
-
-#if NRND > 0
-	/*
-	 * Attach a random number generator, if there is one.
-	 */
-	pchb_attach_rnd(sc, pa);
-#endif
-
-	/*
-	 * If we haven't detected AGP yet (via a product ID),
-	 * then check for AGP capability on the device.
-	 */
-	if (has_agp ||
-	    pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_AGP,
-			       NULL, NULL) != 0) {
-		apa.apa_pci_args = *pa;
-		config_found_ia(self, "agpbus", &apa, agpbusprint);
-	}
-
-	if (doattach) {
-		pba.pba_iot = pa->pa_iot;
-		pba.pba_memt = pa->pa_memt;
-		pba.pba_dmat = pa->pa_dmat;
-		pba.pba_dmat64 = pa->pa_dmat64;
-		pba.pba_pc = pa->pa_pc;
-		pba.pba_flags = attachflags;
-		pba.pba_bus = pbnum;
-		pba.pba_bridgetag = NULL;
-		pba.pba_pc = pa->pa_pc;
-		pba.pba_intrswiz = 0;
-		memset(&pba.pba_intrtag, 0, sizeof(pba.pba_intrtag));
-		config_found_ia(self, "pcibus", &pba, pcibusprint);
-	}
-}
--- a/sys/arch/x86/conf/files.x86	Fri Oct 26 21:09:49 2007 +0000
+++ b/sys/arch/x86/conf/files.x86	Fri Oct 26 21:49:50 2007 +0000
@@ -1,4 +1,4 @@
-#	$NetBSD: files.x86,v 1.31 2007/10/17 19:58:14 garbled Exp $
+#	$NetBSD: files.x86,v 1.32 2007/10/26 21:49:52 xtraeme Exp $
 
 # options for MP configuration through the MP spec
 defflag opt_mpbios.h MPBIOS MPVERBOSE MPDEBUG MPBIOS_SCANPCI
@@ -31,6 +31,13 @@
 define  ioapicbus { [apid = -1] }
 define  ipmibus {}
 
+#
+# CPUs
+#
+device	cpu
+attach	cpu at cpubus
+file 	arch/x86/x86/cpu.c 		cpu
+
 file	arch/x86/x86/apic.c		ioapic | lapic
 file	arch/x86/x86/bus_dma.c
 file	arch/x86/x86/bus_space.c
@@ -38,22 +45,24 @@
 file	arch/x86/x86/consinit.c
 file	arch/x86/x86/errata.c
 file	arch/x86/x86/i8259.c
+file	arch/x86/x86/idle_machdep.c
 file	arch/x86/x86/intr.c
 file	arch/x86/x86/ipi.c		multiprocessor
 file	arch/x86/x86/lock_machdep.c	lockdebug
 file	arch/x86/x86/msr_ipifuncs.c
 file	arch/x86/x86/mtrr_i686.c	mtrr
 file 	arch/x86/x86/patch.c
+file 	arch/x86/x86/pmap.c
 file	arch/x86/x86/softintr.c
 file	arch/x86/x86/sys_machdep.c
 file	arch/x86/x86/x86_autoconf.c
 file	arch/x86/x86/x86_machdep.c
 
-define lapic
+define	lapic
 file	arch/x86/x86/lapic.c		lapic needs-flag
 
-device ioapic: lapic
-attach ioapic at ioapicbus
+device	ioapic: lapic
+attach	ioapic at ioapicbus
 file	arch/x86/x86/ioapic.c		ioapic needs-flag
 
 # MP configuration using Intel SMP specification 1.4
@@ -64,13 +73,8 @@
 
 file    arch/x86/x86/acpi_machdep.c	acpi
 
-file	arch/x86/pci/pci_machdep.c	pci
-file	arch/x86/pci/pci_intr_machdep.c	pci
-
 file	arch/x86/isa/isa_machdep.c	isa
 
-file	arch/x86/pci/pciide_machdep.c	pciide_common
-
 # Powernow common functions
 file	arch/x86/x86/powernow_k8.c	powernow_k8
 file	arch/x86/x86/powernow_common.c	powernow_k8 | powernow_k7
@@ -83,6 +87,6 @@
 file	arch/x86/x86/intel_busclock.c	enhanced_speedstep
 
 # IPMI device
-device ipmi : sysmon_envsys, sysmon_wdog
-attach ipmi at ipmibus
+device	ipmi: sysmon_envsys, sysmon_wdog
+attach	ipmi at ipmibus
 file	arch/x86/x86/ipmi.c		ipmi needs-flag
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/sys/arch/x86/pci/files.pci	Fri Oct 26 21:49:50 2007 +0000
@@ -0,0 +1,25 @@
+#	$NetBSD: files.pci,v 1.2 2007/10/26 21:49:52 xtraeme Exp $
+
+device 	aapic
+attach 	aapic at pci
+file 	arch/x86/pci/aapic.c		aapic
+
+file	arch/x86/pci/agp_machdep.c	agp
+
+file	arch/x86/pci/pci_machdep.c	pci
+file	arch/x86/pci/pci_intr_machdep.c	pci
+
+file	arch/x86/pci/pciide_machdep.c	pciide_common
+
+# PCI-Host bridge chipsets
+device	pchb:	pcibus, agpbus, agp_ali, agp_amd, agp_amd64, agp_i810,
+		agp_intel, agp_sis, agp_via
+attach	pchb at pci
+file	arch/x86/pci/pchb.c		pchb		needs-flag
+file	arch/x86/pci/pchb_rnd.c		pchb & rnd
+
+# PCI-LPC bridges
+device	ichlpcib: acpipmtimer, isabus, sysmon_wdog
+attach	ichlpcib at pci
+
+file 	arch/x86/pci/ichlpcib.c 	ichlpcib
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/sys/arch/x86/pci/pchb.c	Fri Oct 26 21:49:50 2007 +0000
@@ -0,0 +1,374 @@
+/*	$NetBSD: pchb.c,v 1.1 2007/10/26 21:49:52 xtraeme Exp $ */
+
+/*-
+ * Copyright (c) 1996, 1998, 2000 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by Jason R. Thorpe.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *        This product includes software developed by the NetBSD
+ *        Foundation, Inc. and its contributors.
+ * 4. Neither the name of The NetBSD Foundation nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>
+__KERNEL_RCSID(0, "$NetBSD: pchb.c,v 1.1 2007/10/26 21:49:52 xtraeme Exp $");
+
+#include <sys/types.h>
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/device.h>
+
+#include <machine/bus.h>
+
+#include <dev/pci/pcivar.h>
+#include <dev/pci/pcireg.h>
+
+#include <dev/pci/pcidevs.h>
+
+#include <dev/pci/agpreg.h>
+#include <dev/pci/agpvar.h>
+
+#include <arch/x86/pci/pchbvar.h>
+
+#include "rnd.h"
+
+#define PCISET_BRIDGETYPE_MASK	0x3
+#define PCISET_TYPE_COMPAT	0x1
+#define PCISET_TYPE_AUX		0x2
+
+#define PCISET_BUSCONFIG_REG	0x48
+#define PCISET_BRIDGE_NUMBER(reg)	(((reg) >> 8) & 0xff)
+#define PCISET_PCI_BUS_NUMBER(reg)	(((reg) >> 16) & 0xff)
+
+/* XXX should be in dev/ic/i82443reg.h */
+#define	I82443BX_SDRAMC_REG	0x76
+
+/* XXX should be in dev/ic/i82424{reg.var}.h */
+#define I82424_CPU_BCTL_REG		0x53
+#define I82424_PCI_BCTL_REG		0x54
+
+#define I82424_BCTL_CPUMEM_POSTEN	0x01
+#define I82424_BCTL_CPUPCI_POSTEN	0x02
+#define I82424_BCTL_PCIMEM_BURSTEN	0x01
+#define I82424_BCTL_PCI_BURSTEN		0x02
+
+int	pchbmatch(struct device *, struct cfdata *, void *);
+void	pchbattach(struct device *, struct device *, void *);
+
+CFATTACH_DECL(pchb, sizeof(struct pchb_softc),
+    pchbmatch, pchbattach, NULL, NULL);
+
+int
+pchbmatch(struct device *parent, struct cfdata *match, void *aux)
+{
+	struct pci_attach_args *pa = aux;
+
+	if (PCI_CLASS(pa->pa_class) == PCI_CLASS_BRIDGE &&
+	    PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_BRIDGE_HOST)
+		return 1;
+
+	return 0;
+}
+
+void
+pchbattach(struct device *parent, struct device *self, void *aux)
+{
+#if NRND > 0
+	struct pchb_softc *sc = (void *) self;
+#endif
+	struct pci_attach_args *pa = aux;
+	char devinfo[256];
+	struct pcibus_attach_args pba;
+	struct agpbus_attach_args apa;
+	pcireg_t bcreg;
+	u_char bdnum, pbnum = 0; /* XXX: gcc */
+	pcitag_t tag;
+	int doattach, attachflags, has_agp;
+
+	aprint_naive("\n");
+	aprint_normal("\n");
+
+	doattach = 0;
+	has_agp = 0;
+	attachflags = pa->pa_flags;
+
+	/*
+	 * Print out a description, and configure certain chipsets which
+	 * have auxiliary PCI buses.
+	 */
+
+	pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo, sizeof(devinfo));
+	aprint_normal("%s: %s (rev. 0x%02x)\n", self->dv_xname, devinfo,
+	    PCI_REVISION(pa->pa_class));
+
+	switch (PCI_VENDOR(pa->pa_id)) {
+	/*
+	 * i386 stuff.
+	 */
+	case PCI_VENDOR_SERVERWORKS:
+		pbnum = pci_conf_read(pa->pa_pc, pa->pa_tag, 0x44) & 0xff;
+
+		if (pbnum == 0)
+			break;
+
+		/*
+		 * This host bridge has a second PCI bus.
+		 * Configure it.
+		 */
+		switch (PCI_PRODUCT(pa->pa_id)) {
+		case PCI_PRODUCT_SERVERWORKS_CSB5:
+		case PCI_PRODUCT_SERVERWORKS_CSB6:
+			/* These devices show up as host bridges, but are
+			   really southbridges. */
+			break;
+		case PCI_PRODUCT_SERVERWORKS_CMIC_HE:
+		case PCI_PRODUCT_SERVERWORKS_CMIC_LE:
+		case PCI_PRODUCT_SERVERWORKS_CMIC_SL:
+			/* CNBs and CIOBs are connected to these using a
+			   private bus.  The bus number register is that of
+			   the first PCI bus hanging off the CIOB.  We let
+			   the CIOB attachment handle configuring the PCI
+			   buses. */
+			break;
+		default:
+			aprint_error("%s: unknown ServerWorks chip ID "
+			    "0x%04x; trying to attach PCI buses behind it\n",
+			    self->dv_xname, PCI_PRODUCT(pa->pa_id));
+			/* FALLTHROUGH */
+		case PCI_PRODUCT_SERVERWORKS_CNB20_LE_AGP:
+		case PCI_PRODUCT_SERVERWORKS_CNB30_LE_PCI:
+		case PCI_PRODUCT_SERVERWORKS_CNB20_LE_PCI:
+		case PCI_PRODUCT_SERVERWORKS_CNB20_HE_PCI:
+		case PCI_PRODUCT_SERVERWORKS_CNB20_HE_AGP:
+		case PCI_PRODUCT_SERVERWORKS_CIOB_X:
+		case PCI_PRODUCT_SERVERWORKS_CNB30_HE:
+		case PCI_PRODUCT_SERVERWORKS_CNB20_HE_PCI2:
+		case PCI_PRODUCT_SERVERWORKS_CIOB_X2:
+		case PCI_PRODUCT_SERVERWORKS_CIOB_E:
+			switch (attachflags &
+			    (PCI_FLAGS_IO_ENABLED | PCI_FLAGS_MEM_ENABLED)) {
+			case 0:
+				/* Doesn't smell like there's anything there. */
+				break;
+			case PCI_FLAGS_MEM_ENABLED:
+				attachflags |= PCI_FLAGS_IO_ENABLED;
+				/* FALLTHROUGH */
+			default:
+				doattach = 1;
+				break;
+			}
+			break;
+		}
+		break;
+	case PCI_VENDOR_INTEL:
+		switch (PCI_PRODUCT(pa->pa_id)) {
+		case PCI_PRODUCT_INTEL_82452_PB:
+			bcreg = pci_conf_read(pa->pa_pc, pa->pa_tag, 0x40);
+			pbnum = PCISET_BRIDGE_NUMBER(bcreg);
+			if (pbnum != 0xff) {
+				pbnum++;
+				doattach = 1;
+			}
+			break;
+		case PCI_PRODUCT_INTEL_82443BX_AGP:
+		case PCI_PRODUCT_INTEL_82443BX_NOAGP:
+		/*
+		 * http://www.intel.com/design/chipsets/specupdt/290639.htm
+		 * says this bug is fixed in steppings >= C0 (erratum 11),
+		 * so don't tweak the bits in that case.
+		 */
+			if (!(PCI_REVISION(pa->pa_class) >= 0x03)) {
+				/*
+				 * BIOS BUG WORKAROUND!  The 82443BX
+				 * datasheet indicates that the only
+				 * legal setting for the "Idle/Pipeline
+				 * DRAM Leadoff Timing (IPLDT)" parameter
+				 * (bits 9:8) is 01.  Unfortunately, some
+				 * BIOSs do not set these bits properly.
+				 */
+				bcreg = pci_conf_read(pa->pa_pc, pa->pa_tag,
+				    I82443BX_SDRAMC_REG);
+				if ((bcreg & 0x0300) != 0x0100) {
+					aprint_verbose("%s: fixing "
+					    "Idle/Pipeline DRAM "
+					    "Leadoff Timing\n", self->dv_xname);
+					bcreg &= ~0x0300;
+					bcreg |=  0x0100;
+					pci_conf_write(pa->pa_pc, pa->pa_tag,
+					    I82443BX_SDRAMC_REG, bcreg);
+				}
+			}
+			break;
+
+		case PCI_PRODUCT_INTEL_PCI450_PB:
+			bcreg = pci_conf_read(pa->pa_pc, pa->pa_tag,
+					      PCISET_BUSCONFIG_REG);
+			bdnum = PCISET_BRIDGE_NUMBER(bcreg);
+			pbnum = PCISET_PCI_BUS_NUMBER(bcreg);
+			switch (bdnum & PCISET_BRIDGETYPE_MASK) {
+			default:
+				aprint_error("%s: bdnum=%x (reserved)\n",
+				       self->dv_xname, bdnum);
+				break;
+			case PCISET_TYPE_COMPAT:
+				aprint_verbose(
+				    "%s: Compatibility PB (bus %d)\n",
+				    self->dv_xname, pbnum);
+				break;
+			case PCISET_TYPE_AUX:
+				aprint_verbose("%s: Auxiliary PB (bus %d)\n",
+				       self->dv_xname, pbnum);
+				/*
+				 * This host bridge has a second PCI bus.
+				 * Configure it.
+				 */
+				doattach = 1;
+				break;
+			}
+			break;
+		case PCI_PRODUCT_INTEL_CDC:
+			bcreg = pci_conf_read(pa->pa_pc, pa->pa_tag,
+					      I82424_CPU_BCTL_REG);
+			if (bcreg & I82424_BCTL_CPUPCI_POSTEN) {
+				bcreg &= ~I82424_BCTL_CPUPCI_POSTEN;
+				pci_conf_write(pa->pa_pc, pa->pa_tag,
+					       I82424_CPU_BCTL_REG, bcreg);
+				aprint_verbose(
+				    "%s: disabled CPU-PCI write posting\n",
+				    self->dv_xname);
+			}
+			break;
+		case PCI_PRODUCT_INTEL_82451NX_PXB:
+			/*
+			 * The NX chipset supports up to 2 "PXB" chips
+			 * which can drive 2 PCI buses each. Each bus
+			 * shows up as logical PCI device, with fixed
+			 * device numbers between 18 and 21.
+			 * See the datasheet at
+		ftp://download.intel.com/design/chipsets/datashts/24377102.pdf
+			 * for details.
+			 * (It would be easier to attach all the buses
+			 * at the MIOC, but less aesthetical imho.)
+			 */
+			if ((attachflags &
+			    (PCI_FLAGS_IO_ENABLED | PCI_FLAGS_MEM_ENABLED)) ==
+			    PCI_FLAGS_MEM_ENABLED)
+				attachflags |= PCI_FLAGS_IO_ENABLED;
+
+			pbnum = 0;
+			switch (pa->pa_device) {
+			case 18: /* PXB 0 bus A - primary bus */
+				break;
+			case 19: /* PXB 0 bus B */
+				/* read SUBA0 from MIOC */
+				tag = pci_make_tag(pa->pa_pc, 0, 16, 0);
+				bcreg = pci_conf_read(pa->pa_pc, tag, 0xd0);
+				pbnum = ((bcreg & 0x0000ff00) >> 8) + 1;
+				break;
+			case 20: /* PXB 1 bus A */
+				/* read BUSNO1 from MIOC */
+				tag = pci_make_tag(pa->pa_pc, 0, 16, 0);
+				bcreg = pci_conf_read(pa->pa_pc, tag, 0xd0);
+				pbnum = (bcreg & 0xff000000) >> 24;
+				break;
+			case 21: /* PXB 1 bus B */
+				/* read SUBA1 from MIOC */
+				tag = pci_make_tag(pa->pa_pc, 0, 16, 0);
+				bcreg = pci_conf_read(pa->pa_pc, tag, 0xd4);
+				pbnum = (bcreg & 0x000000ff) + 1;
+				break;
+			}
+			if (pbnum != 0)
+				doattach = 1;
+			break;
+
+		/*
+		 * i386 and amd64 stuff.
+		 */
+		case PCI_PRODUCT_INTEL_82810_MCH:
+		case PCI_PRODUCT_INTEL_82810_DC100_MCH:
+		case PCI_PRODUCT_INTEL_82810E_MCH:
+		case PCI_PRODUCT_INTEL_82815_FULL_HUB:
+		case PCI_PRODUCT_INTEL_82830MP_IO_1:
+		case PCI_PRODUCT_INTEL_82845G_DRAM:
+		case PCI_PRODUCT_INTEL_82855GM_MCH:
+		case PCI_PRODUCT_INTEL_82865_HB:
+		case PCI_PRODUCT_INTEL_82915G_HB:
+		case PCI_PRODUCT_INTEL_82915GM_HB:
+		case PCI_PRODUCT_INTEL_82945P_MCH:
+		case PCI_PRODUCT_INTEL_82945GM_HB:
+		case PCI_PRODUCT_INTEL_82965Q_HB:
+			/*
+			 * The host bridge is either in GFX mode (internal
+			 * graphics) or in AGP mode. In GFX mode, we pretend
+			 * to have AGP because the graphics memory access
+			 * is very similar and the AGP GATT code will
+			 * deal with this. In the latter case, the
+			 * pci_get_capability(PCI_CAP_AGP) test below will
+			 * fire, so we do no harm by already setting the flag.
+			 */
+			has_agp = 1;
+			break;
+		}
+		break;
+	}
+
+#if NRND > 0
+	/*
+	 * Attach a random number generator, if there is one.
+	 */
+	pchb_attach_rnd(sc, pa);
+#endif
+
+	/*
+	 * If we haven't detected AGP yet (via a product ID),
+	 * then check for AGP capability on the device.
+	 */
+	if (has_agp ||
+	    pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_AGP,
+			       NULL, NULL) != 0) {
+		apa.apa_pci_args = *pa;
+		config_found_ia(self, "agpbus", &apa, agpbusprint);
+	}
+
+	if (doattach) {
+		pba.pba_iot = pa->pa_iot;
+		pba.pba_memt = pa->pa_memt;
+		pba.pba_dmat = pa->pa_dmat;
+		pba.pba_dmat64 = pa->pa_dmat64;
+		pba.pba_pc = pa->pa_pc;
+		pba.pba_flags = attachflags;
+		pba.pba_bus = pbnum;
+		pba.pba_bridgetag = NULL;
+		pba.pba_pc = pa->pa_pc;
+		pba.pba_intrswiz = 0;
+		memset(&pba.pba_intrtag, 0, sizeof(pba.pba_intrtag));
+		config_found_ia(self, "pcibus", &pba, pcibusprint);
+	}
+}
--- a/sys/arch/xen/conf/files.xen	Fri Oct 26 21:09:49 2007 +0000
+++ b/sys/arch/xen/conf/files.xen	Fri Oct 26 21:49:50 2007 +0000
@@ -1,4 +1,4 @@
-#	$NetBSD: files.xen,v 1.65 2007/10/17 19:58:18 garbled Exp $
+#	$NetBSD: files.xen,v 1.66 2007/10/26 21:49:51 xtraeme Exp $
 #	NetBSD: files.x86,v 1.10 2003/10/08 17:30:00 bouyer Exp 
 #	NetBSD: files.i386,v 1.254 2004/03/25 23:32:10 jmc Exp 
 
@@ -240,7 +240,7 @@
 device	pchb: pcibus, agpbus, agp_ali, agp_amd, agp_i810, agp_intel, agp_sis,
 	      agp_via
 attach	pchb at pci
-file	arch/i386/pci/pchb.c		pchb			needs-flag
+file	arch/x86/pci/pchb.c		pchb			needs-flag
 file	arch/x86/pci/pchb_rnd.c		pchb & rnd
 
 # PCI-ISA bridges